JP2005353891A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of contributing to the reduction of recesses and projections at a top of a bump electrode. <P>SOLUTION: At the time of forming a bump electrode 23 by electroplating on a pad electrode 17 exposed from a surface protective film in the pre-process of forming the pad electrode, the forming temperature of an aluminum-based wiring material is turned to 200-450°C. When the aluminum-based wiring material is formed in the temperature range, it is considered that a grain as a formation unit becomes large, the area of a grain boundary is reduced as a whole when the grain becomes large, and the recesses and projections of a surface after removing a natural oxide film on the pad electrode are reduced. Thus, the recess 24 on the end face of the top of the bump electrode formed on the pad electrode can be turned to a small value such as 1 micrometer or the like. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device provided with a bump electrode used for flip chip bonding and the like, and a method for manufacturing the same. For example, the present invention is applied to manufacture of a semiconductor device used for flip chip bonding with an anisotropic conductive film interposed therebetween. It relates to effective technology.

  As a technique for bonding a bump electrode of a semiconductor device to a terminal of a circuit board using an anisotropic conductive film, Japanese Patent Application Laid-Open No. 11-16946 discloses a conductive particle of an anisotropic conductive film on a tip surface of a bump electrode. It is described that a slightly smaller unevenness is formed to reliably capture the conductive particles and to improve the electrical bonding state.

  Similarly, Japanese Patent Application Laid-Open No. 2000-124263 describes a connection method in which a concave shape in which one or a plurality of conductive particles are formed on the surface of a bump electrode is formed to stably secure the conductive particles and prevent contact failure.

  In JP-A-4-249326 and the corresponding US Pat. No. 2,721,111, an amorphous Ni—P layer is provided on a gold plating underlayer, and the surface roughness of the amorphous Ni—P layer is reduced. A method of forming an electrogold plating pattern in which the gloss unevenness of the electroplated gold layer is improved by 0.3 micrometer or less, which is smaller than the surface roughness of the base layer, is described.

Japanese Patent Laid-Open No. 11-16946 (FIG. 5) JP 2000-124263 A (FIG. 1) JP-A-4-249326 (FIG. 1) US Pat. No. 2,721,111 (FIG. 1 (a) to FIG. 1 (e))

  This inventor examined the mounting technology of the semiconductor device using the anisotropic conductive film. For example, when an LCD (Liquid Crystal Display) driver is mounted on COG (Chip On Glass), the conductivity in the anisotropic conductive film is used to connect the electrode on the glass substrate on which the LCD is formed and the bump electrode of the semiconductor chip. Use beads. The beads are coated with a resin and are non-conductive. However, when the LCD driver is pressed against the glass substrate during mounting to crush the beads, the coating resin is broken and the corresponding bonding pad and electrode can be made conductive. If the bump electrode has a dent larger than the diameter of the bead, the bead cannot be sufficiently crushed, and a part of the electrode and the bump electrode are connected with high resistance, resulting in poor mounting. As a result of studying this depression, the bump electrode is formed by electroplating on the pad electrode exposed from the surface protective film, so that the periphery of the bump electrode is the surface protection of the opening peripheral edge of the surface protective film exposing the pad electrode. Increases the thickness of the film. As a result, a recess equivalent to at least the film thickness of the surface protective film is formed on the tip surface of the bump electrode. In addition, it was clarified that a lot of fine irregularities were formed on the surface of the depression, and the actual irregularities of the depression exceeded the film thickness of the surface protective film. This is presumably because the electroplating traces the irregularities of the plating base layer. The bump electrode plating underlayer (under bump metal) is composed of a bump electrode barrier metal for a pad electrode formed of an aluminum wiring material or the like and a seed layer used as a seed for plating growth. These are deposited by sputtering. According to the study of the present inventor, it has been found that the size of the depression at the tip of the bump electrode depends on the way of removing the oxide film from the pad electrode before forming the under bump metal. This viewpoint is not suggested in any of the above documents.

  One object of the present invention is to provide a method of manufacturing a semiconductor device that can contribute to reducing the depression at the tip of the bump electrode.

  Another object of the present invention is to provide a semiconductor device capable of obtaining a good conductive connection with a mounting substrate using an anisotropic conductive film even with a narrow pitch bump electrode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

<< 1 >>. That is, a semiconductor device manufacturing method including the following steps:
(A) forming a circuit on a semiconductor substrate and exposing a pad electrode made of an aluminum-based wiring material from a surface protective film of the formed circuit;
(B) removing the exposed surface oxide film of the pad electrode;
(C) After the step (b), a step of forming a bump electrode [consisting of an aluminum-based wiring material] on the pad electrode through an under bump metal by electroplating;
Said step (a) comprises the following substeps:
(A1) A step of forming a pad electrode made of the aluminum-based wiring material at a temperature of 200 ° C. to 450 ° C.

  When a pad electrode made of an aluminum-based wiring material is formed in the above temperature range, the grains that form the formation unit become large. When the grains become large, the area of the grain boundary decreases as a whole, and the surface unevenness after removing the oxide film decreases. It is considered to be. The said temperature range is the range confirmed by the experiment mentioned later, The upper limit may be still higher temperature. With this manufacturing method, when the surface oxide film removal of the electrode pad made of aluminum wiring material or the like is performed by RF etching or acid etching, the bump electrode tip end surface unevenness is a small value such as 1 micrometer. It is supported by experimental results that

<< 2 >>. In the method of manufacturing a semiconductor device of item <1>, the step (b) includes the following substeps:
(B1) A step of removing the surface oxide film of the pad electrode by RF etching. The RF etching means plasma etching.

  << 3 >>. In the method of manufacturing a semiconductor device according to item << 2 >>, the thickness removed by the RF etching is approximately 15 to 20 nanometers in terms of a silicon oxide film. As the amount of scraping of the pad electrode surface by RF etching is smaller, the unevenness of the bump electrode tip surface becomes smaller. This is because the surface roughness is accumulated as the impact by the ions is increased. Therefore, it is considered that the unevenness of the surface after the removal decreases as the amount of the oxide film removed decreases.

<< 4 >>. In the method of manufacturing a semiconductor device according to item << 1 >>, the step (b) includes the following sub-steps:
(B2) removing the surface oxide film of the pad electrode with an acidic aqueous solution containing hydrogen fluoride;
The optimum temperature range in the step (a1) is 300 ° C. to 450 ° C. This is based on experimental results.

  << 5 >>. In the method of manufacturing a semiconductor device according to item <1>, the aluminum-based wiring material forming the pad electrode is made of a wiring material containing copper in aluminum, and is different from a wiring material containing copper and silicon in aluminum.

  << 6 >>. In the method of manufacturing a semiconductor device according to the item << 3, 4 >>, in the step (c), the bump electrode is formed in a cubic or rectangular parallelepiped shape. Compared to so-called solder bumps with reflow, it is easy to narrow the pitch.

  << 7 >>. In the method of manufacturing a semiconductor device described in the item << 6 >>, in the step (c), a plurality of the bump electrodes are formed in parallel at a pitch of 30 μm or less.

<< 8 >>. A semiconductor device manufacturing method including the following steps according to another aspect:
(A) forming a circuit having a plurality of metal wiring layers on a semiconductor substrate and exposing a pad electrode from a surface protective film of the formed circuit;
(B) removing the exposed surface oxide film of the pad electrode;
(C) After the step (b), a step of forming a bump electrode on the pad electrode through an under bump metal by electroplating;
The pad electrode is made of a wiring material containing copper and silicon in aluminum,
Of the plurality of metal wiring layers, the same wiring layer as the pad electrode is made of a first wiring material containing copper and silicon in aluminum,
Of the plurality of metal wiring layers, a wiring layer different from the pad electrode is made of a second wiring material containing copper in aluminum and is different from the first wiring material.

  In this manufacturing method, when the pad electrode is formed of the first wiring material, the unevenness of the end surface of the bump electrode is larger than that of the second wiring material. This is based on the experimental result that the ratio depending on the conditions of RF etching or acid etching for removing becomes small. For example, the condition dependency such as the oxide film removal thickness by RF etching is reduced. Therefore, even when the wafer process is the same and the bump electrode formation process is different, it is possible to alleviate or inhibit the state in which the size of the depression on the end face of the bump electrode greatly varies for each bump electrode formation process. In short, even if the bump electrode forming process is different, it is possible to contribute to uniforming the size of the depression at the tip of the bump electrode.

<< 9 >>. Semiconductor devices including the following configurations from different viewpoints:
(A) a circuit formed on a semiconductor substrate;
(B) a pad electrode exposed from a surface protective film of the formed circuit;
(C) a bump electrode formed on the exposed pad electrode by gold electroplating through an under bump metal;
The thickness of the surface protective film is 0.6 micrometer or more, and the bump electrode has a maximum height dimension of a peripheral portion that overlaps the surface protective film and a height of an inner portion that does not overlap the surface protective film. The difference from the average value is 1 micrometer or less. Further, each of the bump electrodes has a cubic or rectangular parallelepiped shape, a plurality of the bump electrodes are arranged in parallel, and the parallel pitch is 30 micrometers or less.

  Even with the above semiconductor device in which the parallel pitch of the bump electrodes is a narrow pitch of 30 μm or less, a conductive connection with the mounting substrate using an anisotropic conductive film having a conductive bead diameter of about 2 μm Can be obtained.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a method for manufacturing a semiconductor device that can contribute to reducing the size of the recess at the tip of the bump electrode.

  Even if it is a bump electrode of a narrow pitch, the semiconductor device which can obtain a favorable conductive connection with the mounting board | substrate using an anisotropic conductive film is realizable.

  FIG. 1 is a partial cross-sectional view of a semiconductor device having bump electrodes. The semiconductor device 1 shown in the figure is not particularly limited, but has four aluminum wiring layers as wiring formation layers, and has an insulated gate field effect transistor (hereinafter also simply referred to as a MOS transistor) as an active element. A required circuit is formed on the semiconductor substrate 2. In the figure, one MOS transistor Tr is representatively shown as an active element. 2 is a p-type semiconductor substrate, 6 is a channel region, 7 and 8 are n-type semiconductor regions which are used as source and drain electrodes, 9 is a gate oxide film, 10 is a gate electrode, and 11 is a sidewall spacer. The signal wirings 12 and 13 connected to the source / drain electrodes are exemplified as the first aluminum wiring layer, the signal wirings 14 and 15 are exemplified as the second aluminum wiring layer, and the third layer The signal wiring 16 is exemplified as the aluminum wiring layer, and the pad electrode 17 is exemplified as the fourth aluminum wiring layer. Each wiring layer is insulated by an interlayer insulating film 18 made of silicon oxide or the like. Wiring connections between wiring layers are made through through holes 19.

  The surface of the semiconductor device 1 is covered with a surface protective film (final passivation film). The surface protective film is formed of, for example, a silicon nitride film 21 and a polyimide resin (PiQ) film 22. Instead of the silicon nitride film 21 and the polyimide resin (PiQ) film 22, a phosphorus glass (PSG) film or the like may be employed.

  The surface protective film is removed from the surface of the pad electrode 17, and a bump electrode 23 is formed by electroplating through the under bump metal 20 in the opening from which the surface protective film has been removed. The under bump metal 20 includes a barrier metal layer 20A for the metal pad 17 and a seed metal layer 20B used as a seed for plating growth. The bump electrode 23 is formed in a cubic or rectangular parallelepiped shape by gold plating. TiW, Ti, or the like can be used for the barrier metal layer 20A. Au or Pd can be used for the seed metal layer 20B.

  A recess 24 is formed on the tip surface of the bump electrode 17. The recess 24 is formed by tracing the base shape of the plating due to the property of isotropic growth of plating. For example, if the height of the side surface of the bump electrode 23 is H, the height of the central portion of the bump electrode is h, and the depth of the recess 24 is G, in principle, H is equal to h, and G is the under bump metal 20. It has a relationship that is almost equal to the thickness of In short, the recess 24 means the surface portion of the bump electrode located immediately above the portion that does not overlap the surface protective films 21 and 22. The depression may be grasped as a step on the tip surface of the bump electrode 23.

  In practice, a large number of fine irregularities are formed on the surface of the recess 24 as illustrated in FIG. In the present specification, the size of the recess 24 is defined as follows. That is, assuming that the maximum height dimension of the bump electrode 23 with respect to the reference position BH is A, the maximum height of the recess 24 from the reference position BH is B, and the minimum height of the recess 24 from the reference position BH is C. The size (depth) G of the recess 24 is given by G = A− (B + C) / 2. For example, when A = 15.8 micrometers (μm), B = 15.2 μm, and C = 14.7 μm, G = 0.85 μm.

  In the semiconductor integrated circuit 1, it is considered to reduce the size of the recess 24. Here, attention is paid to the process performed before forming the under bump metal to reduce the size of the recess 24, that is, the temperature at which the pad electrode is formed and the process of removing the natural oxide film from the pad electrode 17. To do. Removal of the natural oxide film from the pad electrode 17 is an essential process for maintaining good adhesion to the under bump metal 20 formed thereon. In removing the natural oxide film, a method that can contribute to suppressing the roughening of the removal surface as much as possible was adopted. The method is described below.

  FIG. 3A shows a partial cross-sectional structure corresponding to FIG. 1 in the semiconductor device 1 in a wafer state in which the surface protective film is completed. The semiconductor device 1 is accepted in the bump electrode forming process in this state. In the bump electrode forming step, first, the natural oxide film is removed from the pad electrode 17. This natural oxide film removing process is a method in which the surface of the wafer is RF-etched with inert gas ions, or a method in which the wafer is etched with an acid mixture containing hydrofluoric acid.

  In the RF etching method, for example, argon ions collide with the pad electrode 17 in a high vacuum to remove the oxide film on the surface. At this time, the pad electrode 17 is made of a wiring material (aluminum / copper wiring material) containing copper in aluminum, and the wiring material is different from a wiring material (aluminum / copper / silicon wiring material) containing copper and silicon in aluminum. Made of material. The wiring formation temperature is 200 ° C. to 450 ° C. For example, a sputtering method or a vapor deposition method may be used for forming the wiring. The formation temperature is the surface temperature of the semiconductor device. The natural oxide film of the pad electrode 17 is about 17 μm, and a removal thickness for removing it by the sputtering method is, for example, 15 nm or 20 nm in terms of a silicon oxide film. In this specification, the formation temperature of the aluminum-based wiring material may be grasped as the set temperature of the semiconductor device itself, particularly the surface thereof.

In the etching method using the acidic solution, the surface of the pad electrode 17 is etched using, for example, an aqueous solution containing hydrogen fluoride (HF), ammonium fluoride (NH ₄ F), and acetic acid (CH ₃ COOH).

FIG. 4A shows, as an experimental example, the relationship between the formation temperature of the aluminum-based wiring material when the bump electrode 23 is formed by gold plating, the natural oxide film removal treatment condition, and the size of the recess 24. In the example shown in the figure, a pad electrode 17 made of an aluminum / copper wiring material is used. The first experimental example indicated by the trend line of L1 is a case where 25 nm in terms of silicon oxide film is removed by collision of argon ions. The second experimental example indicated by the trend line of L2 is a case where 20 nm in terms of silicon oxide film is removed by collision of argon ions. The third experimental example indicated by the trend line of L3 is a case where 15 nm in terms of silicon oxide film is removed by collision of argon ions. A fourth experimental example indicated by a trend line of L4 is a case where etching is performed using an aqueous solution containing hydrogen fluoride (HF), ammonium fluoride (NH ₄ F), and acetic acid (CH ₃ COOH).

  From the experimental results shown in FIG. 4A, the size G of the dent was smaller as the formation temperature of the aluminum-based wiring material was higher. This is because when the temperature at which the aluminum-based wiring material is formed increases, the grains that form the unit increase, and when the grains increase, the area of the grain boundary decreases as a whole, and the unevenness of the surface after removal of the oxide film is reduced. This is thought to be because it decreases. In addition, the size G of the dent became smaller as the amount of scraping by RF etching was smaller. This is presumably because surface roughness increases as the ion bombardment is applied, so that the smaller the removal amount, the less the surface irregularities after removal. For example, when the target size G of the recess 24 of the bump electrode 23 is set to 1 μm or less, the formation temperature of the aluminum-based wiring material is 300 ° C. or more in the etching method using an acidic solution, and the removal amount is oxidized in the RF etching method As represented by 20 nm or less in terms of silicon film, the result is that it is better that the aluminum oxide film is smaller within the range that can be removed. The natural oxide film removal process of the pad electrode 17 described with reference to FIG. 3A takes the condition into consideration.

  FIG. 4B shows the relationship between the formation temperature of the aluminum-based wiring material when the bump electrode 23 is formed by gold plating, the natural oxide film removal treatment condition, and the size of the recess 24 based on another experimental result. The example shown in the figure is different from the experimental condition of FIG. 4A in that a pad electrode 17 made of an aluminum / copper / silicon wiring material is used. In this experimental example, there was no great difference in the amount of depression G due to the difference in processing such as the amount of cutting. This is because the pad electrode 17 made of aluminum / copper / silicon wiring material is harder than the pad electrode made of aluminum / copper wiring material. This is thought to be because it is difficult to exert a positive influence. The effect of temperature has the same tendency as in FIG. 4A. From this experimental result, if the pad electrode 17 made of an aluminum / copper / silicon wiring material is used, the size of the recess 24 of the bump electrode 23 is determined by RF etching or acid etching for removing the surface oxide film of the electrode pad 17. Even when the wafer process is the same and the formation process of the bump electrode 23 is different, the size of the depression 24 of the bump electrode 23 varies greatly for each formation process of the bump electrode 23. Can be mitigated or deterred.

  3B to 3F are cross-sectional views for explaining the manufacturing process up to the formation of the bump electrode subsequent to the removal process of the natural oxide film on the pad electrode 17 in order.

  After the removal process of the natural oxide film, as shown in FIG. 3B, the under bump metal 20 is deposited on the entire surface of the wafer by sputtering. For example, as the amber bump metal 20, Ti is adopted for the barrier metal layer 20A, and Pd is adopted for the seed metal layer 20B. After that, as shown in FIG. 3C, for example, a positive type photoresist is applied on the under bump metal 20 and exposed except for a portion where the bump electrode is formed, leaving a resist pattern 25 in the unexposed portion. Next, as shown in FIG. 3D, gold is plated on the under bump metal 20 exposed from the remaining resist pattern 25 by electroplating to form the bump electrode 23. Next, the resist pattern 25 is removed from the surface of the wafer (FIG. 3E), and the under bump metal 20 exposed on the surface is removed by etching (FIG. 3F). Thereafter, the formed bump electrode 20 is annealed to reduce the hardness.

  FIG. 5 illustrates a mounting form of the semiconductor device. In the figure, the semiconductor device 1 is a liquid crystal driver LSI. A thin film transistor (TFT) type liquid crystal display 31 is formed on the glass substrate 30, and a number of wiring patterns 32 for mounting connected to the drive terminals of the liquid crystal display 31 are formed. A corresponding bonding pad of the semiconductor device 1 is electrically coupled to the mounting wiring pattern 32 with an anisotropic conductive film interposed therebetween. This type of implementation is referred to as COG implementation.

  FIG. 6A shows a state before the completion of mounting in which an anisotropic conductive film is interposed between the wiring pattern 32 for mounting and the corresponding bonding pad of the semiconductor device 1, and FIG. 6B shows the state after the completion of mounting. The status is indicated.

  The anisotropic conductive film 34 is not particularly limited, but has a two-layer structure of an adhesive layer 34A and a conductive particle layer 34B. A single layer of only the conductive particle layer 34B may be used. In the conductive particle layer 34B, conductive beads 35 are mixed in the resin as a large number of conductive particles. The conductive bead 35 has a resin core at the center, is covered with a metal shell, and is further covered with a resin shell. When a predetermined pressure is applied from the outside, The resin shell is broken and the metal shell is exposed. When the metal shell is exposed, the outer diameter of the conductive beads 35 is naturally reduced. In the case of a single layer structure, the resin of the conductive particle layer 34B also serves as an adhesive. Therefore, the resin characteristics of the conductive particle layer 34B are tuned so that the two-layer structure has a higher conductive particle capture rate by the bump electrode than the single-layer structure.

  When the semiconductor device 1 is pressed from the state shown in FIG. 6A, the adhesive layer 34A flows to the side by being pressed by the bump electrode 23, and the conductive beads 35 of the conductive particle layer 34B are connected to the front end surface of the bump electrode 23 and the mounting wiring pattern. When the metal shell of the conductive bead 35 is brought into contact with both the front end surface of the bump electrode 23 and the mounting wiring pattern 32, electrical connection between them is achieved and adhesion is achieved. The mounting state of the semiconductor device 1 on the glass substrate 30 is maintained by the adhesive force of the agent layer 34A.

  In order for the metal shell of the conductive beads 35 to contact both the front end surface of the bump electrode 23 and the mounting wiring pattern 32 to achieve good electrical contact with all the bonding pads, the size of the recess 24 is It must be smaller than the value obtained by subtracting the collapse allowance from the diameter of the conductive beads 35. At this time, the parallel pitch of the bump electrodes of the semiconductor device 1 is 30 μm, and at such a narrow pitch, the outer diameter of the conductive beads 35 is optimally about 2 μm. If the outer diameter of the conductive beads 35 is too large at a narrow pitch of the bump electrodes, there is a risk that the insulation between adjacent bonding pads may be poor, and if it is too small, the conductive beads 35 are related to the size of the recess. 35 can no longer be crushed. As described in the pretreatment when forming the under bump metal 20, in the semiconductor device 1, the formation temperature of the aluminum wiring material and the removal amount of the natural oxide film with respect to the pad electrode 17 made of the aluminum wiring material are controlled. Therefore, the size G of the depression is set to 1 μm or less. Therefore, it is possible to ensure good electrical connection between the semiconductor device 1 and the liquid crystal display 31 in COG mounting using the anisotropic conductive film 34 having the conductive beads 35 having a particle diameter of approximately 2 μm.

  In the semiconductor device 1, when the target recess size G is actually determined, the oxide film is removed by the formation temperature of the aluminum-based wiring material, the RF etch amount, and the etching amount by acid predicted from the experimental result of FIG. 4A. What is necessary is just to process. For example, when the target recess size G is 1 μm, etching is performed using the mixed acidic solution at an aluminum wiring material forming temperature of 400 ° C., or an aluminum wiring material forming temperature of 300 ° C. The oxide film may be removed by performing RF etching of 20 nm in terms of silicon oxide film with C. The experimental result of FIG. 4A is that the protective film thickness is 0.6 μm in the semiconductor device manufactured in the 0.18 μm process generation. In addition, the protective film thickness is in the semiconductor device manufactured in the 0.18 μm process generation. If the thickness is larger than 0.6 μm, the formation temperature of the aluminum-based wiring material may be further increased to reduce the oxide film removal amount to suppress the occurrence of unevenness. Moreover, since the wiring pitch is wide in the semiconductor device manufactured in the 0.35 μm process generation, the arrangement pitch of the bump electrodes may be large according to this, and even if the particle size of the conductive beads is large, the gap between the adjacent bump electrodes is large. Since there is no risk of leakage, the recess may be larger than in the case of a semiconductor device manufactured in a 0.18 μm process generation. In such a case, the temperature range applied to the formation of the aluminum-based wiring material may be as wide as 200 ° C. to 450 ° C., or the natural oxide film removal amount on the pad electrode by etching may be increased. . In short, the etching conditions for removing the natural oxide film may be rough. Regarding the formation temperature condition of the aluminum-based wiring material, if it is not limited to the advanced process generation, it is 200 degrees C to 400 degrees C. If it is limited to the advanced process generation such as 0.18 μm process generation, it is 300 degrees. Considering future process generations such as C to 450 ° C. and 0.13 μm process generation, the conditions may be narrowed to the high temperature side such as 350 ° C. to 450 ° C.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the type of the surface protective film of the semiconductor device is not limited to the above, and can be appropriately changed such as omitting PiQ. The removal of the natural oxide film by RF etching can be replaced with other dry cleaning methods. The pad electrode made of an aluminum / copper wiring material may contain other metals other than Si. The blending of copper is not limited to 1%. The arrangement pitch of the bump electrodes is not limited to 30 μm. For example, the arrangement pitch may be 40 μm or less. The thickness of the surface protective film may be 1.3 μm, 0.6 μm, or any other thickness. The target value of the depression may be 1.5 μm, 1.0 μm, 0.8 μm, or other values. The semiconductor device according to the present invention is not limited to the LCD driver LSI, and can be applied to various semiconductor devices such as a microcomputer, an accelerator, and a memory.

It is a fragmentary longitudinal cross-sectional view of the semiconductor device which has a bump electrode. It is a wave form diagram for demonstrating the definition of the level | step difference dimension of the hollow in a bump electrode front end surface. It is a longitudinal cross-sectional view corresponding to FIG. 1 in the semiconductor device of the wafer state in which the surface protective film was completed. It is a longitudinal cross-sectional view corresponding to FIG. 1 which shows the state which deposited the under bump metal on the whole surface of the wafer surface by sputtering following the removal process of the natural oxide film with respect to a pad electrode. 2 is a longitudinal sectional view corresponding to FIG. 1 showing a state in which a positive photoresist is applied on an under bump metal and a resist pattern is left. FIG. It is a longitudinal cross-sectional view corresponding to FIG. 1 which shows the state which plated gold by the electroplating on the under bump metal exposed from a register pattern, and formed the bump electrode. It is a longitudinal cross-sectional view corresponding to FIG. 1 which shows the state which removed the resist pattern 25 from the surface of the wafer. It is a longitudinal cross-sectional view corresponding to FIG. 1 which shows the state which removed the under bump metal exposed on the surface by etching. It is explanatory drawing of the experimental result which shows the relationship between the formation temperature of the aluminum-type wiring material when a bump electrode is formed by gold plating, the natural oxide film removal process conditions, and the dimension of a hollow. It is explanatory drawing of another experimental result which shows the relationship between the formation temperature of the aluminum-type wiring material when forming a bump electrode by gold plating, the natural oxide film removal process conditions, and the dimension of a hollow. It is a front view which illustrates the mounting form of a semiconductor device. It is a longitudinal cross-sectional view which shows the state before the completion of mounting which interposed the anisotropic conductive film between the wiring pattern for mounting, and the corresponding bonding pad of a semiconductor device. It is a longitudinal cross-sectional view which shows the state after the completion of mounting which interposed the anisotropic conductive film between the wiring pattern for mounting, and the corresponding bonding pad of a semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 12, 13 Signal wiring formed in the first aluminum wiring layer 14, 15 Signal wiring formed in the second aluminum wiring layer 16 In the third aluminum wiring layer Signal wiring formed 17 Pad electrode formed on the fourth aluminum wiring layer 20 Under bump metal 20A Barrier metal layer 20B Seed metal layer 21 Silicon nitride film constituting the surface protective film 22 Polyimide constituting the surface protective film Resin film 23 Bump electrode 24 Dimple 30 Glass substrate 31 Liquid crystal display 32 Wiring pattern for mounting 34 Anisotropic conductive film 34A Adhesive layer 34B Conductive particle layer 35 Conductive bead

Claims (9)

A semiconductor device manufacturing method including the following steps:
(A) forming a circuit on a semiconductor substrate and exposing a pad electrode made of an aluminum-based wiring material from a surface protective film of the formed circuit;
(B) removing the exposed surface oxide film of the pad electrode;
(C) After the step (b), a step of forming a bump electrode on the pad electrode through an under bump metal by electroplating;
Said step (a) comprises the following substeps:
(A1) A step of forming a pad electrode made of the aluminum-based wiring material at a temperature of 200 ° C. to 450 ° C. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (b) includes the following sub-steps:
(B1) A step of removing the surface oxide film of the pad electrode by RF etching. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a thickness removed by the RF etching is about 15 to 20 nanometers in terms of a silicon oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (b) includes the following sub-steps:
(B2) removing the surface oxide film of the pad electrode with an acidic aqueous solution containing hydrogen fluoride;
The temperature in the step (a1) is 300 ° C. to 450 ° C. In the manufacturing method of the semiconductor device according to claim 1,
The aluminum-based wiring material constituting the pad electrode is made of a wiring material containing copper in aluminum, and is different from a wiring material containing copper and silicon in aluminum. 5. The method of manufacturing a semiconductor device according to claim 3, wherein in the step (c), the bump electrode is formed in a cubic or rectangular parallelepiped shape. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step (c), a plurality of the bump electrodes are formed in parallel at a pitch of 40 microns or less. A semiconductor device manufacturing method including the following steps:
(A) forming a circuit having a plurality of metal wiring layers on a semiconductor substrate and exposing a pad electrode from a surface protective film of the formed circuit;
(B) removing the exposed surface oxide film of the pad electrode;
(C) After the step (b), a step of forming a bump electrode on the pad electrode through an under bump metal by electroplating;
The pad electrode is made of a wiring material containing copper and silicon in aluminum,
Of the plurality of metal wiring layers, the same wiring layer as the pad electrode is made of a first wiring material containing copper and silicon in aluminum,
Of the plurality of metal wiring layers, a wiring layer different from the pad electrode is made of a second wiring material containing copper in aluminum and different from the first wiring material. A semiconductor device including the following configuration:
(A) a circuit formed on a semiconductor substrate;
(B) a pad electrode exposed from a surface protective film of the formed circuit;
(C) a bump electrode formed on the exposed pad electrode by gold electroplating through an under bump metal;
The thickness of the surface protective film is 0.6 micrometer or more,
The bump electrode, the difference between the maximum height dimension of the peripheral edge overlapping the surface protective film and the average value of the height of the inner portion that does not overlap the surface protective film is 1 micrometer or less,
Further, each of the bump electrodes has a cubic shape, and a plurality of the bump electrodes are arranged in parallel, and the parallel pitch is 30 micrometers or less.

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