JP2005353878A5 - - Google Patents

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Publication number
JP2005353878A5
JP2005353878A5 JP2004173745A JP2004173745A JP2005353878A5 JP 2005353878 A5 JP2005353878 A5 JP 2005353878A5 JP 2004173745 A JP2004173745 A JP 2004173745A JP 2004173745 A JP2004173745 A JP 2004173745A JP 2005353878 A5 JP2005353878 A5 JP 2005353878A5
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JP
Japan
Prior art keywords
mold
runner
resin
lead frame
cavity
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Application number
JP2004173745A
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Japanese (ja)
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JP2005353878A (en
JP4454399B2 (en
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Priority to JP2004173745A priority Critical patent/JP4454399B2/en
Priority claimed from JP2004173745A external-priority patent/JP4454399B2/en
Publication of JP2005353878A publication Critical patent/JP2005353878A/en
Publication of JP2005353878A5 publication Critical patent/JP2005353878A5/ja
Application granted granted Critical
Publication of JP4454399B2 publication Critical patent/JP4454399B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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タブとインナーリードとを一組の単位フレームとし、これが複数のマトリックス状に配列されたリードフレームを準備する工程と、A step of preparing a lead frame in which a tab and an inner lead are set as a unit frame, and this is arranged in a plurality of matrices, and
上下で一対となる金型であり、前記単位フレーム毎の樹脂封止領域となるキャビティ部の型と、各キャビティ部の型に対応して設けられた複数のゲート部の型と、前記複数のゲート部に接続されるランナ部の型と、前記ランナ部の型より上下金型の空間の高さが薄く、前記ランナ部の型に接続されるサブランナ部の型とを有する、前記一対の金型を準備する工程と、A pair of upper and lower molds, a cavity part mold serving as a resin sealing region for each unit frame, a plurality of gate part molds provided corresponding to each cavity part mold, The pair of molds, comprising: a runner part mold connected to the gate part; and a sub-runner part mold connected to the runner part mold, wherein a space of the upper and lower molds is thinner than the runner part mold. Preparing the mold,
前記リードフレームに対して前記金型を設置し、前記サブランナ部の型と前記ランナ部の型と前記ゲート部の型を介して前記キャビティ部の型に樹脂を流入する工程とを有することを特徴とする半導体装置の製造方法。And a step of installing the mold with respect to the lead frame, and injecting resin into the cavity part mold through the sub-runner part mold, the runner part mold, and the gate part mold. A method for manufacturing a semiconductor device.
タブとインナーリードを含む領域となるキャビティ部と、前記キャビティ部に接続する領域となるゲート部と、前記ゲート部に接続する領域となり、所定の外力によって破断することが可能な形状を備えたランナ部とを有するリードフレームを準備する工程と、
前記キャビティ部を樹脂で封止する際の治具であり、前記キャビティ部と前記ゲート部と前記ランナ部にそれぞれ対応する樹脂の流入経路の型と、樹脂の供給源となるカル部の型と、前記カル部と前記ランナ部の間の樹脂の流入経路に対応し、前記ランナ部との接続部分に縊れ形状を備えたサブランナ部の型とを有する金型を準備する工程と、
前記リードフレームに対して前記金型を設置し、前記カル部の型から前記キャビティ部の型に向けて樹脂を流入する工程と、
前記リードフレームから前記金型を取り外した際に、前記リードフレームの前記ランナ部の残存樹脂に連結されている前記サブランナ部および前記カル部の残存樹脂を、前記サブランナ部の残存樹脂に形成された前記縊れ形状の位置で除去する工程と、
前記ランナ部の残存樹脂を含むリードフレームを、切断装置に搬送する工程と、
前記切断装置を用いて、前記ランナ部の残存樹脂と前記ゲート部の残存樹脂を除去する工程とを有することを特徴とする半導体装置の製造方法。
A cavity portion that is a region including a tab and an inner lead, a gate portion that is a region that is connected to the cavity portion, and a runner that is a region that is connected to the gate portion and can be broken by a predetermined external force Preparing a lead frame having a portion;
A jig for sealing the cavity part with resin, a mold of a resin inflow path corresponding to the cavity part, the gate part, and the runner part, and a mold of a cull part serving as a resin supply source, A step of preparing a mold having a mold of a sub-runner portion corresponding to a resin inflow path between the cull portion and the runner portion and having a twisted shape at a connection portion with the runner portion;
Installing the mold on the lead frame, and flowing the resin from the cull part mold toward the cavity part mold;
When the mold is removed from the lead frame, the residual resin of the sub-runner portion and the cull portion connected to the residual resin of the runner portion of the lead frame is formed in the residual resin of the sub-runner portion. Removing at the position of the drooping shape;
Conveying the lead frame containing the residual resin of the runner part to a cutting device;
A method for manufacturing a semiconductor device, comprising: using the cutting device to remove residual resin in the runner portion and residual resin in the gate portion.
JP2004173745A 2004-06-11 2004-06-11 Manufacturing method of semiconductor device Expired - Fee Related JP4454399B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004173745A JP4454399B2 (en) 2004-06-11 2004-06-11 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004173745A JP4454399B2 (en) 2004-06-11 2004-06-11 Manufacturing method of semiconductor device

Publications (3)

Publication Number Publication Date
JP2005353878A JP2005353878A (en) 2005-12-22
JP2005353878A5 true JP2005353878A5 (en) 2007-07-26
JP4454399B2 JP4454399B2 (en) 2010-04-21

Family

ID=35588077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004173745A Expired - Fee Related JP4454399B2 (en) 2004-06-11 2004-06-11 Manufacturing method of semiconductor device

Country Status (1)

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JP (1) JP4454399B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5054923B2 (en) * 2006-01-23 2012-10-24 Towa株式会社 Resin sealing molding method for electronic parts
JP7121835B1 (en) 2021-06-25 2022-08-18 Towa株式会社 RESIN MOLDING APPARATUS AND METHOD OF MANUFACTURING RESIN MOLDED PRODUCT

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