JP2005353274A - Semiconductor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor circuit configured of MOS-FETs capable of attaining both a high-speed switching characteristic and a small sub threshold current characteristic. <P>SOLUTION: This semiconductor circuit having a logic circuit 1 composed of MOS-FET Q1 and Q2 is provided with voltage supplying means 15 and 13 for supplying voltages V<SB>pp</SB>and V<SB>bb</SB>different from backgate bias voltages V<SB>cc</SB>and V<SB>SS</SB>of the MOS-FET Q1 and Q2 and a switching means 10 for switching the backgate bias voltages of the MOS-FET Q1 and Q2 to the voltages V<SB>cc</SB>and V<SB>SS</SB>and the voltages V<SB>pp</SB>and V<SB>bb</SB>different from the voltages V<SB>cc</SB>and V<SB>SS</SB>. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an improvement of a semiconductor circuit using a MOS-FET.

FIG. 23 is a circuit diagram showing a complementary MOS inverter used in a conventional semiconductor circuit. A power supply potential _Vcc is applied to the source and back gate (substrate) of the pMOS FET Q1, and a ground potential V _ss is applied to the source and back gate of the nMOS FET Q2. The gates of the FET Q1 and FET Q2 are connected to each other. The connection point is set as an input node IN, the drains are connected, and the connection point is set as an output node OUT. The operation of such a complementary MOS inverter will be described below. When an H level (power supply potential V _cc ) logic signal is input from the input node IN, the FET Q1 is turned off and the FET Q2 is turned on, and an L level (ground potential V _ss = 0V) logic signal is output through the FET Q2. Output from OUT. On the other hand, when an L level (ground potential V _ss = 0V) logic signal is input from the input node IN, the FET Q1 is turned on and the FET Q2 is turned off, and an H level (power supply potential V _cc ) logic signal is passed through the FET Q1. Output from the output node OUT.

  By the way, every time the miniaturization of the semiconductor circuit advances and the size of the MOS-FET in the semiconductor circuit is scaled down, the MOS-FET has high performance. Specifically, faster switching characteristics are obtained by shortening the channel length, thinning the gate oxide film, and reducing the absolute value of the threshold potential. However, when the threshold is lowered or the channel length is shortened in order to obtain the high-speed switching characteristics of the MOS-FET, when the drain depletion layer and the source depletion layer are connected, the channel is not formed. However, punch-through in which a current flows between the source and the drain is likely to occur, and there arises a problem that the subthreshold current in the weak inversion state that flows when the gate potential does not reach the threshold value near the threshold potential increases.

  FIG. 24 is a cross-sectional structure diagram schematically showing an example of the structure of a conventional memory cell used in a MOS-DRAM. An nMOS FET 53 and a capacitor 50 are provided on a p-well 52, a word line WL is formed on the gate 54, a bit line BL is formed on the drain 56, one electrode of the capacitor 50 is formed on the source 55, and the other electrode of the capacitor 50 is formed. The cell plate 51 is connected to each. In the memory cell 57 having such a configuration, when an H level signal is applied from the word line WL to the gate 54 and the FET 53 is turned on, the charge of the capacitor 50 is transferred via the source 55, the drain 56, and the bit line BL. Writing or refreshing / reading is performed by charging / discharging. By the way, in the memory cell 57, the electric charge of the capacitor 50 is constantly leaking. This leakage is caused by the subthreshold leakage through the channel portion of the FET 53 indicated by the arrow 58 and the pn junction portion indicated by the arrow 59. There is a junction leak. Among these, when the peripheral circuit and the bit line BL are in the standby state, the junction leak is mainly, and when the peripheral circuit and the bit line BL are in the active state, the subthreshold leak is mainly.

  Further, in the MOS-DRAM, refresh (rewrite) for periodically updating the stored contents is performed to compensate for the above-described leakage loss of the memory cell 57. For this refresh, peripheral circuits and bit lines are used. There are pause refresh when the BL is in the standby state and disturb refresh when the peripheral circuit and the bit line BL are in the active state. The larger the leak, the shorter the refresh cycle and the higher the frequency. Don't be. Therefore, when the absolute value of the back gate bias potential (p-well potential), which is a normal negative potential of the FET 53, is reduced in order to reduce the junction leakage, the absolute value of the threshold potential of the FET 53 is reduced and the junction leakage is reduced. However, there arises a problem that the subthreshold leak increases.

"MT (M ulti- T hreshold) -CMOS: 1V Fast CMOS digital circuit technology, IEICE Spring Conference 1994, C-627,5-195" and "1V-High speed Digital Circuit Technology with 0.5 μm Multi- "Threshold (MT) CMOS, (Proc. IEEE ASIC Conf., 1993, pp 186-189)" describes a CMOS circuit using pMOS and nMOS FETs having two types of threshold voltages, high and low. A CMOS circuit using an MT-MOS is intended to reduce the subthreshold current flowing during standby and to increase the operation speed during active operation, and is configured as follows. That is, the logic circuit is composed of a FET having a low threshold voltage (0.3 to 0.4 V). Then, the power supply line and the sub power supply line are connected through a high threshold voltage (0.7 V) FET for blocking the leak path. Further, the ground line and the sub-ground line are connected through an FET having a high threshold voltage (0.7 V). A logic circuit is connected between the sub power line and the sub ground line.

FIG. 25 is a circuit diagram showing a conventional CMOS circuit using MT-MOS when the logic circuit is an inverter array. The connection point of the gates of the pMOS FET Q51 and the nMOS FET Q52 of the inverter I ₅ is the input node IN, and the drain connection point of the pMOS FET Q51 and the nMOS FET Q52 is the gate of the pMOS FET Q53 and the nMOS FET Q54 of the inverter I _6. Is connected to the connection point. Similarly FETQ53 and drain connection point FETQ54 of nMOS of the pMOS is connected to a connection point of the gates of the pMOS of FETQ55 and nMOS of FETQ56 inverter I _7, the drain connection point of the pMOS FETQ55 and nMOS of FETQ56 It is connected to the connection point of the gates of the pMOS of FETQ57 and nMOS of FETQ58 inverter I _8. The connection point between the drains of the pMOS FET Q57 and the nMOS FET Q58 is the output node OUT.

pMOS of FETQ51, Q53, Q55, the source of Q57 is connected to the secondary power supply line V _cc1, the source of nMOS of FETQ52, Q54, Q56, Q58 are connected to the sub-ground line V _ss1. The sub power supply line _Vcc1 is connected to the power supply line _Vcc (power supply potential: _Vcc ) via a pMOS FET Q59 to which the inverted clock signal bar φ is applied to the gate. The sub-ground line V _ss1 is connected to the ground line V _ss (ground potential: V _ss ) via an nMOS FET Q60 to which the clock signal φ is applied to the gate. FETQ59, 60 the threshold voltage of, FET Q51 constitute an inverter _{I 5, I 6, I 7} , I 8, Q52, Q53, Q54, Q55, Q56, Q57, higher than the threshold voltage of Q58.

In an inverter array using MT-MOS FETs, FETs Q59 and 60 are turned on when active. As a result, the power supply potential _Vcc is _applied to the sources of the pMOS FETs Q51, Q53, Q55, and Q57 via the sub power supply line Vcc1, and the sub-ground line V _ss1 is _applied to the sources of the nMOS FETs Q52, Q54, Q56, and Q58. The ground potential V _ss is applied through the via.

Further, the FETs Q59 and 60 are turned off during standby. As a result, the power supply potential V _cc is not _applied to the sub power supply line V _cc1 , and the ground potential V _ss is not _applied to the sub ground line V _ss1 . Therefore, the current path between the power source and the ground is cut, and the subthreshold current is also reduced.

Since the threshold voltages of the FETs Q51, Q52, Q53, Q54, Q55, Q56, Q57, and Q58 constituting the inverters I ₅ , I ₆ , I ₇ , and I ₈ are small, high speed operation is possible when active. However, when a subthreshold current flows in the inverter train during standby, the potential of the sub power supply line _Vcc1 may decrease or the potential of the sub ground line _Vss1 may increase. Then, at the time of transition from the standby state to the active state, the potential of the sub power supply line V _{cc1 and} the potential of the sub ground line V _ss1 may cause a large switching delay, or the logic may change in the worst case. There is. Such a phenomenon is remarkable when the active period is long.

FIG. 26 is a circuit diagram showing a conventional word driver. In the word driver WD, a pMOS FET Q61 and an nMOS FET Q62 are connected in series between a power supply line V _pp connected to a boost power supply and the ground, and a decoder signal X is input to the gates of the pMOS FET Q61 and the nMOS FET Q62. The word line WL is connected to the connection point of the drains of the pMOS FET Q61 and the nMOS FET Q62. The n word drivers WD having such a configuration are arranged in parallel in the vertical direction and m columns in the horizontal direction (WD _{11 to} WD _mn ). Then, when the decoder signal X ₁₁ is input to the selected word driver WD (for example, the word driver WD ₁₁ ), the word line WL becomes active.

  In such a configuration, a subthreshold current flows in the word driver WD in the standby state, which is a problem in realizing low power consumption. Japanese Patent Application Laid-Open No. 5-210976 discloses a word driver provided with switching means (FET) for switching power supply potential supply to the pMOS FET Q61 of the word driver WD so as not to flow a subthreshold current. Yes.

Furthermore, "Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's, Symposium on VLSI Circuit Dig. Of Tech. Papers, pp. 45-46" switches the power supply potential supply of the pMOS FET Q61 of the word driver WD in columns. A hierarchical word driver having switching means (FET) provided between the switching means and the word driver is described. FIG. 27 is a circuit diagram showing this word driver. Power line V _pp via FETQ70 of pMOS, each word driver array B1, B2, ... FETQ71 each connected pMOS to Bm, Q72, are connected to ... Q7m. The gates of the FETs Q71, Q72,..., Q7m have column selection signals K1, K2,... Km that become L level only when the corresponding word driver columns B1, B2,. Given.

  This makes it unnecessary to increase the source potential of the pMOS FET Q61 of all the word drivers WD at the time of transition from the standby state where the source potential of the pMOS FET Q61 is slightly lowered, to include the selected word driver. Since the source potential of the word driver column only needs to be increased, current consumption at this time can be reduced.

  In the word driver shown in FIG. 27, it is necessary to raise the source potential of the pMOSFET Q61 from the slightly lowered potential to the power supply potential at the time of transition from the standby state to the active state, so that the rise of the selected word line is delayed. There's a problem.

  The present invention has been made in view of such circumstances, and by providing means for switching the back gate bias potential of the MOS-FET, it is possible to achieve both high-speed switching characteristics and small subthreshold current characteristics. It aims at providing the semiconductor circuit comprised by these.

  According to a first aspect of the present invention, there is provided a semiconductor circuit of a first conductivity type, a first well region and a second well region of a second conductivity type formed on the semiconductor substrate, and the second well. A first conductivity type well region formed in the region, a first MOS-FET having a back gate bias potential as a potential of the second conductivity type first well region, and the first conductivity type A second MOS-FET having a back-gate bias potential as the potential of the well region, and a first potential or a second potential in the first well region of the second conductivity type of the first MOS-FET. And a switch means for selectively applying the voltage as a back gate bias potential.

  According to a second aspect of the present invention, there is provided a semiconductor circuit of a first conductivity type, a first well region and a second well region of a second conductivity type formed on the semiconductor substrate, and the second well. A first conductivity type well region formed in the region, a first MOS-FET having a back gate bias potential as a potential of the second conductivity type first well region, and the first conductivity type A second MOS-FET whose back gate bias potential is the potential of the well region of the first MOS transistor, and a third gate potential or a fourth potential in the well region of the first conductivity type of the second MOS-FET. And switch means for selectively applying the bias potential.

  According to a third aspect of the present invention, there is provided a semiconductor circuit of a first conductivity type, a first well region and a second well region of a second conductivity type formed on the semiconductor substrate, and the second well. A first conductivity type well region formed in the region, a first MOS-FET having a back gate bias potential as a potential of the second conductivity type first well region, and the first conductivity type A second MOS-FET having a back-gate bias potential as the potential of the well region, and a first potential or a second potential in the first well region of the second conductivity type of the first MOS-FET. Is selectively applied as a back gate bias potential, and a third potential or a fourth potential is applied to the well region of the first conductivity type of the second MOS-FET as a back gate bias potential. Selectively applied as the second Characterized in that it comprises a switching means.

  A semiconductor circuit according to a fourth invention is the semiconductor circuit according to the third invention, wherein when the first switch means applies the first potential (or second potential) to the first MOS-FET, The switch means is characterized in that the third potential (or fourth potential) is applied to the second MOS-FET.

  A semiconductor circuit according to a fifth invention is characterized in that, in any one of the first, third, and fourth inventions, the second potential is higher than the first potential.

  A semiconductor circuit according to a sixth invention is characterized in that, in any one of the second, third, and fourth inventions, the fourth potential is lower than the third potential.

  In the first invention, the first MOS-FET having the potential of the first well region of the second conductivity type as the back gate bias potential and the potential of the well region of the first conductivity type as the back gate bias When the gates and drains of the second MOS-FETs to be potentials are connected, the switch means has a first potential in the first well region of the second conductivity type of the first MOS-FETs. Alternatively, the second potential is selectively applied as a back gate bias potential. Thereby, since the absolute value of the threshold potential of the first MOS-FET is switched, the switching characteristic and the subthreshold current characteristic can be switched.

  In the second invention, the first MOS-FET using the potential of the first conductivity type first well region as the back gate bias potential, and the potential of the first conductivity type well region as the back gate bias. When the gates and drains of the second MOS-FETs to be potentials are connected, the switching means has a third potential or a fourth potential in the well region of the first conductivity type of the second MOS-FETs. Is selectively applied as a back gate bias potential. Thereby, since the absolute value of the threshold potential of the second MOS-FET is switched, switching characteristics and subthreshold current characteristics can be switched.

  In the third aspect of the invention, the first MOS-FET that uses the potential of the first well region of the second conductivity type as the back gate bias potential, and the back gate bias of the potential of the first conductivity type well region. When the gates and drains of the second MOS-FETs to be potentials are connected, the first switch means is connected to the first well region of the second conductivity type of the first MOS-FET. The first potential or the second potential is selectively applied as a back gate bias potential, and the second switch means applies a third potential or a third potential to the well region of the first conductivity type of the second MOS-FET. The fourth potential is selectively applied as a back gate bias potential. Thereby, since the absolute value of the threshold potential of the second MOS-FET is switched, switching characteristics and subthreshold current characteristics can be switched.

  In the fourth invention, when the first switch means applies the first potential (or second potential) to the first MOS-FET, the second switch means 3 potential (or fourth potential) is applied to the second MOS-FET.

In the fifth invention, the first switch means selectively applies the first potential or a second potential higher than the first potential as the back gate bias potential of the first MOS-FET. For example, when the first potential is the power supply potential V _cc and the second potential is a higher potential V _pp , when the potential V _pp is applied to the back gate, the subthreshold current is approximately the same as the conventional one. In this way, when the power supply potential _Vcc is applied to the back gate, the absolute value of the threshold potential becomes smaller than that in the conventional case.

In the sixth invention, the second switch means selectively applies a third potential or a fourth potential lower than the third potential as the back gate bias potential of the second MOS-FET. For example, when the third potential is V _ss and the fourth potential is a ground potential V _bb lower than this, when the potential V _bb is applied to the back gate, a subthreshold current comparable to that in the prior art is obtained. In other words, when the ground voltage V _ss is applied to the back gate, the absolute value of the threshold potential becomes smaller than the conventional value.

  In the first to sixth inventions, the switching characteristics and subthreshold current characteristics of the MOS-FET can be made variable by switching the absolute value of the threshold potential of the MOS-FET. It is possible to realize a semiconductor circuit composed of a MOS-FET compatible with a small subthreshold current characteristic.

Hereinafter, the present invention will be described with reference to the drawings illustrating embodiments thereof.
Example 1.
FIG. 1 is a circuit diagram of a complementary MOS inverter showing an example of a logic circuit constituting a semiconductor circuit according to the present invention. The power source potential V _cc is applied to the FETQ1 source, and applying a ground potential V _ss to the source of FET Q2, and connecting the gate of each of the FETQ1 the FET Q2, and the connection point between the input node IN, and the drains Are connected to each other as an output node OUT. The back gate of the FET Q2 is connected to the switch circuit 10 that switches between the ground potential V _ss (= 0 V) and the potential V _bb (<0 V) lower than the ground potential V _ss , and the back gate of the FET Q1 is connected to the power supply potential V _cc It is connected to a switch circuit 11 for switching between the power supply potential V higher than _cc potential V _pp and.

Here, when the potential V _pp higher than the power supply potential V _cc and the potential V _bb lower than the ground potential V _ss are applied to the respective back gates, the FET Q1 and the FET Q2 have, for example, a subthreshold current comparable to that in the prior art. Like that. Then, when the power supply potential V _cc and the ground potential V _ss are applied to the respective back gates, the absolute value of the threshold potential becomes smaller than in the conventional case, so that the subthreshold current increases but the switching speed is made faster than in the conventional case. be able to. Thus, when the complementary MOS inverter 1 operates, if the absolute value of the threshold potential is made small in this way, the subthreshold current increases according to the proportion of the time during which the complementary MOS inverter 1 operates. If the ratio of the operating time is not large, the switching speed can be made higher than before with only a slight increase in current.

FIG. 2 is a circuit diagram showing an example of the switch circuit 10 for switching between the ground potential V _ss and the potential V _bb shown in FIG. The pMOS FETs Q3 and Q4, the nMOS FETs Q5 and Q6, and the inverter 12 constitute a level shift circuit 10a. The drains of FETQ3 and FETQ5, the drains of FETQ4 and FETQ6, and the drains and gates of FETQ5 and Q6, respectively. Is connected. The input node of the level shift circuit 10a is provided at the gate of the FET Q3, is connected to the gate of the FET Q4 via the inverter 12, and receives the input signal bar φ from the clock signal generator 14. FET Q3, the power source potential V _cc to the source and back gate of Q4 is applied, the FET Q5, Q6 source and a back gate of a low potential V _bb than the ground potential V _ss supplied from the voltage supply means 13 is applied Yes. The output node of the level shift circuit 10a is provided at the connection point between the drains of the FET Q4 and FET Q6, and this output node is connected to the input node of the changeover switch 10b.

The changeover switch 10b includes an nMOS FET Q7 and a pMOS FET Q8. The gates of the FET Q7 and the FET Q8 are connected to serve as an input node of the changeover switch 10b, and the drains are connected to serve as an output node. The source and back gate of FETQ7 is applied a lower potential V _bb than the ground potential V _ss supplied from the voltage supply means 13, to the source of FETQ8 ground potential V _ss is applied.

Figure 3 is a circuit diagram showing one example of a switch circuit 11 for switching between the power source potential V _cc and the potential V _pp shown in Fig. The pMOS FETs Q9 and Q10, the nMOS FETs Q11 and Q12, and the inverter 14 constitute a level shift circuit 11a. The drains of FETQ9 and FETQ11, the drains of FETQ10 and FETQ12, and the drains and gates of FETQ11 and Q12 are connected to each other. It is connected. The input node of the level shift circuit 11a is provided at the gate of the FET Q9, is connected to the gate of the FET Q10 via the inverter 12, and receives the input signal bar φ from the clock signal generator 14. A potential V _pp higher than the power supply potential V _cc supplied from the voltage supply means 15 is applied to the sources and back gates of the FETs Q9 and Q10, and a ground potential V _ss is applied to the sources of the FETs Q11 and Q12. The output node of the level shift circuit 11a is provided at the connection point between the drains of the FET Q9 and the FET Q11, and this output node is connected to the input node of the changeover switch 11b.

The changeover switch 11b includes a pMOS FET Q13 and an nMOS FET Q14. The gates of the FET Q13 and the FET Q14 are connected to serve as an input node of the changeover switch 11b, and the drains are connected to serve as an output node. The source and back gate of the FET Q13, a high potential V _pp than the power supply potential V _cc supplied from the voltage supply means 15 is applied, the power source potential V _cc is applied to the source of FET Q14.

  FIG. 4 is a cross-sectional structure diagram showing the well structure of the complementary MOS inverter 1 shown in FIG. An n well 19 for the power supply line and an n well 20 for the FET Q1 are formed in the upper portion of the p substrate 21, and a p well 18 for the FET Q2 is further formed in the upper portion of the n well 19 to form a triple well structure. ing. Impurity diffusion layers 11d, 25, and 23 for the back gate, source, and drain electrodes are provided in the upper portion of the n well 20, and the back gate, source, and drain are provided in the upper portion of the p well 18. Impurity diffusion layers 10d, 24, and 22 for electrodes are formed, and gates 17 and 16 are formed above n well 20 and p well 18 with an insulating layer (not shown) interposed therebetween. Yes. The switch circuits 10 and 11 are formed in wells (not shown) with fixed potentials.

The operation of such complementary MOS inverter 1 will be described below. When the complementary MOS inverter 1 does not operate, an H level signal of the control clock signal bar φ is input from the clock signal generator 14 to the switch circuits 10 and 11, and the switch circuit 10 outputs a potential V _bb lower than the ground potential V _ss. (<0) is, from the switching circuit 11 is output from the high potential V _pp is the power source potential V _cc, is applied to each FET Q2, FET Q1 of the back gate. At this time, the FETQ2 and FETQ1 have a threshold potential having a larger absolute value than that when the ground potential V _ss and the power supply potential _Vcc are applied to the respective back gates, and the subthreshold current is small. .

When the complementary MOS inverter 1 operates, the L level signal of the control clock signal bar φ is input from the clock signal generator 14 to the switch circuits 10 and 11, and the ground potential V _ss is supplied from the switch circuit 10 to the switch circuit 11. Supplies a power supply potential _{Vcc, which} is applied to the back gates of FETQ2 and FETQ1, respectively. At this time, the FETQ2 and FET Q1, than when lower than the ground potential V _ss to each of the back-gate voltage V _bb and the power source potential V _cc higher than the potential V _pp is applied, becomes smaller threshold potential of absolute value Thus, the subthreshold current increases, but the switching speed becomes faster.

When an H level (power supply potential V _cc ) logic signal is input from the input node IN, the FET Q1 is turned off and the FET Q2 is turned on, and an L level (ground potential V _ss = 0V) logic signal is output through the FET Q2. Output from OUT. On the other hand, when an L level (ground potential V _ss = 0V) logic signal is input from the input node IN, the FET Q1 is turned on and the FET Q2 is turned off, and an H level (power supply potential V _cc ) logic signal is passed through the FET Q1. Output from the output node OUT.

The operation of the switch circuit 10 shown in FIG. 2 will be described below. As described above, when the complementary MOS inverter 1 does not operate, the H level signal of the control clock signal bar φ is input from the clock signal generator 14, and at this time, the FET Q4 is turned on, the FET Q5 is turned on, and the FET Q4 is turned on. The power supply potential _Vcc is output from the level shift circuit 10a. At this time, FETQ3 and FETQ6 are turned off, and there is no short circuit in FETQ5 and FETQ4. When the power supply potential V _cc is input from the level shift circuit 10a, the changeover switch 10b turns on the FET Q7 and turns off the FET Q8, and outputs a potential V _bb lower than the ground potential V _ss through the FET Q7.

On the other hand, as described above, when the complementary MOS inverter 1 operates, the L level signal of the control clock signal bar φ is input from the clock signal generator 14, and at this time, the FET Q3 is turned on and the FET Q6 is turned on. A potential V _bb lower than the ground potential V _ss is output from the level shift circuit 10a via the FET Q6. At this time, FETQ4 and FETQ5 are turned off, and there is no short circuit in FETQ6 and FETQ3. When the potential V _bb is inputted from the level shift circuit 10a, the selector switch 10b, FET Q8 is turned on, FET Q7 via the FET Q8 turned off, the output node is a ground potential V _ss.

The operation of the switch circuit 11 shown in FIG. 3 will be described below. As described above, when the complementary MOS inverter 1 does not operate, the H level signal of the control clock signal bar φ is input from the clock signal generator 14, and at this time, the FET Q10 is turned on, the FET Q11 is turned on, and the FET Q11 is turned on. Thus, the output node of the level shift circuit 11a becomes the ground potential V _ss . At this time, FETQ9 and FETQ12 are turned off, and there is no short circuit in FETQ11 and FETQ10. When the ground potential V _ss is input from the level shift circuit 11a, the selector switch 11b, FET Q13 is turned on, FET Q14 is turned off via the FET Q13, high potential V _pp is output from the power source potential V _cc.

On the other hand, as described above, when the complementary MOS inverter 1 operates, the L level signal of the control clock signal bar φ is input from the clock signal generator 14, and at this time, the FET Q9 is turned on and the FET Q12 is turned on. through the FET Q9, high potential V _pp than the power supply potential V _cc is outputted from the level shift circuit 11a. At this time, the FET Q10 and the FET Q11 are turned off, and the FET Q12 and the FET Q9 are not short-circuited. When the potential V _pp is input from the level shift circuit 11a, the selector switch 11b, FET Q13 is turned off, via the FETQ14 become FETQ14 is turned on, the power source potential V _cc is outputted.

  In the above description, the back gate bias can be switched for both the pMOS-FET and the nMOS-FET. However, the back gate bias can be switched only for the pMOS-FET or only the nMOS-FET. You can also In that case, the configuration in which the back gate bias can be switched only for the pMOS-FET can be realized by the twin well structure of the p substrate, and the configuration in which only the nMOS-FET can be switched can be realized by the twin well structure of the n substrate, as shown in FIG. Such a triple well structure is not necessary. The voltage supply means 13 and 15 do not need to be circuits provided inside the semiconductor circuit, and may be terminals that relay a potential applied from the outside of the semiconductor circuit to the inside of the semiconductor circuit.

Example 2
5 and 6 are block diagrams showing the configuration of an example of a MOS-DRAM. The external row address signal is input to the input terminal ex. A _{0 to} ex. A _{n is} input to the input buffer 26, latched in the latch circuit 27, and then sent to the row decoder 29 via the buffer gate column 39. The row decoder 29 selects the word lines WL _{0 to} WL _m, and the selected word lines WL _{0 to} WL _m are driven by the word driver 30 to access the memory cell 57 on the word line in the memory cell array 33. The contents of the accessed memory cell 57 are transferred to the bit lines BL _{0 to} BL _k , amplified by the sense amplifiers SA _{0 to} SA _k , and simultaneously rewritten to the original memory cell 57.

On the other hand, an external column address signal input through an input terminal, an input buffer, a latch circuit, and a buffer gate column (not shown) is sent to the column decoder 31, and the column decoder 31 selects sense amplifiers SA _{0 to} SA _k. Outputs of the selected sense amplifiers SA _{0 to} SA _k amplified above are amplified by the preamplifier 34 via the I / O gate 40 and the I / O bus 41 and output from the output buffer 35.

Further, when the logic circuits of the input buffer 26, the latch circuit 27, the N-stage buffer gate 39, the row decoder 29, and the word driver 30 which are row-related operation circuits of the MOS-DRAM 42 operate, the pMOS constituting the logic circuit is operated. back gate bias potential of -FET is switch circuit 43R which receives the control clock signal bar phi ₁ to be described later, is switched from the potential V _pp from the voltage supply means 44R to the power source potential V _cc. Similarly, the back gate bias potential of nMOS-FET constituting the logic circuit, the switching circuit 45R which receives the control clock signal bar phi _1, is switched from the potential V _bb from the voltage supply means 46R to the ground potential V _ss .

On the other hand, when the logic circuits of the I / O gate 40, the preamplifier 34, the column decoder 31, the M stage buffer gate (not shown), and the output buffer 35, which are column-related operation circuits of the MOS-DRAM 42, are activated. back gate bias potential of the pMOS-FET constituting the circuit, the switching circuit 43C which receives the control clock signal bar phi ₂ to be described later, is switched from the potential V _pp from the voltage supply means 44C to the power source potential V _cc. Similarly, the back gate bias potential of nMOS-FET constituting the logic circuit, the switching circuit 45C which receives the control clock signal bar phi _2, is switched from the potential V _bb from the voltage supply means 46C to the power source potential V _ss . The switch circuits 43R and 43C are the same as the switch circuit 11 shown in FIG. 3, and the switch circuits 45R and 45C are the same as the switch circuit 10 shown in FIG.

In the above-described series of operations, the clock signal generator 49 is configured such that the enable signal inverted signal bar WE, the external RAS (Row Address Strobe) signal (external row selection signal) inverted signal bar ex. The control signals are controlled by control clock signals φ ₁ and φ ₂ which are output in response to RAS, the activation signal φ _W of the word driver 30, the activation signals φ _{S of} the sense amplifiers SA _{0 to} SA _k , and the like.

FIG. 7 is a timing chart showing the breakdown of the transmission time of the external RAS signal in each internal part of the MOS-DRAM 42. In the figure, T0 is the conversion time from the potential of the TTL circuit to the potential of the MOS circuit in the input buffer 26, T1 is the external row address latch time in the latch circuit 27, Td1 is the row in the block 28 comprising the row decoder 29 and the word driver 30. decoder setup time, TS, Tb sense amplifier SA ₀ -SA _k and memory cell selection time and the sense time in block 32 consisting of the preamplifier 34, Td2 is a delay time from the preamplifier 34 to the output buffer 35.

Here, the back gate bias potential of the MOS-FET constituting the logic circuit of the input buffer 26, the latch circuit 27, the N-stage buffer gate 39, the row decoder 29, and the word driver 30, which are row-related operation circuits of the MOS-DRAM 42. The control clock signal for switching the signal is represented by the bar φ ₁ , and the control clock signal for switching the back gate bias potential of the MOS-FET constituting the logic circuit of the preamplifier 34 and the output buffer 35 as the column-related operation circuit is represented by the bar φ _2. And In this case, for example, in the clock signal generator 49, the control clock signal bar φ ₁ is the inverted signal bar ex. Of the external RAS signal. The control clock signal bar φ ₂ is generated by the falling edge of the RAS and the rising edge of the activation signal φ _W of the word driver 30. The control clock signal φ ₂ is generated by the rising edge of the activation signal φ _S of the sense amplifiers SA _{0 to} SA _k and the external RAS signal. Inverted signal bar ex. Created at the rise of RAS.

8A to 8C show the control clock signal bar φ ₁ and bar φ ₂ generated as described above and the inverted signal bar ex. Of the external RAS signal in the MOS-DRAM 42. 3 is a timing chart showing the relationship of RAS. Times T0, T1, Td1 consumed in the input buffer 26, latch circuit 27, N-stage buffer gate 39, row decoder 29, and word driver 30, which are row-related operation circuits of the MOS-DRAM 42, that is, the input buffer 26, latch circuits 27, N stage buffer gate 39, row decoder 29, during the time T0, T1, Td1 to word driver 30 is activated (Fig. 8 (a)), the control clock signal bar phi ₁ of the L-level signal switch The signal is input to the circuit 43R and the switch circuit 45R (FIG. 8B). On the other hand, the time Tb and Td2 consumed in the preamplifier 34 and the output buffer 35 which are column-related operation circuits of the MOS-DRAM 42, that is, the operation time Tb and Td2 of the preamplifier 34 and the output buffer 35 (FIG. 8A). ), The L level signal of the control clock signal bar φ ₂ is input to the switch circuit 43C and the switch circuit 45C (FIG. 8C).

Accordingly, when the input buffer 26, the latch circuit 27, the N-stage buffer gate 39, the row decoder 29, and the word driver 30 which are row-related operation circuits of the MOS-DRAM 42 are operated, the switch circuit 43R and the switch circuit 45R supply power. The potential V _cc and the ground potential V _ss are output and applied to the back gates of the pMOS-FETs and the nMOS-FETs of the above-described operation circuits, respectively. At this time, each pMOS-FET and each nMOS-FET has an absolute value higher than that when the potential V _pp higher than the power supply potential V _cc and the potential V _bb lower than the ground potential V _ss are applied to the respective back gates. Although the threshold voltage is small, the subthreshold current increases, but the switching speed becomes faster.

On the other hand, the input buffer 26, latch circuits 27, N stage buffer gate 39, row decoder 29, when the word driver 30 is not operated, the switch circuits 43R and high potential V _pp and ground potential than the power supply potential V _cc from the switching circuit 45R A potential V _bb lower than V _ss is output and applied to the back gate of each pMOS-FET and each nMOS-FET of the above-described operation circuit. At this time, the pMOS-FET and the nMOS-FET, rather than when the power source potential V _cc and ground potential V _ss is applied to each of the back gate, has become a big threshold potential of absolute value, subthreshold The current is getting smaller.

Similarly, the preamplifier 34 is an operation circuit of a column type of MOS-DRAM 42, when the output buffer 35 is activated, the power supply potential V _cc and ground potential V _ss is output from the switch circuit 43C and the switch circuits 45C, each of the above It is applied to the back gate of each pMOS-FET and each nMOS-FET of the operating circuit. At this time, each pMOS-FET and each nMOS-FET has an absolute value higher than that when the potential V _pp higher than the power supply potential V _cc and the potential V _bb lower than the ground potential V _ss are applied to the respective back gates. Although the threshold voltage is small, the subthreshold current increases, but the switching speed becomes faster.

On the other hand, the output when the buffer 35 is not operated, from the switch circuit 43C and the switch circuit 45C outputs the power supply potential V higher than _cc potential V _pp and lower than the ground potential V _ss potential V _bb are each the pMOS of the above operating circuit -Applied to the back gate of each FET and each nMOS-FET. At this time, the pMOS-FET and the nMOS-FET, rather than when the power source potential V _cc and ground potential V _ss is applied to each of the back gate, has become a big threshold potential of absolute value, subthreshold The current is getting smaller.

Example 3 FIG.
FIG. 9 is a block diagram showing the configuration of one embodiment of the memory cell constituting the MOS-DRAM. The nMOS FET 37 and the capacitor 50 are connected by the source of the FET 37 and one electrode of the capacitor 50, the word line WL is connected to the gate of the FET 37, the bit line BL is connected to the drain, and the cell plate 51 is connected to the other electrode of the capacitor 50. Each is connected. A switch circuit 36 for switching to the back gate bias potential V _bb2 from the voltage supply means 48b or the potential V _bb1 from the voltage supply means 48a (V _bb1 <V _bb2 ) is connected to the back gate of the FET 37.

FIG. 10 is a circuit diagram showing a configuration example of the switch circuit 36, which is substantially the same as the circuit diagram of the switch circuit 10 shown in FIG. The voltage supply means 13, the ground potential V _SS , the clock signal generator 14, the control clock signal bar φ, the level shift circuit 10a, and the changeover switch 10b in FIG. 2 are respectively output from the voltage supply means 48a and the voltage supply means 48b in FIG. Potential V _bb2 , clock signal generator 49, external RAS (Row Address Strobe) signal (external row selection signal) ex. This corresponds to the RAS, level shift circuit 36a, and changeover switch 36b, and voltage supply means 48b is added to FIG. In switch circuit 36, the external RAS signal ex. When the RAS H level signal is input from the clock signal generator 49, the potential _Vbb1 is output, and the external RAS signal ex. When the RAS L level signal is input, the potential V _bb2 is output. Other operations are the same as those of the switch circuit 10 shown in FIG.

The configuration of one embodiment of the MOS-DRAM using the memory cell 38 having such a configuration is substantially the same as the block diagram showing the configuration of the MOS-DRAM shown in FIGS. In the seventh and eighth inventions, a switch circuit 36, a voltage supply means 48a, and a voltage supply means 48b are added to the structure of the above-described fifth and sixth inventions. In the MOS-DRAM 42 having such a configuration, the inverted signal bar ex. Of the external row address signal and the external RAS signal (external row selection signal). After the RAS L level signal is input to the input buffer 26, the row decoder 29 selects the word lines WL _{0 to} WL _m . When the selected word lines WL _{0 to} WL _m are given an H level signal by the word driver 30 and the FET 37 on the word lines WL _{0 to} WL _m is turned on, the charge of the capacitor 50 is charged via the bit line BL. Writing or refreshing / reading is performed by being discharged.

On the other hand, the inverted signal bar ex. Of the external RAS signal. When the RAS L level signal is input to the clock signal generator 49, the clock signal generator 49 generates the external RAS signal ex. The RAS H level signal is output to the switch circuit 36. The switch circuit 36 receives the external RAS signal ex. When the RAS H level signal is input, the output is switched from the potential V _bb2 (V _bb2 <0) to a lower potential V _bb1, and the back gate bias potential of the FET 37 constituting all the memory cells 38 of the memory cell array 33 is changed. The potential V _bb2 (V _bb2 <0) is switched to a lower potential V _bb1 . At this time, the absolute value of the threshold potential of the _{FETs 37} constituting all the memory cells 38 becomes larger than when the potential _Vbb2 is applied to the back gate, and the subthreshold leakage is reduced. Therefore, when the DRAM 42 is in the active state and the peripheral circuit and the bit line BL are in the active state, the subthreshold leak, which is the main leak at that time, can be reduced. The frequency can be lowered.

Inverted signal bar ex. Of external RAS signal (external row selection signal) to DRAM 42. When the RAS H level signal is input to the input buffer 26, the DRAM 42 becomes inactive. On the other hand, the inverted signal bar ex. Of the external RAS signal. When the RAS H level signal is input to the clock signal generator 49, the clock signal generator 49 generates the external RAS signal ex. The RAS L level signal is output to the switch circuit 36. The switch circuit 36 receives the external RAS signal ex. When RAS at L-level signal is input, outputs a switching from the potential V _bb1 to potential V _bb2, switching the back gate bias potential of FET37 which constitute all the memory cells 38 in the memory cell array 33 from the potential V _bb1 to potential V _bb2 .

At this time, the absolute value of the threshold potential of the _{FETs 37} constituting all the memory cells 38 becomes smaller than when the potential V _bb1 lower than the potential V _bb2 is applied to the back gate, and junction leakage is reduced. Accordingly, when the DRAM 42 is in an inactive state and the peripheral circuit and the bit line BL are in the standby state, junction leak, which is the main leak at that time, can be reduced. , Can reduce the frequency.

  Even in the case of a DRAM using a self-refresh memory cell that can be refreshed in the memory cell, the self-refresh state is the same as that in the pause refresh. be able to. Further, the voltage supply means in the MOS-DRAM according to the fifth to eighth inventions described above need not be a circuit provided in the MOS-DRAM, and the potential applied from the outside of the MOS-DRAM -It may be a terminal that relays into the DRAM.

Example 4
FIG. 11 is a sectional structural view showing another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention, which corresponds to FIG. FIG. 12 is a plan view of this. In this embodiment, an SOI structure nMOS and pMOS-FET are arranged in parallel on a Si substrate. An SiO ₂ layer 62 is formed on the Si substrate 61. P ⁺ layers 63 and 64 are formed in the source / drain region of the pMOS-FET Q21, and an n ⁻ channel layer 65 is formed between them. An SiO ₂ layer 71 is formed between the pMOS-FET Q21 and the nMOS-FET Q22, and the elements are isolated by the LOCOS method. N ⁺ layers 66 and 67 are formed in the source / drain region of the nMOS-FET Q22, and a p ⁻ channel layer 68 is formed between them. to the source of the pMOS-FET Q21 is applied the power source potential V _cc is adapted to the ground potential V _ss is applied to the source of the nMOS-FET Q22.

As shown in FIG. 12, the n ⁻ channel layer 65 separated from the source / drain by the gate electrode 69 is connected to the switch circuit 11 similar to that shown in FIGS. Vbody-n is applied. Switching circuit 11 can switch the body bias potential Vbody-n to a power supply potential V _cc or boosted potential V _pp. The p ⁻ channel layer 68 separated from the source / drain by the gate electrode 70 is connected to the switch circuit 10 similar to that shown in FIGS. 1 and 2, and the body bias potential Vbody-p is applied from the switch circuit 10. Applied. The switch circuit 10 can switch the body bias potential Vbody-p to the ground potential V _ss or the negative potential V _bb .

Further, an input signal is applied to the gate electrode 69 of the pMOS-FET Q21 formed on the n ⁻ channel layer 65 and the gate electrode 70 of the nMOS-FET Q22 formed on the p ⁻ channel layer 68. An output signal is output from the drain of the pMOS-FET Q21 and the drain of the nMOS-FET Q22.

The operation of the logic circuit configured as described above will be described. When this logic circuit does not operate, an H level signal of the inverted control clock signal bar φ is input from the clock signal generator 14 to the switch circuits 10 and 11, and the switch circuit 10 outputs a potential V lower than the ground potential V _{ss. bb} (<0) is higher potential V _pp than the power supply potential V _cc from the switch circuit 11 is output, each nMOS-FET Q22, the body bias potential Vbody-p of pMOS-FET Q21, is the body bias potential Vbody-n Yes. At this time, the nMOS-FET Q22 and the pMOS-FET Q21 have a threshold potential having a larger absolute value than when the ground potential V _ss and the power supply potential V _cc are applied to the respective channel layers, and the subthreshold current is It is getting smaller.

Conversely, when the logic circuit operates, the L level signal of the inverted control clock signal bar φ is input from the clock signal generator 14 to the switch circuits 10 and 11, and the ground potential V _ss is supplied from the switch circuit 10 to the switch circuit. 11 outputs a power supply potential _{Vcc, which} is a body bias potential Vbody-p and a body bias potential Vbody-n of nMOS-FET Q22 and pMOS-FET Q21, respectively. At this time, the nMOS-FET Q22 and the pMOS-FET Q21 have thresholds with smaller absolute values than when the potential V _bb lower than the ground potential V _ss and the potential V _pp higher than the power supply potential V _cc are applied to the respective channel layers. At the potential, the subthreshold current increases, but the switching speed is faster.

When an H level (power supply potential V _cc ) logic signal is input from the input node IN, the pMOS-FET Q21 is turned off and the nMOS-FET Q22 is turned on, and the L level (ground potential V _ss = 0V) via the nMOS-FET Q22. Are output from the output node OUT. On the other hand, when an L level (ground potential V _ss = 0V) logic signal is input from the input node IN, the pMOS-FET Q21 is turned on, the nMOS-FET Q22 is turned off, and the H level (power supply potential V _cc ) is output from the output node OUT.

As described above, in this embodiment, both high-speed switching characteristics and small subthreshold current characteristics can be achieved. Further, in the element configuration shown in FIG. 4, since the bias voltage of the bulk structure well having a relatively large capacity is changed, the switching time is relatively long and the accompanying charge / discharge current is relatively large. However, in the element configuration shown in FIG. 11, the capacitance of the n ⁻ channel layer 65 and the p ⁻ channel layer 68 is smaller than the capacitance of the well described above, so that the switching time can be shortened and the accompanying charge / discharge current is also relatively reduced. be able to. Furthermore, by fixing the body voltage, the kink of the SOI transistor is eliminated and the pressure resistance is improved.

Embodiment 5 FIG.
FIG. 13 is a cross-sectional structure diagram showing still another embodiment of a logic circuit constituting a semiconductor circuit according to the present invention. In this embodiment, element isolation between the pMOS-FET Q21 and the nMOS-FET Q22 is performed by the field shield (FS) method instead of the LOCOS method. That is, on both outer sides of the p ⁺ layers 63 and 64 of the pMOS-FET Q21, by forming FS layers 74 and 74 made of polysilicon and applying 0V, the channel is turned off to form n ⁻ layers 72 and 73. ing. Further, on both outer sides of the n ⁺ layers 66 and 67 of the nMOS-FET Q22, by forming FS layers 74 and 74 and applying a negative bias, the channel is turned off to form p ⁻ layers 75 and 76. A p ⁺ layer 77 is formed between the n ⁻ layer 73 and the p ⁻ layer 75.

The body bias potential Vbody-n is applied from the switch circuit 11 to the n ⁻ channel layer 65 and the n ⁻ layers 72 and 73. The body bias potential Vbody-p is applied from the switch circuit 10 to the p ⁺ layer 77, the p ⁻ channel layer 68, and the p ⁻ layers 75 and 76. The power supply potential _Vcc is applied to the FS layers 74 and 74 of the pMOS-FET Q21, and the ground potential V _ss is applied to the FS layers 74 and 74 of the nMOS-FET Q22. Other configurations are the same as those shown in FIG. 11, and the description thereof will be omitted by assigning the same reference numerals.

Also in this embodiment, the same effect as that of the above-described embodiment can be obtained. In this embodiment, the layout for the body bias potential as shown in FIG. 12 is not required, and the potential can be fixed in the n ⁻ layers 72 and 73 or the p ⁻ layers 75 and 76 below the FS layer 74. An n ⁺ layer may be formed between the n ⁻ layer 73 and the p ⁻ layer 75, and a body bias potential Vbody-n may be applied to the n ⁺ layer.

Example 6
FIG. 14 is a sectional structural view showing still another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention. In this embodiment, element isolation is performed by the FS method and the LOCOS method. That is, an SiO ₂ layer 71 is formed in place of the p ⁺ layer 77 shown in FIG. A body bias potential Vbody-n is applied from the switch circuit 11 to the n ⁻ channel layer 65 and the n ⁻ layers 72 and 73. A body bias potential Vbody-p is applied from the switch circuit 10 to the p ⁻ channel layer 68 and the p ⁻ layers 75 and 76. Other configurations are the same as those shown in FIG. The present invention can also be applied to the case where element isolation is performed by the FS method and the LOCOS method as described above, and the same effects as those of the above-described embodiments can be obtained.

Example 7
FIG. 15 is a sectional structural view showing still another embodiment of the logic circuit constituting the semiconductor circuit according to the present invention. In this embodiment, an nMOS-FET Q23 having the same configuration as that of the nMOS-FET Q22 is formed in place of the pMOS-FET Q21, and the nMOS-FET is juxtaposed. An n ⁺ layer 78 is formed between the nMOS-FETs Q22 and Q23. The ground potential V _ss is applied to the FS layers 74, 74, 74, 74 of the nMOS-FETs Q22, Q23 and the p ⁻ layers 75, 76 and the p ⁻ channel layer 68 of the nMOS-FET Q22, and the n ⁺ layer 78 is supplied with power. The potential V _cc is applied. The switch circuit 10 is connected to the p ⁻ layers 75 and 76 and the p ⁻ channel layer 68 of the nMOS-FET Q23. Other configurations are the same as those shown in FIG. The present invention can also be applied to the case where such nMOS-FETs are juxtaposed, and the same effects as those of the above-described embodiments can be obtained.

In each of the above-described embodiments, the power supply potential V _cc <potential V _pp , the potential V _bb <the ground potential V _ss , and the potential V _bb1 <potential V _bb2 are described. V _cc> potential V _pp, the potential V _bb> ground potential V _ss, even when the potential V _bb1> potential V _bb2, can describe each same thing.

Example 8 FIG.
FIG. 16 is a circuit diagram showing Example 8 of the semiconductor circuit according to the present invention. FIG. 16 shows a case where three inverters I ₁₁ , I ₁₂ , I ₁₃ constituted by bulk structure FETs in which wells are formed are connected in series. In the inverter I ₁₁ , a pMOS FET Q81 and an nMOS FET Q82 are connected in series between a power supply line V _cc (power supply potential: V _cc ) and a ground line V _ss (ground potential: V _ss ). Similarly, in the inverter I ₁₂ (I ₁₃ ), a pMOS FET Q83 (Q85) and an nMOS FET Q84 (Q86) are connected in series between the power supply line V _cc and the ground line V _ss .

The gates of the pMOS FET Q81 and the nMOS FET Q82 are connected, and this connection point is used as the input node IN. The pMOS of FETQ81, the drain of the nMOS of FETQ82 are connected, the connection point is connected to the connection point of the gates of the pMOS of FETQ83 and nMOS of FETQ84 inverter I _12. Similarly FETQ83 and drain connection point FETQ84 of nMOS of the pMOS is connected to FETQ85 and connection points of the gates of FETQ86 of nMOS of pMOS inverter I _13, the drain connection point of the pMOS FETQ85 and nMOS of FETQ86 Is an output node OUT.

The back gate of pMOS of FETQ81, Q85 is connected to the switching circuit 11 for switching between the power source potential V _cc and the potential V _pp, the back gate of FETQ83 are connected to the same power supply line V _cc and a source. The back gates of the nMOS FETs Q82 and Q86 are connected to the same ground line V _ss as the source, and the back gate of the FET Q84 is connected to the switch circuit 10 for switching between the ground potential V _ss and the potential V _bb .

In this embodiment, an H level clock signal is input to the input node IN during standby. to the pMOS FETQ81, Q85 of the back gate potential V _pp is applied from the switch circuit 11, the power source potential V _cc is applied to the back gate of FETQ83. The ground potential V _ss is applied to the back gates of the nMOS FETs Q82 and Q86, and the potential V _bb is applied from the switch circuit 10 to the back gate of the FET Q84.

On the other hand, when active, a clock signal at L level is input to the input node IN. The power supply potential _Vcc is applied from the switch circuit 11 to the back gates of the FETs Q81 and Q85, and the same power supply potential _Vcc as the source potential is applied to the back gate of the FET Q83. The FETQ82, the same ground potential V _ss to the source potential is applied to Q86 to the back gate, a ground potential V _ss from the switch circuit 10 is applied to the back gate of FETQ84.

  By controlling the potential applied to the back gate in this way, the threshold voltages of the pMOS FETs Q81 and Q85 that are off during standby become larger than the threshold voltage during active, and are off during standby. The threshold voltage of the nMOS FET Q84 is larger than the threshold voltage when active. Therefore, it is possible to reduce the subthreshold current flowing in the FET that is turned off during standby. High-speed operation in the inverter array can be realized by performing threshold scaling for the low-voltage circuit.

Example 9
FIG. 17 is a circuit diagram showing Example 9 of the semiconductor circuit according to the present invention. FIG. 17 shows a case where _four inverters I ₁ , I ₂ , I ₃ , and I ₄ constituted by SOI-structure FETs are connected in series. In the inverter I ₁ , a pMOS FET Q31 and an nMOS FET Q32 are connected in series between a power supply line V _cc (power supply potential: V _cc ) and a ground line V _ss (ground potential: V _ss ). Similarly, in the inverter I ₂ (I ₃ , I ₄ ), a pMOS FET Q33 (Q35, Q37) and an nMOS FET Q34 (Q36, Q38) are connected in series between the power supply line V _cc and the ground line V _ss. Yes.

The gates of the pMOS FET Q31 and the nMOS FET Q32 are connected, and this connection point is used as the input node IN. The pMOS of the FET Q31, the drain of the nMOS of FETQ32 are connected, the connection point is connected to the connection point of the gates of FETQ34 the inverter I ₂ pMOS of FETQ33 and nMOS. Similarly FETQ33 and drain connection point FETQ34 of nMOS of the pMOS is connected to a connection point of the gates of FETQ35 of pMOS inverters I ₃ and nMOS of FETQ36, the drain connection point of the pMOS FETQ35 and nMOS of FETQ36 Is connected to the connection point of the gates of the pMOS FET Q37 and the nMOS FET Q38 of the inverter I ₄ . The connection point of the drains of the pMOS FET Q37 and the nMOS FET Q38 is the output node OUT.

The bodies of the pMOS FETs Q31 and Q35 (including the channel layer and the channel off layer below the FS layer) are connected to the same power supply line _Vcc as the source, and the bodies of the nMOS FETs Q34 and Q38 are the same as the ground line V _ss as the source. It is connected to the. The bodies of the pMOS FETs Q33 and Q37 are connected to a switch circuit 81 that selectively _applies the potential V _pp1 or the potential V _pp2 (V _pp1 > V _pp2 ). The bodies of the nMOS FETs Q32 and Q36 have the potential V _bb1. Alternatively, it is connected to a switch circuit 82 that selectively _{applies a} potential V _bb2 (V _bb1 <V _bb2 ).

The switch circuit 81 is supplied with the potential V _pp1 by the voltage supply means 83, is supplied with the potential V _pp2 by the voltage supply means 84, and is further supplied with the inverted clock signal bar φ from the clock signal generation circuit 85. . Further to the switch circuit 82, the potential V _bb1 given by the voltage supply means 86, the potential V _bb2 provided by the voltage supply means 87, further comprise a clock signal generating circuit 85 to the inverted clock signal bar φ is given Yes. The circuit including the switch circuits 81, 82, the voltage supply means 83, 84, 86, 87, and the clock signal generation circuit 85 is referred to as the substrate (body) bias switching circuit 88.

The switch circuit 82 is connected to the external RAS signal ex. RAS is the same as the clock signal (φ or bar φ) generated by the clock signal generation circuit 85. The output side of the changeover switch (36b) is connected to the bodies of the nMOS FETs Q34 and Q38. Note one of the potential V _bb1 or potential V _bb2 be a ground potential V _ss, it becomes similar to the configuration shown the potential V _bb2 to the ground potential V _ss Tosureba FIG. At this time, V _bb1 <V _bb2 must be _satisfied .

Further, the switch circuit 81 may _{replace the} voltage supply means 15 shown in FIG. 3 with the voltage supply means 83 to change the potential V _pp to the potential V _pp1 and the power supply potential V _cc to the potential V _pp2 obtained from the voltage supply means 84. Naonao can either potential V _pp1 or potential V _pp2 the power supply potential V _cc, becomes similar to the configuration shown the potential V _pp2 to the power supply potential V _cc Tosureba FIG. At this time, V _pp1 > V _pp2 must be _satisfied .

The operation of the semiconductor circuit configured as described above will be described. The input signal input from the input node IN during standby is at L level, and the body bias potentials of the FETs Q31, Q34, Q35, and Q38 that are turned on during standby are the same as the source potential. The body bias voltage of the nMOS of FET Q32, Q36 are turned off in the standby are potential V _bb1, body bias voltage of the pMOS of FETQ33, Q37 is a potential V _pp1.

When active, the input signal input from the input node IN becomes H level, and the FETs Q32, Q33, Q36, and Q37 are turned on. In this case the applied potential V _bb2 The body of the nMOS of FET Q32, Q36 at a substrate (body) bias switching circuit 88, the potential V _pp2 at pMOS of FETQ33, the body of Q37 substrate (body) bias switching circuit 88 Is applied. The body bias potentials of the FETs Q31, Q34, Q35, and Q38 that are turned off are the same as the source potential.

  As in the first embodiment, during standby, the body bias potential of the nMOS FET is set lower than that during activation, and the body bias potential of the pMOS FET is set higher than that during activation to increase the threshold voltage. Thereby, the subthreshold current can be reduced. In addition, since the threshold voltage is reduced when active, the switching speed of the inverter train can be increased.

  In this embodiment, the body bias potentials of all the FETs constituting the inverter are not controlled, but only the FETs Q32, Q33, Q36, and Q37 that are turned off during standby are connected to the substrate (body) bias switching circuit 88. Is controlling. Therefore, the current consumption required for switching the body bias potential is half that for controlling the body bias potential of all FETs. The body bias potential switching speed is also high.

  If the inverter array is manufactured in a bulk structure in which wells are formed as shown in FIG. 4, there are four types of substrate potentials, so four wells are necessary. In this case, there is a problem that the layout area is increased due to separation between wells or the like, and charge / discharge with respect to the parasitic capacitance of the well is large. However, when an inverter array is made of MOSFETs having an SOI structure as shown in FIG. 11, such a problem does not occur. Therefore, when this embodiment is applied to an inverter array composed of MOSFETs having an SOI structure, a good effect can be obtained. As described above, a logic circuit which has a low threshold voltage and a small standby current (subthreshold current) and which can operate at high speed can be realized.

Example 10
FIG. 18 is a circuit diagram showing Example 10 of the semiconductor circuit according to the present invention. In this embodiment, in place of the pMOS FETs Q31 and Q35 (for example, threshold voltage: 0.7 V) in the ninth embodiment, pMOS FETs Q41 and Q45 having a threshold voltage smaller than these (for example, 0.3 to 0.4 V) are used. Further, in place of the nMOS FETs Q34 and Q38 (for example, threshold voltage: 0.7V) in the ninth embodiment, nMOS FETs Q44 and Q48 having a smaller threshold voltage (for example, 0.3 to 0.4 V) are used. Other configurations are the same as those shown in FIG. A bulk-structure FET may be used.

  In this embodiment, since the threshold voltages of the FETs Q41, Q44, Q45, and Q48 that are turned on when active are reduced, current flows instantaneously at the time of transition from standby to active. Therefore, a switching operation faster than that in the ninth embodiment is possible.

Example 11.
FIG. 19 is a circuit diagram showing Example 11 of the semiconductor circuit according to the present invention. In this embodiment, four inverters I ₅ , I ₆ , I ₇ and I ₈ using the MT-MOS structure are shown. PMOS of FET Q51 of inverter I _5, and the connection point of the gate of the nMOS of FETQ52 an input node IN, FET Q51, the drain connection point FETQ52 of nMOS of pMOS is the pMOS inverter I ₆ FETQ53 and nMOS gates of FETQ54 Is connected to the connection point. Similarly FETQ53 and drain connection point FETQ54 of nMOS of the pMOS is connected to a connection point of the gates of the pMOS of FETQ55 and nMOS of FETQ56 inverter I _7, the drain connection point of the pMOS FETQ55 and nMOS of FETQ56 It is connected to the connection point of the gates of the pMOS of FETQ57 and nMOS of FETQ58 inverter I _8. The connection point between the drains of the pMOS FET Q57 and the nMOS FET Q58 is the output node OUT.

pMOS of FETQ51, Q53, Q55, the source of Q57 is connected to the secondary power supply line V _cc1, the source of nMOS of FETQ52, Q54, Q56, Q58 are connected to the sub-ground line V _ss1. Secondary power supply line V _cc1 is inverted clock signal bar φ is supplied to the gate, the power source potential V _cc is connected to the power supply line V _cc through a FETQ59 of pMOS given to the body (back gate). The sub-ground line V _ss1 is connected to the ground line V _ss via an nMOS FET Q60 to which the clock signal φ is applied to the gate and the ground potential V _ss is applied to the body (back gate). FETQ59, the threshold voltage of Q60 is larger than the inverter I _5, FET Q51 constituting the _{I 6, I 7, I 8} , Q52, Q53, Q54, Q55, Q56, Q57, Q58 threshold voltage.

  The body (back gate) of the pMOS FETs Q51, Q53, Q55, and Q57 is connected to the switch circuit (81) of the substrate (body) bias switching circuit 88, and the body (back) of the nMOS FETs Q52, Q54, Q56, and Q58. The gate) is connected to the switch circuit (82) of the substrate (body) bias switching circuit 88.

In the semiconductor circuit configured as described above, the FETs Q59 and 60 are turned off during standby. As a result, the power supply potential V _cc is not _applied to the sub power supply line V _cc1 , and the ground potential V _ss is not _applied to the sub ground line V _ss1 . Further, the potential V _pp1 is applied to the bodies (back gates) of the pMOS FETs Q51, Q53, Q55, and Q57, and the potential V _bb1 is applied to the bodies (back gates) of the nMOS FETs Q52, Q54, Q56, and Q58.

When active, FETs Q59 and 60 are turned on. As a result, the power supply potential _Vcc is _applied to the sources of the pMOS FETs Q51, Q53, Q55, and Q57 via the sub power supply line Vcc1, and the sub-ground line V _ss1 is _applied to the sources of the nMOS FETs Q52, Q54, Q56, and Q58. The ground potential V _ss is applied through the via. Furthermore the pMOS of FETQ51, Q53, Q55, Q57 of the body (back gate) is applied potential V _pp2, the nMOS FETQ52, Q54, Q56, the potential V _bb2 to Q58 of the body (back gate) is applied.

In the present invention, even if a current flows through the inverter train and the potential of the sub power supply line V _{cc1 and} the potential of the sub ground line V _ss1 occur, the body of the FET (back gate) so as to increase the threshold voltage during standby. Since the bias potential is controlled, it is possible to prevent a delay in switching or a change in logic.

Example 12.
FIG. 20 is a circuit diagram showing Example 12 of the semiconductor circuit according to the present invention. In this embodiment the pMOS FETQ51 shown in FIG. 19, Q55 body (the back gate) connected to the power supply line V _cc, the pMOS of FETQ53, Q57 only the body (back gate) on a substrate (body) bias switching circuit 88 Connected. Further, the body (back gate) of the nMOS FETs Q54 and Q58 shown in FIG. 19 is connected to the ground line V _ss, and the body (back gate) of only the nMOS FETs Q52 and Q56 is connected to the substrate (body) bias switching circuit 88. Yes. Other configurations are the same as those shown in FIG.

  In this embodiment, only the substrate bias potentials of the FETs Q52, Q53, Q56, and Q57 that are turned off during standby are variable. As a result, the number of FETs whose substrate bias potential is changed by the substrate (body) bias switching circuit 88 is halved as compared with the case of the eleventh embodiment. And can be switched at high speed.

Example 13.
FIG. 21 is a circuit diagram showing Embodiment 13 of the semiconductor circuit according to the present invention, and shows a case where the present invention is applied to the word driver shown in FIG. In the word driver WD, a pMOS FET Q61 and an nMOS FET Q62 are connected in series between a power supply line V _pp2 (potential: V _pp2 ) connected to a boost power supply and the ground, and are connected to the gates of the pMOS FET Q61 and the nMOS FET Q62. The decoder signal X is input, and the word line WL is connected to the connection point of the drains of the pMOS FET Q61 and the nMOS FET Q62. The n word drivers WD having such a configuration are arranged in parallel in the vertical direction and m columns in the horizontal direction (WD _{11 to} WD _mn ). The body (back gate) of the pMOS FET Q61 of each word driver WD is connected to the switch circuit 81 similar to the above-described embodiment.

In the semiconductor circuit having such a configuration, the body (back gate) bias potential of the pMOS FET Q61 is set to the potential V _pp1 during standby by the switch circuit 81. When active, the potential is V _pp2 (V _pp1 > V _pp2 ), and the decoder signal X ₁ is input to the selected word driver WD (for example, word driver WD ₁₁ ), so that the word line WL becomes active. Also in this embodiment, it is possible to realize a DRAM with a small standby current (subthreshold current) flowing during standby.

Example 14.
FIG. 22 is a circuit diagram showing Embodiment 14 of the semiconductor circuit according to the present invention, and shows a case where a hierarchical word driver is realized by using the present invention. The word drivers WD arranged in the vertical direction shown in FIG. 21 are defined as word driver columns B1, B2,. The body (back gate) of the pMOS FET Q61 is connected to the switch circuit 81 for each word driver column B. The potentials V _pp1 and V _pp2 are applied to the switch circuits 81 from the voltage supply means 83 and 84, _respectively . Further, the output signals of NOR circuits N1, N2,... Nm that receive the clock signal φ that is L level when active and the column selection signal K for selecting the word driver column B are supplied to each switch circuit 81. There is. Other configurations are the same as those shown in FIG. 21, and the same reference numerals are given and description thereof is omitted.

In the semiconductor circuit having such a configuration, during standby, the clock signal φ and the column selection signals K1, K2,... Km are at the H level, and the potential V _pp1 is applied to the body (back gate) of the pMOS FET Q61. As a result, the threshold voltage of the pMOS FET Q61 increases, and almost no subthreshold current flows.

When active, the clock signal becomes L level, and the column selection signal K1 applied to the switch circuit 81 connected to the selected word driver WD (eg, word driver WD ₁₁ ) becomes L level. The other column selection signals K2,... Km are at the H level. The word line WL rises by the decoder signal X ₁ on the pMOS FETQ61 is input. When active, the threshold voltage of the pMOS FET Q61 of the selected word driver WD becomes small, so that the word line WL rises at high speed.

  In this embodiment, it is only necessary to raise the source potential of only the word driver column B including the selected word driver WD, so that the rise time of the word line WL can be shortened compared to the twelfth embodiment.

  Examples 10 to 14 may be applied to either a bulk structure or an SOI structure. However, the control potential is the back gate bias potential in the case of the bulk structure, and the body bias potential in the case of the SOI structure.

It is a circuit diagram of a complementary MOS inverter showing an example of a logic circuit constituting a semiconductor circuit according to the present invention. FIG. 2 is a circuit diagram illustrating an example of a switch circuit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a switch circuit illustrated in FIG. 1. FIG. 2 is a cross-sectional structure diagram showing a well structure of the complementary MOS inverter shown in FIG. 1. It is a block diagram which shows the structure of an example of MOS-DRAM. It is a block diagram which shows the structure of an example of MOS-DRAM. 7 is a timing chart showing a breakdown of a transmission time of an external RAS signal in each internal part of the MOS-DRAM shown in FIGS. 5 and 6. FIG. 4 is a timing chart showing a relationship between a control clock signal and an external RAS signal in a MOS-DRAM. It is a block diagram which shows the structure of one Example of the memory cell which comprises MOS-DRAM. FIG. 10 is a circuit diagram showing a configuration example of the switch circuit shown in FIG. 9. FIG. 7 is a cross-sectional structure diagram showing another embodiment of a logic circuit constituting a semiconductor circuit according to the present invention. FIG. 12 is a diagram showing a layout of a main part of the semiconductor circuit shown in FIG. 11. FIG. 7 is a cross-sectional structure diagram showing still another embodiment of a logic circuit constituting a semiconductor circuit according to the present invention. FIG. 7 is a cross-sectional structure diagram showing still another embodiment of a logic circuit constituting a semiconductor circuit according to the present invention. FIG. 7 is a cross-sectional structure diagram showing still another embodiment of a logic circuit constituting a semiconductor circuit according to the present invention. 1 is a circuit diagram showing a semiconductor circuit according to the present invention. It is a circuit diagram which shows the other Example of the semiconductor circuit which concerns on this invention. 1 is a circuit diagram showing a semiconductor circuit according to the present invention. 1 is a circuit diagram showing a semiconductor circuit according to the present invention. 1 is a circuit diagram showing a semiconductor circuit according to the present invention. 1 is a circuit diagram showing a semiconductor circuit according to the present invention. 1 is a circuit diagram showing a semiconductor circuit according to the present invention. It is a circuit diagram which shows the complementary MOS inverter used for the conventional semiconductor circuit. It is the cross-section figure which showed typically the structural example of the conventional memory cell used for DRAM. It is a circuit diagram which shows the conventional CMOS circuit which uses MT-MOS when a logic circuit is an inverter row | line | column. It is a circuit diagram which shows the conventional word driver. It is a circuit diagram which shows the word driver of the conventional hierarchical structure.

Explanation of symbols

1 Complementary MOS inverter 10, 11, 36, 43C, 43R, 45C, 45R, 81, 82 Switch circuit 10a, 11a Level shift circuit 10b, 11b Changeover switch 13, 15, 44C, 44R, 46C, 46R, 48a, 48b, 83, 84, 86,
87 Voltage supply means 14 Clock signal generator 57 Memory cell 42 MOS-DRAM
85 Clock signal generation circuit 88 Substrate bias switching circuit φ, φ ₁ , φ ₂ control clock signal _Vcc power supply potential (normal back gate bias potential)
V _ss ground potential (normal back gate bias potential)
V _pp , V _bb , V _bb1 , V _bb2 potentials from voltage supply means, ex. RAS external row selection signal _{I 1, I 2, I 3} , I 4, I 5, I 6, I 7, I 8, I 11, I 12, I 13 inverter,
WD Word driver B Word driver string

Claims (6)

A semiconductor substrate of a first conductivity type;
A first well region and a second well region of a second conductivity type formed in the semiconductor substrate;
A first conductivity type well region formed in the second well region;
A first MOS-FET having a potential of the first well region of the second conductivity type as a back gate bias potential;
A second MOS-FET in which the potential of the well region of the first conductivity type is a back gate bias potential;
Switch means for selectively applying the first potential or the second potential as a back gate bias potential to the first well region of the second conductivity type of the first MOS-FET. Semiconductor circuit. A semiconductor substrate of a first conductivity type;
A first well region and a second well region of a second conductivity type formed in the semiconductor substrate;
A first conductivity type well region formed in the second well region;
A first MOS-FET having a potential of the first well region of the second conductivity type as a back gate bias potential;
A second MOS-FET in which the potential of the well region of the first conductivity type is a back gate bias potential;
And a switching means for selectively applying a third potential or a fourth potential as a back gate bias potential to the well region of the first conductivity type of the second MOS-FET. . A semiconductor substrate of a first conductivity type;
A first well region and a second well region of a second conductivity type formed in the semiconductor substrate;
A first conductivity type well region formed in the second well region;
A first MOS-FET having a potential of the first well region of the second conductivity type as a back gate bias potential;
A second MOS-FET in which the potential of the well region of the first conductivity type is a back gate bias potential;
First switch means for selectively applying a first potential or a second potential as a back gate bias potential to the first well region of the second conductivity type of the first MOS-FET;
And second switch means for selectively applying a third potential or a fourth potential as a back gate bias potential to the well region of the first conductivity type of the second MOS-FET. Semiconductor circuit.   When the first switch means applies the first potential (or the second potential) to the first MOS-FET, the second switch means has the third potential (or the fourth potential) 4. The semiconductor circuit according to claim 3, wherein a potential is applied to the second MOS-FET.   The semiconductor circuit according to claim 1, wherein the second potential is higher than the first potential. 5. The semiconductor circuit according to claim 2, wherein the fourth potential is lower than the third potential. 6.

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