JP2005347491A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the reduction of an oxygen diffusion barrier film provided under a capacitor, caused by a crystallization heat treatment of a dielectric film. <P>SOLUTION: A method for manufacturing a semiconductor device comprises the steps of forming an oxygen diffusion barrier layer 25 so as to come into contact with a second contact plug 23 on a second interlayer insulating film 21; forming a third interlayer insulating film 26 on the oxygen diffusion barrier layer 25 and the second interlayer insulating film 21; forming a capacity element 34 composed of a lower electrode 29, a capacity insulating film 32, and an upper electrode 33 in an opening 27 formed in the third interlayer insulating film 26; removing a part of the third interlayer insulating film 26 surrounding the capacity element 34; and conducting a heat treatment under an oxygen atmosphere for the capacity element 34 after the step of removing the third interlayer insulating film 26. Thus, it is possible to prevent the reduction of the oxygen diffusion barrier layer 25 at the time of the heat treatment step. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device having an oxygen diffusion barrier layer in a capacitor.

  As the degree of integration of DRAM and FeRAM increases in the semiconductor memory device, the area of the memory cell is reduced. On the other hand, the area of the capacitor cannot be reduced as the cell size is reduced, and a minimum capacity is required to maintain a stable operation.

  Therefore, as a method for securing the capacity of the memory capacitor within the limited memory cell area, there is a method in which the structure of the lower electrode of the capacitor is three-dimensionalized in order to increase the effective area of the capacitor.

As one of such three-dimensional capacitors, there is a concave type capacitor. For example, Patent Document 1 shows a method for manufacturing a concave capacitor in which an oxygen diffusion barrier layer is provided between a capacitor and a contact plug.
JP 2003-133534 A (page 8, FIG. 4)

  However, a three-dimensional capacitor using a noble metal oxide such as an iridium oxide for the oxygen diffusion barrier layer has the following problems.

  In the concave type capacitor, heat treatment is performed in an oxygen atmosphere in order to crystallize the dielectric film after forming the capacitor. At this time, oxygen from the concave portion of the concave is consumed to some extent by crystallization of the ferroelectric film, but most of the oxygen is supplied to the oxygen barrier layer. However, in a three-dimensional capacitor, a dense insulating film is formed thickly on or next to the oxygen barrier layer except in a region in contact with the concave concave portion of the oxygen barrier layer. Oxygen is not sufficiently supplied to the noble metal oxide layer that is the diffusion barrier layer. That is, since the oxygen intrusion path from the atmosphere to the oxygen diffusion barrier layer is long, oxygen supply in the atmosphere is not sufficiently performed to the oxygen diffusion barrier layer. Since noble metals have poor chemical reactivity, if no oxygen is supplied during heat treatment, oxides of noble metals are likely to decompose and release oxygen. When the noble metal oxide is reduced, the oxygen barrier property is weakened, so that oxygen diffuses to the contact plug below the oxygen diffusion barrier layer, the contact plug is oxidized, and the contact resistance increases.

  Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing reduction of an oxygen diffusion barrier layer in a concave capacitor in view of the problems of the conventional technology.

  In order to solve the above problems, a first method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a substrate, and a first in a hole formed in the first insulating film. A step (a) of forming an embedded plug of the conductive film, a step (b) of forming a second conductive film made of a noble metal oxide on the first insulating film so as to be in contact with the plug, and a second A step (c) of forming a second insulating film on the conductive film and the first insulating film; a step (d) of forming an opening reaching the second conductive film in the second insulating film; A step (e) of forming a capacitive element comprising a lower electrode, a capacitive insulating film, and an upper electrode in the opening, a step (f) of removing a second insulating film at least around the capacitive element, and a second After the step (f) of removing the insulating film, a step of performing heat treatment on the capacitor element in an oxygen atmosphere ( And having a).

  The second method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a substrate, and a hole formed in the first insulating film so as not to completely fill the hole. A step (a) of embedding the first conductive film below the upper surface of the first insulating film, and a second step made of a noble metal oxide on the first conductive film so as to completely fill the hole. A step (b) of forming a conductive film, a step (c) of forming a second insulating film on the second conductive film and the first insulating film, and a second conductive film on the second insulating film. A step (d) of forming an opening reaching the film, a step (e) of forming a capacitive element comprising a lower electrode, a capacitive insulating film, and an upper electrode in the opening, and a second at least around the capacitive element After the step (f) of removing the insulating film and the step (f) of removing the second insulating film, the oxygen atmosphere is applied to the capacitor element. Characterized by a step (g) performing a heat treatment under.

  As described above, according to the first and second semiconductor device manufacturing methods, after the thickness of the second insulating film on the oxygen diffusion barrier layer, which is the second conductive film made of the noble metal oxide, is once reduced, Since the heat treatment is performed on the capacitive insulating film in an oxygen atmosphere, the distance between the oxygen diffusion barrier layer and the oxygen atmosphere is shortened, and oxygen is sufficiently supplied to the oxygen diffusion barrier layer made of a noble metal oxide. Therefore, reduction of the oxygen diffusion barrier layer can be prevented during the heat treatment, and peeling due to reduction of the oxygen diffusion barrier film can be prevented.

  In the first and second semiconductor device manufacturing methods, the step (f) of removing the second insulating film includes a second insulation from the upper surface of the second insulating film to the upper surface of the second conductive film. Preferably, the film is removed. In this case, since the second conductive film which is an oxygen diffusion barrier layer is in direct contact with the oxygen atmosphere, oxygen can be effectively supplied to the second conductive film, and reduction can be prevented.

  In the first and second semiconductor device manufacturing methods, the step (f) of removing the second insulating film preferably leaves at least the second insulating film on the side of the capacitor element. In this case, even if the second insulating film around the capacitor element is removed, the capacitor element can be prevented from falling by leaving a part of the second insulating film in contact with the capacitor element.

  In the first and second semiconductor device manufacturing methods, the second insulating film is preferably removed by wet etching. By using wet etching, damage to the capacitor insulating film caused by etching for removing the second insulating film can be reduced.

  In the first and second semiconductor device manufacturing methods, the second interlayer insulating film is preferably removed by dry etching. In this manner, by using anisotropic dry etching, the second insulating film remains partly below the upper electrode of the capacitor, so that the concave three-dimensional capacitor can be prevented from falling. Further, when the lower electrode of the capacitive element has a tapered shape, a part of the second insulating film remains below the tapered portion, so that the collapse due to the removal of the second insulating film of the concave three-dimensional capacitor is prevented. Can do.

  In the first and second semiconductor device manufacturing methods, the heat treatment temperature is preferably 650 ° C. or higher and 850 ° C. or lower.

  In the first and second semiconductor device manufacturing methods, the second conductive film is preferably formed of a noble metal oxide stack. Thus, when the oxygen diffusion barrier layer is composed of a stack of noble metal oxides, the oxygen barrier property is improved, and oxidation of the plug in an oxygen atmosphere can be effectively prevented.

  In the first and second semiconductor device manufacturing methods, the noble metal oxide is preferably an iridium oxide. Since the iridium oxide is thermally unstable and decomposes and releases oxygen by the heat treatment, reduction of the oxygen diffusion barrier layer can be suppressed by supplying more oxygen during the heat treatment.

  In the first and second semiconductor device manufacturing methods, the plug is preferably made of tungsten. Since tungsten is easily oxidized by heat treatment, when tungsten is used as the plug, oxidation of the plug can be reduced by using the first and second semiconductor device manufacturing methods.

  In the first and second semiconductor device manufacturing methods, the dielectric film is preferably a ferroelectric film. Since the crystallization temperature of the ferroelectric film is generally high, the effect of the present invention is great.

  According to the method for manufacturing a semiconductor device of the present invention, in a capacitor having an oxygen diffusion barrier layer, reduction of the oxygen diffusion barrier layer can be prevented and deterioration of contact resistance can be suppressed.

(First embodiment)
A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1A to FIG. 4C are process cross-sectional views of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, a shallow trench isolation region (STI: Shallow Trench Isolation) 11 is selectively formed on a semiconductor substrate 10 made of, for example, silicon (Si), and a semiconductor is formed by the formed STI region 11. The substrate 10 is partitioned into a plurality of element formation regions.

  Subsequently, each element formation region includes, for example, a gate insulating film 12 made of silicon oxide or silicon oxynitride and having a thickness of about 3 nm, and a gate electrode 13 having a thickness of about 200 nm including polycrystalline silicon, metal, or metal silicide. And the impurity diffusion layer 14 is formed by ion implantation of impurity ions using the gate electrode 13 as a mask, thereby forming the transistors 15.

Subsequently, an insulating film made of, for example, BPSG, HDP-NSG, or O ₃ -NSG is formed with a film thickness of about 0.6 μm to 1.2 μm so as to cover the semiconductor substrate 10 by CVD, Thereafter, the surface of the formed insulating film is planarized using a chemical mechanical polishing (CMP) method, and the first interlayer insulating film having a thickness of about 0.4 μm to 0.8 μm. 16 is formed.

  Next, as shown in FIG. 1B, a first contact hole 17 that exposes one impurity diffusion layer 14 of each transistor 15 is formed in the first interlayer insulating film 16 by lithography and dry etching. Form.

  Next, as shown in FIG. 1C, the first contact plug is filled so as to fill the first contact hole 17 on the first interlayer insulating film 16 by sputtering, CVD or plating. A formation film 18 is formed. Here, the first contact plug forming film 18 is made of a metal such as tungsten, a metal nitride such as titanium nitride, a silicide metal such as titanium silicide, copper, or polycrystalline silicon. Further, before the first contact plug formation film 18 is formed, an adhesion layer made of, for example, titanium and titanium nitride or a laminated film of tantalum and tantalum nitride, which are sequentially laminated from the substrate side, may be formed.

  Next, as shown in FIG. 1D, the formed first contact plug forming film 18 is etched back or subjected to CMP until the upper surface of the first interlayer insulating film 16 is exposed. A first contact plug 19 that is electrically connected to one impurity diffusion layer 14 of each transistor 15 is formed from the first contact plug formation film 18.

  Next, as shown in FIG. 1E, a conductive film made of, for example, tungsten or polycrystalline silicon is formed on the first interlayer insulating film 16 by, for example, sputtering, CVD, or a furnace, and then Then, the conductive film is patterned so as to be connected to the first contact plug 19 by lithography and etching to form a plurality of bit wirings 20 from the conductive film. At this time, when the wiring material is tungsten, for example, an etching gas obtained by mixing a chlorine-based gas and a fluorine-based gas may be used, and when polycrystalline silicon is used, a fluorine-based gas may be used. When tungsten is used for the bit wiring 20, an adhesion layer made of a laminated film of, for example, titanium and titanium nitride sequentially laminated from the substrate side may be formed before the tungsten film is formed. The thickness of each bit wiring 20 is determined by wiring resistance and design rules, and is preferably about 20 nm to 150 nm. Furthermore, when forming a stack type contact plug with the wiring above the capacitor element, a bit wiring pattern is formed in advance so as to cover one of the first contact plugs 19. This description is given in the figure.

  In the present embodiment, the configuration in which the bit wiring 20 is disposed below the capacitive element has been described. However, the present invention is not limited to this, and the present invention is also applicable to a configuration in which the bit wiring is disposed above the capacitive element. The effect of can be obtained.

  Next, as shown in FIG. 1F, a second interlayer insulating film 21 made of BPSG or the like having a film thickness of about 200 nm to 800 nm is formed on the first interlayer insulating film 16 by CVD. A film is formed so as to cover the bit wiring 20, and then, the formed second interlayer insulating film 21 is planarized by CMP, etchback or reflow processing. By this planarization treatment, it is easy to form a capacitor element provided on the second interlayer insulating film 21. In particular, when the CMP method is used, the stepped portion caused by each bit wiring 20 can be further planarized on the second interlayer insulating film 21.

  The film thickness X of the upper portion of each bit wiring 20 in the second interlayer insulating film 21 is preferably set to 50 nm to 500 nm, which is a film thickness that can prevent the oxidation of each bit wiring 20.

  Next, as shown in FIG. 1G, the other impurity diffusion layer 14 of each transistor 15 is exposed to the first interlayer insulating film 16 and the second interlayer insulating film 21 by lithography and dry etching. A second contact hole 22 is formed. Here, the first interlayer insulating film 16 and the second interlayer insulating film 21 are the first insulating films.

  Next, a second contact plug forming film (not shown) is formed on the second interlayer insulating film 21 so as to fill the second contact hole 22 by sputtering, CVD, or plating. Film. Here, the material of the second contact plug formation film may be the same as that of the first contact plug 19. Also in this case, an adhesive layer made of a laminated film of titanium nitride and titanium or tantalum nitride and tantalum may be formed before the second contact plug formation film is formed. Here, the second contact plug formation film is the first conductive film.

  Thereafter, as shown in FIG. 2A, the second contact plug formation film thus formed is subjected to etch back or CMP treatment until the second interlayer insulating film 21 is exposed, so that the second contact is formed. A second contact plug 23 that is electrically connected to the other impurity diffusion layer 14 of each transistor 15 is formed from the plug formation film. Here, the second contact plug 23 is a plug.

  Next, as shown in FIG. 2B, the entire surface of the second interlayer insulating film 21 is formed by, for example, sputtering, CVD, or metal organic chemical vapor deposition (MOCVD). The second contact plug is mainly formed by oxygen that passes through the upper electrode, the capacitor insulating film, and the lower electrode in order during the heat treatment for crystallization of the capacitor insulating film in the subsequent process. An oxygen diffusion barrier forming film 24 for preventing oxidation of the film 23 is formed. .

  Here, as the material of the oxygen diffusion barrier forming film 24, for example, a single layer film of a noble metal oxide film such as an iridium oxide film (IrOx) or a ruthenium oxide film, or a laminate including at least a noble metal oxide film. Use a membrane.

  The material laminated together with the noble metal oxide film includes titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium oxynitride (TiAlON), iridium (Ir), ruthenium (Ru), etc. By laminating with a noble metal oxide film, the oxygen diffusion barrier property is improved, and it may also serve as a barrier for metal diffusion. For example, when a laminated film of Ir and IrOx is formed, the oxygen barrier property is higher than that of a single film of IrOx. Further, for example, when TiN or TiAlN is formed on a contact plug made of tungsten, it is possible to prevent tungsten atoms from diffusing into a film on TiN or TiAlN during the heat treatment in the middle of the process. For TiAlN, TiAlON, and TiN, it also serves as a conductive hydrogen diffusion barrier film. It also becomes.

  Next, as shown in FIG. 2C, the oxygen diffusion barrier forming film 24 is patterned so as to cover the contact plug 23, and an oxygen diffusion barrier layer 25 is formed. Here, the oxygen diffusion barrier layer 25 is a second conductive film.

  Next, as shown in FIG. 2D, a third interlayer insulating film 26 having a thickness of about 300 nm to 1500 nm is formed on the entire surface of the oxygen diffusion barrier layer 25 by, eg, CVD. Subsequently, a planarization process is performed by a CMP method to obtain a film thickness of about 200 nm to 1300 nm. BPSG, PSG, TEOS, or SiN may be used as the material of the third interlayer insulating film 26, but O3NSG is most preferable. Thus, NSG formed by thermal CVD using O3 is particularly preferable because it is an insulating film containing no impurities and does not generate hydrogen during film formation. Here, the film thickness of the third interlayer insulating film 26 is a parameter for determining the capacitance value of a capacitor element to be described later in order to determine the depth of the opening 27 for forming the capacitor element. The third interlayer insulating film 26 is a second insulating film.

  Next, as shown in FIG. 2E, the upper surface of the oxygen diffusion barrier layer 25 is exposed to the third interlayer insulating film 26 by lithography and dry etching, or lithography and wet etching. A plurality of openings 27 are formed.

  The opening 27 preferably has a taper of 60 degrees or more and 90 degrees or less. That is, it is preferable that the angle formed between the wall surface and the bottom surface of the opening 27 is about 90 degrees to 120 degrees. According to such a shape, the film coverage is good, so that the lower electrode, the capacitor insulating film, and the upper electrode to be formed thereafter can be formed with a substantially uniform film thickness by sputtering or the like. Therefore, variation in film thickness can be suppressed, and disconnection of the electrode can be prevented.

  Next, as shown in FIG. 3A, by sputtering, CVD, or MOCVD, at a temperature of about 200 ° C. or more and 500 ° C. or less, on the third interlayer insulating film 26 and each opening 27. A conductive film 28 which is a lower electrode formation film having a thickness of about 20 nm to 50 nm is formed along the wall surface and the bottom surface. As a material for the conductive film 28, a noble metal such as platinum or iridium, or an oxide, nitride, or oxynitride of a noble metal is preferable.

  Next, as shown in FIG. 3B, the conductive film 28 on the third interlayer insulating film 26 is removed so that at least the conductive film 28 in the opening 27 remains, and a lower electrode 29 is formed. . Here, as a method for removing the conductive film 28, patterning is performed outside the opening 27 so as to leave the opening 27 by lithography and dry etching. Alternatively, the conductive film 28 other than the opening 27 may be removed by a CMP method.

  Next, as shown in FIG. 3C, for example, a ferroelectric film is formed by the MOCVD method so as not to bury the opening 27 on the third interlayer insulating film 26 and on each lower electrode 29. A capacitive insulating film 30 having a thickness of about 20 nm to about 100 nm is formed.

The capacitor insulating film 30 has a barium strontium titanate (Ba _x Sr _1-x TiO ₃ ) (provided that x is 0 ≦ x ≦ 1, hereinafter referred to as BST) based dielectric, Lead zirconium titanate (Pb (Zr _x T _1-x ) O ₃ ) (where x is 0 ≦ x ≦ 1, hereinafter referred to as PZT) or lead lanthanum zirconium titanate (Pb _y La ₁₋ Perovskite-based dielectrics containing lead such as _y (Zr _x Ti _1-x ) O ₃ , where x and y are 0 ≦ x and y ≦ 1, or strontium bismuth tantalate (Sr _1-y Bi _{2 + x} Ta ₂ O ₉ ) (where x and y are 0 ≦ x and y ≦ 1, hereinafter referred to as SBT) or bismuth lanthanum titanate (Bi _4−x La _x Ti ₃ O ₁₂ ) (Where x is 0 ≦ x ≦ 1) or the like and a perovskite dielectric material containing bismuth is used. When, it is possible to produce a non-volatile memory device.

For the ferroelectric film, a compound having a perovskite structure represented by a general formula ABO ₃ (however, A and B are different elements) can be used. Here, the element A is, for example, lead (Pb), barium (Ba), strontium (Sr), calcium (Ca), lanthanum (La), lithium (Li), sodium (Na), potassium (K), magnesium. (Mg) and at least one selected from the group consisting of bismuth (Bi), and the element B is, for example, titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), tungsten (W ), Iron (Fe), nickel (Ni), scandium (Sc), cobalt (Co), hafnium (Hf), magnesium (Mg), and molybdenum (Mo).

  In addition, the capacitor insulating film 30 is not limited to a single-layer ferroelectric film, and a plurality of ferroelectric films having different compositions may be used, and furthermore, different compositions may be inclined.

Needless to say, the capacitor insulating film 30 according to the present invention is not limited to a ferroelectric substance, and silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), niobium pentoxide (Nb ₂ O _5). ), Tantalum pentoxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), or the like may be used.

  Next, a conductive material that is an upper electrode forming film having a thickness of about 20 nm is formed on the capacitor insulating film 30 by sputtering, CVD, or MOCVD under the same film forming conditions as the conductive film 28 for forming the lower electrode. A film 31 is formed.

  Next, the capacitive insulating film 30 is patterned from the capacitive insulating film 30 by patterning the capacitive insulating film 30 and the conductive film by a lithography method and a dry etching method using a mixed gas of a chlorine-based gas and a fluorine-based gas. Then, the upper electrode 33 is formed from the conductive film 31. As a result, a concave capacitive element 34 including the lower electrode 29, the capacitive insulating film 32 and the upper electrode 33 is formed.

  Next, as shown in FIGS. 4A to 4D, a part of the third interlayer insulating film 26 is removed by dry etching or wet etching.

  In the case of wet etching, as shown in FIG. 4A, in the capacitor cross-sectional view in the cell plate line direction, a region below the upper electrode 33 formed across a plurality of capacitors isotropic etching. a is etched. Further, as shown in FIG. 4C, in the capacitor cross-sectional view in the bit line direction, the third interlayer insulating film 26 in the region a is etched. After that, as shown in FIGS. 5A and 5B, the region a is not buried when the fourth interlayer insulating film 35 is formed, and a void is generated.

  When wet etching is used, damage to the capacitor insulating film 32 made of a ferroelectric film can be reduced.

  On the other hand, since anisotropic dry etching is anisotropic etching, for example, in the cross-sectional view in the cell plate direction shown in FIG. 4B, the upper electrode 33 formed across a plurality of capacitors. The third insulating film 26 below is left as it is. Furthermore, as shown in the capacitor cross-sectional view in the bit line direction of FIG. 4D, the third insulating film 26 below the upper electrode 33 remains, and the concave capacitor 34 can be prevented from falling. Further, when the lower electrode 29 has a tapered shape, the third interlayer insulating film 26 remains in the lower layer of the tapered portion, and the concave type capacitor can be prevented from falling.

  Here, the third interlayer insulating film 26 above the upper surface of the oxygen diffusion barrier layer 25 is removed at least around the capacitive element 34. At this time, for example, as shown in FIGS. 4C and 4A, the film thickness A of the third interlayer insulating film 26 remaining on the oxygen diffusion barrier layer 25 is preferably as thin as possible. It is necessary to have a film thickness that does not cause collapse of the film. Further, the contact plug 23 needs to have a film thickness that does not allow oxygen to diffuse directly. In order to prevent the reduction of the noble metal oxide constituting the oxygen diffusion barrier layer 25, the thickness A of the third interlayer insulating film 26 remaining on the oxygen diffusion barrier layer 25 should be as thin as possible. Needless to say. From these three points, the film thickness A of the third interlayer insulating film 26 remaining on the oxygen diffusion barrier layer 25 is preferably about 0 to 200 nm. Further, 10 to 50 nm is more preferable.

  Next, heat treatment is performed at a temperature of 650 ° C. to 850 ° C., for example, in an oxygen atmosphere for the purpose of crystallizing the capacitive insulating film 32. This heat treatment is performed by annealing in a furnace, RTA, or the like. At this time, since the third interlayer insulating film 26 on the oxygen diffusion barrier layer 25 is thin, oxygen is sufficiently supplied to the oxygen diffusion barrier layer 25, and the decomposition of oxygen from the noble metal oxide film does not proceed. The oxygen diffusion barrier layer 25 does not deteriorate. As a result, oxidation of the contact plug 23 can be prevented. In addition, when the oxygen barrier layer is a laminated film of IrOx, Ir, TiAlN from the top, since there is no deterioration of the oxygen barrier film of IrOx, IrOx can prevent oxygen diffusion and is a lower film Ir and TiAlN are not oxidized.

  Next, as shown in FIGS. 5A and 5B, a fourth interlayer insulating film 35 made of BPSG or the like is formed over the entire surface of the semiconductor substrate 10 so as to cover the capacitive element 34 by the CVD method. A film is formed, and the surface of the formed fourth interlayer insulating film 35 is planarized by a CMP method. The thickness of the fourth interlayer insulating film 35 after planarization from the upper end portion of the capacitive element 34 is desirably 100 to 200 nm.

  If wet etching is used when removing the third interlayer insulating film 26 in the previous step, a BPSG film may not be deposited around the capacitive element 34 and a void (not shown) may be formed. .

  Next, as shown in FIG. 5C, the bit wiring 20 is formed on the fourth interlayer insulating film 35, the third interlayer insulating film 26, and the second interlayer insulating film 21 by lithography and dry etching. A third contact hole 36 exposing the portion is formed.

  Next, as shown in FIG. 5D, the third contact is made so that the third contact hole 36 is filled on the fourth interlayer insulating film 35 by sputtering, CVD, or plating. A plug forming film (not shown) is formed. Here, the material of the third contact plug formation film may be the same as that of the first contact plug formation film 18. Also in this case, an adhesion layer made of a laminated film of titanium nitride and titanium or tantalum nitride and tantalum may be formed before forming the third contact plug formation film. Thereafter, the formed third contact plug formation film is etched back or subjected to CMP processing until the upper surface of the fourth interlayer insulating film 35 is exposed, and each bit wiring is formed from the third contact plug formation film. A third contact plug 37 that is electrically connected to the contact hole 20 is formed. Thus, a so-called stack contact is formed by the first contact plug 19, the bit line 20, and the third contact plug 37.

  In addition, when the oxygen diffusion barrier layer 25 is a single layer of noble metal oxide, the reduction in oxygen diffusion barrier property due to reduction is large. Therefore, when the method for manufacturing a semiconductor device according to the present invention is used, oxygen can be effectively absorbed. Since it can be supplied to the oxygen diffusion barrier layer 25, the effect of reducing reduction is great.

  Further, when the material of the contact plug 23 is W, W is easily oxidized. Therefore, when the method for manufacturing a semiconductor device according to the present invention is used, deterioration of the oxygen barrier property of the oxygen diffusion barrier layer 25 is suppressed. The effect of preventing oxidation of the contact plug is increased.

  In addition, when the noble metal oxide constituting the oxygen diffusion barrier layer 25 is an iridium oxide, iridium oxide is thermally unstable, and thus is easily decomposed by heat treatment to release oxygen. In such a case, by using the method for manufacturing a semiconductor device according to the present invention, heat treatment can be performed while oxygen is sufficiently supplied, so that decomposition of iridium oxide can be suppressed.

  Further, when the capacitor insulating film 32 is a ferroelectric material, the heat treatment temperature in the oxygen atmosphere is high during crystallization, so that the effect of the present invention is great.

(Second Embodiment)
A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 6A to FIG. 7C show cross-sectional configurations in the order of steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention. Further, the steps before FIG. 6A are the same as the steps from FIG. 1A to FIG. 1G of the first embodiment, and thus description thereof is omitted. Further, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 6A, the contact plug formation film 18 (not shown) is removed by an etch back method or a CMP method, and the upper surface of the contact plug is positioned lower than the upper surface of the second interlayer insulating film 21. To form. Thereby, as shown to Fig.6 (a), the recessed part 38 is formed. The recess 38 can be controlled by an etch back method or a CMP selection ratio. Alternatively, the contact plug 23 can be removed by wet etching.

  Next, an oxygen diffusion barrier formation film 24 (not shown) is formed so as to fill the recess 38 over the entire surface of the second interlayer insulating film 21, and the oxygen diffusion barrier formation film 24 protruding from the recess 38 is etched. By removing by the back method or the CMP method, the oxygen diffusion barrier layer 25 is formed only in the recess 38.

  6 (c) to 7 (b) are the same steps as those in FIGS. 2 (d) to 3 (c) of the first embodiment, and a description thereof will be omitted.

  Next, as shown in FIG. 7C, a part of the third interlayer insulating film 26 is removed by dry etching or wet etching. At this time, the film thickness A of the third interlayer insulating film 26 remaining above the oxygen diffusion barrier layer 25 is preferably as thin as possible, but the film thickness that does not cause the capacitor element 34 to fall is required at a minimum. Further, the contact plug 23 needs to have a film thickness that does not allow oxygen to diffuse directly. Further, in order to prevent the reduction of the noble metal oxide which is one layer of the oxygen diffusion barrier layer 25, the thickness of the third interlayer insulating film 26 around the oxygen diffusion barrier layer 25, that is, the third interlayer insulating film 26 closest to the oxygen diffusion barrier layer. It goes without saying that A should be as thin as possible. From these three points, the film thickness A of the third interlayer insulating film 26 remaining on the oxygen diffusion barrier layer 25 is preferably about 0 to 200 nm. Further, 10 to 50 nm is more preferable.

  The subsequent steps are the same as those after FIG.

  In the second embodiment, the oxygen diffusion distance from the oxygen barrier film to the upper surface of the insulating film is longer than that in the first embodiment, so that the effect of the present invention is great.

  The method for manufacturing a semiconductor device according to the present invention is useful for a semiconductor device having a concave three-dimensional capacitor having an oxygen barrier film under the capacitor.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

10 Semiconductor substrate 11 Shallow trench isolation region 12 Gate insulating film 13 Gate electrode 14 Impurity diffusion layer 15 Transistor 16 First interlayer insulating film 17 First contact hole 18 Contact plug forming film 19 First contact plug 20 Bit wiring 21 First Second interlayer insulating film 22 second contact hole 23 second contact plug 24 oxygen diffusion barrier forming film 25 oxygen diffusion barrier layer 26 third interlayer insulating film 27 opening 28 conductive film 29 lower electrode 30 capacitive insulating film 31 conductive Film 32 Capacitor insulating film 33 Upper electrode 34 Capacitor element 35 Fourth interlayer insulating film 36 Third contact hole 37 Third contact plug

Claims (11)

Forming a plug made of the first conductive film in the first insulating film on the substrate;
(B) forming a second conductive film made of a noble metal oxide on the plug on the first insulating film;
A step (c) of forming a second insulating film on the second conductive film and the first insulating film;
A step (d) of forming an opening exposing the second conductive film in the second insulating film;
Forming a capacitive element comprising a lower electrode, a capacitive insulating film, and an upper electrode in the opening (e);
A step (f) of removing at least the second insulating film around the capacitive element;
A method of manufacturing a semiconductor device, comprising a step (g) of performing a heat treatment in an oxygen atmosphere after the step (f). A step (a) of forming a first conductive film in a hole formed in the first insulating film on the substrate so as not to completely fill the upper part of the hole;
Forming a second conductive film made of a noble metal oxide on the first conductive film so as to completely fill the hole;
Forming a second insulating film on the second conductive film and the first insulating film (c);
A step (d) of forming an opening exposing the second conductive film in the second insulating film;
Forming a capacitive element comprising a lower electrode, a capacitive insulating film, and an upper electrode in the opening (e);
A step (f) of removing at least the second insulating film around the capacitive element;
A method of manufacturing a semiconductor device, comprising a step (g) of performing a heat treatment in an oxygen atmosphere after the step (f). The step (f)
3. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film above the upper surface of the second conductive film is removed. The step (f)
3. The method of manufacturing a semiconductor device according to claim 1, wherein at least the second insulating film around a side of the capacitor element is left. The step (f)
3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is removed by a wet etching method. The step (f)
3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is removed by a dry etching method. The step (g)
3. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed at a temperature of 650.degree.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the second conductive film is formed of a single layer or a stack of noble metal oxides.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the noble metal oxide is an iridium oxide.   The method of manufacturing a semiconductor device according to claim 1, wherein the plug is made of tungsten. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the capacitor insulating film is made of a ferroelectric film.

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