JP2005346279A - Image compositing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image compositing device for compositing only the necessary part of image data with one image data while reducing the size. <P>SOLUTION: A comparison curcuit 54 compares specific data stored in a buffer 52 with target values Tg-R, Tg-G and Tg-B for judging a specific color, and controls the passage/non-passage of background data in a gate circuit 51 installed on a route on which background data are written in the buffer 52 based an enable signal EN corresponding to the comparison result. The specific color background data of the specific data stored in the buffer 52 are overwritten, and a composite image data are generated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to an image synthesizing apparatus, and more particularly to an image synthesizing apparatus that synthesizes only necessary portions of other image data with one piece of image data.
In recent years, chroma key technology for synthesizing a plurality of image data has been widely used. Further, since it is desired to increase the speed of image composition by the chroma key technology, it is required to increase the speed of an IC (image composition device) for providing the chroma key technology and to reduce the size of the IC.

  Conventionally, there is an image chroma key as a method of combining images. This image chroma key generally includes image data of a background image (hereinafter referred to as background data) obtained by photographing a landscape and the like, and image data (hereinafter referred to as specific data) taken with a specific color (key color) as a background. These are synthesized (for example, see Patent Document 1).

  By the way, in the method of reading image data for each pixel as in the above-mentioned Patent Document 1, it takes time to read the image data because the access to the memory increases, and the processing time of the image data for one screen becomes long. . In view of this, there has been proposed an image composition device provided with a buffer for temporarily storing image data corresponding to each image data (see, for example, Patent Document 2).

  FIG. 11 is a partial block circuit diagram of an image composition apparatus provided with a buffer for each image data. This image composition device synthesizes the specific data 11a and the background data 11b stored in the image memory 11, and temporarily stores the first buffer 12 for temporarily storing the specific data 11a and the background data 11b. And a second buffer 13 to be stored. The apparatus further includes a register 14 for storing background color data of a specific color, and the comparison circuit 15 compares the background color data stored in the register 14 with the specific data read from the first buffer 12. . Then, the selection circuit 16 is controlled based on the comparison result. When the data in the first buffer 12 is background color data, the data (background data) output from the second buffer 13 is output from the selection circuit 16. When the data in the first buffer 12 is not background color data, the data (specific data) output from the first buffer 12 is output from the selection circuit 16. With this configuration, the image composition device synthesizes the pixels other than the specific color included in the specific data 11a with the background data 11b by outputting the background data when the specific data matches the background color data, that is, the specific color. The synthesized data is output.

  The above processing procedure is expressed as shown in FIG. That is, the image composition apparatus first extracts a predetermined number (for example, 16 pixels) of specific data 11a from the image memory 11 (step 21) and stores it in the first buffer 12 (step 22). A predetermined number (for example, 16 pixels) of background data 11b is extracted (step 23) and stored in the second buffer 13 (step 24). Next, the target value is compared with the value of the specific data for each pixel (step 25). If the two values match, the background data is selected (step 26). If the two values do not match, the specific data is selected. Are selected (step 27), and the selected background data or specific data is output to a display device (not shown) (step 28).

Then, the image synthesizing apparatus repeats the processing from step 25 to step 28 by the number of data stored in the first and second buffers 12 and 13, and synthesizes the image data in the first and second buffers 12 and 13. Further, the image composition device repeatedly executes the processing from step 21 to step 28 for all data of the specific data 11a and the background data 11b to synthesize the specific data 11a and the background data 11b.
JP-A-10-307697 JP 2003-280626 A

  By the way, recent semiconductor devices are required to be reduced in size in order to improve yield and cost, and the same applies to the above-described image composition device (IC). However, the above image composition apparatus has the problem that it is difficult to reduce the overall size because two buffers 12 and 13 are required.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide an image composition device capable of reducing the size.

  In order to achieve the above object, according to the invention described in claim 1, 2 or 3, the specific data stored in the buffer and the target value for determining the specific color are compared by the comparison circuit, and the comparison is made. The passage / non-passage of the background data in the gate circuit provided on the path for writing the background data to the buffer is controlled according to the result. Therefore, the specific color background data of the specific data stored in the buffer is overwritten to generate composite image data. Since the specific data and the background data are combined in one buffer, the apparatus size can be reduced.

  According to the fourth aspect of the present invention, the gate circuit is provided on a path for writing the specific data and the background data from the image memory to the buffer, and the specific data passes through the gate circuit when the specific data is read by the control unit. At the time of reading the background data, passage / non-passage of pixels to be written to the buffer is controlled according to the comparison result of the comparison circuit. Accordingly, the passage / non-passage of the background data is controlled corresponding to each pixel of the specific data stored in the buffer, and the background data is easily overwritten on the pixel of the specific color.

  According to the fifth aspect of the present invention, the register stores a target value and an allowable value indicating a predetermined range, and the comparison circuit determines whether the value of the specific data is within the allowable value range including the target value. Is judged. Therefore, it is possible to reliably determine a specific color and combine the specific data and the background data.

  As described above, according to the present invention, since the specific data and the background data are stored in one buffer, the size of the image composition device can be reduced.

Hereinafter, an embodiment embodying the present invention will be described with reference to FIGS.
FIG. 1 is a schematic block diagram of the image composition device 30.
The device 30 includes an image memory 31 as an image storage unit, a control unit 32, and an image composition unit 33.

  The image memory 31 stores a plurality (two in FIG. 1) of image data 31a and 31b. The first image data 31a (denoted as image 1 in the figure) is data of an image (synthesized image) P1 of a subject (for example, a person as shown in FIG. 6) photographed with a specific color (key color) in the background. This data is hereinafter referred to as specific data 31a. The second image data 31b (denoted as image 2 in FIG. 1) is data of a background image P2 obtained by photographing a landscape as shown in FIG. 6, for example, and this data is hereinafter referred to as background data 31b.

  The specific data 31a and the background data 31b are composed of a plurality of pixels, and each pixel is composed of three color (RGB) points, and a color image is expressed by the strength of these colors. Therefore, the specific data 31a and the background data 31b include pixel data of a plurality of pixels constituting the images P1 and P2, and each pixel data includes color data of three colors. Each color data is composed of a predetermined number of bits (for example, 8 bits).

  The image synthesizing device 30 synthesizes the synthesized image P1 and the background image P2 shown in FIG. 6 to generate a synthesized image P3, that is, synthesizes the background data 31b and the specific data 31a to generate synthesized image data. . Specifically, for each pixel constituting the specific data 31a, the image composition device 30 constitutes the background data 31b when the color of the pixel matches a specific color (background color), and the pixel at the same position as the pixel. Is the combined data, and if they do not match, the pixel (the pixel of the specific data 31a) is set as the combined data.

  The image composition unit 33 synthesizes the specific data 31a and the background data 31b to generate composite data, and the control unit 32 reads the image data from the image memory 31 and combines the image data in the image composition unit 33. Control.

As shown in FIG. 1, the control unit 32 includes an address register 41, a control circuit (signal generation circuit) 42, and counters 43 and 44.
The address register 41 stores a read start address of each image data. For example, the address register 41 stores a start address ST1 for starting reading of the specific data 31a stored in the image memory 31 and a start address ST2 for starting reading of the background data 31b stored in the image memory 31. Yes.

  The address register 41 stores a head address of data to be read next from the image memory 31. The address register 41 stores an address of background data 31b to be read next from the image memory 31.

  The first counter 43 is, for example, an up counter, and is used for sequentially reading the specific data 31 a stored in the image memory 31. The first counter 43 starts counting up in response to a command signal from the control circuit 42 and outputs the count value to the control circuit 42. Further, the first counter 43 outputs a count-up signal to the control circuit 42 when the count value matches the count-up value corresponding to the data amount (for example, 16 pixels) of the specific data 31a read out from the image memory 31 at a time. To do.

  The second counter 44 is, for example, an up counter, and is used to sequentially read the background data 31b stored in the image memory 31. The second counter 44 starts counting up in response to the command signal from the control circuit 42 and outputs the count value to the control circuit 42. The second counter 44 outputs a count-up signal to the control circuit 42 when the count value matches the count-up value corresponding to the data amount (for example, 16 pixels) of the background data 31b read out from the image memory 31 at a time. To do.

  The first counter 43 starts counting up in response to a command signal from the control circuit 42 and outputs the count value to the control circuit 42. The control circuit 42 adds the count value to the start address ST1 or the head address AD1 of the address register 41, and outputs the addition result to the image memory 31 as the read address ADD1 at that time. In response to the read address ADD1, the image memory 31 outputs the image data of the address ADD1.

  The second counter 44 starts counting up in response to the command signal from the control circuit 42 and outputs the count value to the control circuit 42. The control circuit 42 adds the count value to the start address ST1 or the head address AD1 of the address register 41, and outputs the addition result to the image memory 31 as the read address ADD1 at that time. In response to the read address ADD2, the image memory 31 outputs the image data of the address ADD2.

  The control circuit 42 outputs a comparison command signal CCOMP based on the count up signal from the first counter 43. Further, the control circuit 42 outputs an output command signal COUT based on the count up signal of the second counter 44.

The image composition unit 33 includes a gate circuit 51, a buffer 52, a target register 53, and a comparison circuit 54.
The buffer 52 is a memory capable of storing image data of a predetermined number of pixels. The capacity of the buffer 52 is substantially the same as the capacity of the first and second buffers 12 and 13 shown in the conventional example. In this embodiment, the capacity of the image data of 16 pixels can be stored. .

  The gate circuit 51 is connected between the image memory 31 and the buffer 52, and permits or prohibits transfer of image data from the image memory 31 to the buffer 52 for each pixel in response to an enable signal EN described later.

The gate circuit 51 includes a number of sub-circuits corresponding to the storage capacity of the buffer 52.
FIG. 3 is a block diagram showing a configuration example of the gate circuit 51, and shows a sub-circuit for one pixel. This sub-circuit will be described as a gate circuit 51a.

  The gate circuit 51 a includes a register 61 and an AND circuit 62. The register 61 has a storage capacity of 1 bit and stores an enable signal EN. In the present embodiment, the enable signal EN is a signal having a number of bits equal to the number of pixels stored in the buffer 52, and the gate circuit 51a stores information on the bit position corresponding to itself. This bit position information will be described simply as an enable signal EN.

  For example, the register 61 stores a value “1” when the enable signal EN is “1” (H level), and stores a value “0” when the enable signal EN is “0” (L level). To do. Then, the register 61 outputs a signal having a level corresponding to the stored value. That is, the register 61 outputs an H level signal when the value “1” is stored, and outputs an L level signal when the value “0” is stored.

  The AND circuit 62 receives image data (specific data 31a or background data 31b) for one pixel read from the image memory 31 and an output signal of the gate circuit 51a. The AND circuit 62 outputs a signal having substantially the same level as the input signal when the output signal of the register 61 is at the H level, that is, outputs image data substantially the same as the input image data. When the output signal 61 is at L level, no image data is output.

  As shown in FIG. 1, the register 61 is supplied with a set signal SET from the control circuit 42. The register 61 stores “1” in response to the set signal SET. That is, the gate circuit 51a outputs image data that is substantially the same as the image data that is input when the register 61 stores "1" by the set signal SET.

  That is, the gate circuit 51a including the register 61 storing “1” by the enable signal EN or the set signal SET passes the signal from the image memory 31 and includes the register 61 storing “0” by the enable signal EN. The circuit 51a does not pass the signal from the image memory 31.

  The control circuit 42 supplies a set signal SET to the register 61 when reading the specific data 31 a from the image memory 31. Therefore, the gate circuit 51 a stores a predetermined number of specific data 31 a read from the image memory 31 through the gate circuit 51 a and is stored in the buffer 52.

  As shown in FIG. 1, the target register 53 stores target values Tg-R, Tg-G, and Tg-B indicating the background color of the specific data 31a. As for the target value, the number of bits of the target value of the specific data is set to the same number as the number of bits of the pixels constituting the image data stored in the image memory 31.

  As shown in FIG. 2, the image data (for example, specific data 31a) is composed of a plurality of pixel data 71, and each pixel data 71 includes three color data of red (R), green (G), and blue (B). 72. In the following description, red color data is R data, green color data is G data, and blue color data is B data. That is, the image data of one pixel is composed of R data, G data, and B data. Each color data is composed of a predetermined number of bits (for example, 8 bits). The target register 53 is provided corresponding to each color, and the target value of each color is set according to the background color of the specific data 31a. For example, when the background color is blue, the red target value Tg-R is set to “0”, the green target value Tg-G is set to “0”, and the blue target value Tg-B is set to “255”.

  As shown in FIG. 1, the target register 53 stores allowable values th-R, th-G, and th-B. This allowable value is used to give a wide range to the coincidence determination in the comparison determination in the comparison circuit 54 described later. For example, when the background color of the specific data is blue, the target values Tg-R, Tg-G, and Tg-B of each color are (R: 0, G: 0, B: 255). However, it is extremely rare that the prepared background color (specific color) completely matches the target values Tg-R, Tg-G, and Tg-B. This is because the prepared background color is different from perfect blue, or because the value of the color data 72 is different from perfect blue depending on the condition of light rays. Therefore, the target value of each color is given a width, and image data that falls within the width is determined as the background, so that even image data with slightly different background colors can be combined. For example, when the permissible value of each color is (r: 10, g: 10, b: 10), the comparison circuit 54 has an image in which R data is 0 to 10, G data is 0 to 10, and B data is 245 to 255. Judge that the data matches the target value.

  As shown in FIG. 1, the comparison circuit 54 responds to the comparison command signal CCOMP from the control circuit 42, each color data constituting the image data of each pixel stored in the buffer 52, and the target value read from the register 53. Enable signal EN that compares Tg-R, Tg-G, and Tg-B, compares the color data with target values Tg-R, Tg-G, and Tg-B, and has a bit arrangement corresponding to the comparison result Is generated. In the present embodiment, the comparison circuit 54 determines that the color data and the target value match (specifically, the color data value is included in the allowable value range centered on the target value). The bit corresponding to the position of the color data is set to “1”, and if they do not match, it is set to “0”. For example, when the image data of the first pixel matches the target value, the comparison circuit 54 sets the first bit of the enable signal EN to “1”.

  The target value corresponds to the background color of the specific data 31a. Therefore, when the color of the image data to be compared is the background color, the comparison circuit 54 sets the bit corresponding to the pixel to “1”. That is, the comparison circuit 54 sets the corresponding bit of the enable signal EN to “1” when the image data of the plurality of pixels stored in the buffer 52 is the background color.

  The enable signal EN generated by the comparison circuit 54 is input to the gate circuit 51, and the gate circuit 51 stores the state of each bit of the enable signal EN in the register 61 (see FIG. 3). Then, the gate circuit 51 outputs the image data input to the gate circuit 51 a including the register 61 in which “1” is set to the buffer 52. Background color image data is stored in the buffer 52 corresponding to the bit in which “1” is set among the plurality of bits constituting the enable signal EN. Therefore, the image data read out from the image memory 31 next by the enable signal EN is written in the area where the background color image data is stored. That is, the background color image data is overwritten by the next input image data.

  On the other hand, the gate circuit 51 does not output the image data input to the gate circuit 51a including the register 61 in which “0” is set. Among the plurality of bits constituting the enable signal EN, the buffer 52 corresponding to the bit set to “0” stores image data of a color other than the background color, that is, image data of the subject. Therefore, the image data read from the image memory 31 next by the enable signal EN is not written in the area in which the image data of the subject is stored.

  That is, the image composition unit 33 determines whether or not the image data of the plurality of pixels stored in the buffer 52 is background color image data, and if the image data is background color, the next image data is the background color image data. The image data was overwritten. Accordingly, the specific data 31a and the background data 31b are combined in the buffer 52 to generate combined image data. Therefore, the buffer 52 only needs to store one-time image data read from the image memory 31, and the area of the image synthesis device 30 or the semiconductor integrated circuit device including the image synthesis device 30 can be reduced accordingly.

FIG. 4 is a flowchart of an image composition process executed in the image composition apparatus 30 configured as described above, and FIG. 5 is a schematic diagram showing a data flow.
First, the image composition device 30 takes out a predetermined number (for example, 16 pixels) of specific data 31a (image 1) from the image memory 31 (step 81) and stores it in the buffer 52 (step 82). Next, the image composition device 30 compares the specific data 31a stored in the buffer 52 with the target value (step 83), and if they match, the writing of the bit is permitted (corresponding bit of the enable signal EN) Is set to "1") (step 84). On the other hand, when the specific data 31a and the target value do not match, the image composition device 30 prohibits writing of the bit (sets the corresponding bit of the enable signal EN to “0”) (step 85).

  Then, the image composition device 30 determines whether or not the comparison with the target value has been completed for all the pixels in the buffer 52 (step 86), and if not completed, proceeds to step 82 and ends. If yes, the process proceeds to the next step 87. That is, the image composition device 30 repeatedly executes the processing of steps 82 to 85 to determine whether or not all the pixels in the buffer 52 match the target value. Actually, the comparison circuit 54 is configured to execute an operation of comparing a plurality of data in parallel, and a predetermined number (16 pixels) of specific data (R data, G) is performed by one comparison operation. (Data, B data) and the target values Tg-R, Tg-G, Tg-B are determined to match. In this determination, as described above, the image synthesizing device 30 sets the values of the image data to the target values Tg-R, Tg-G, Tg-B with the allowable values th-R, th-G, th-B. It is judged whether or not it matches the considered value.

  Next, the image composition device 30 takes out a predetermined number (for example, 16 pixels) of background data 31b (image 2) from the image memory 31 (step 87), and obtains background data 31b corresponding to the bits permitted by the enable signal EN. Write to the buffer 52 (step 88). Then, the image composition device 30 outputs the image data in the buffer 52 to, for example, a display device (not shown) (step 89). At this time, the specific data 31a and the background data 31b are partially stored in the buffer 52. Therefore, composite image data obtained by combining the specific data 31a and the background data 31b is output to the display device.

  Next, the image synthesizer 30 determines whether or not the processing has been completed for all the specific data 31a in the image memory 31 (step 90), and if not, proceeds to step 81 and ends. If so, the series of processing ends. That is, the image composition device 30 repeatedly executes the processing of steps 81 to 90 to synthesize the specific data 31a and the background data 31b.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The comparison circuit 54 compares the specific data stored in the buffer 52 with the target values Tg-R, Tg-G, and Tg-B for determining a specific color, and enables according to the comparison result. Based on the signal EN, the passage / non-passage of the background data in the gate circuit 51 provided on the path for writing the background data to the buffer 52 is controlled. Therefore, the specific color background data of the specific data stored in the buffer 52 is overwritten to generate composite image data. Since the specific data and the background data are combined in one buffer 52, the apparatus size can be reduced.

  (2) The gate circuit 51 is provided on a path for writing specific data and background data from the image memory 31 to the buffer 52, and the control circuit 42 passes the specific data through the gate circuit 51 when reading the specific data. At the time of data reading, the passage / non-passing of pixels to be written to the buffer 52 is controlled according to the comparison result of the comparison circuit 54. Accordingly, since the passage / non-passage of the background data is controlled corresponding to each pixel of the specific data stored in the buffer 52, the background data is easily overwritten on the pixel of the specific color, and the composite image data is saved. Can be generated.

  (3) The target value Tg-R, Tg-G, Tg-B and an allowable value indicating a predetermined range are stored in the target register 53, and the comparison circuit 54 determines that the value of the specific data is the target value Tg-R, Tg. It is determined whether or not the value is within the range of allowable values th-R, th-G, and th-B including -G and Tg-B, and whether or not the specific data matches the target value. Therefore, it is possible to reliably determine a specific color while allowing an error, and to combine the specific data and the background data.

In addition, you may implement the said embodiment in the following aspects.
In the above embodiment, the configuration / operation of the control unit 32 may be changed as appropriate. For example, the control circuit 42 may store the address of the image data to be read next in the address register 41 when reading of the image data of a predetermined number of pixels is completed. The first and second counters 43 and 44 are used to read the specific data 31a and the background data 31b, respectively. However, the first counter 43 is used to generate an address for reading the specific data 31a and the background data 31b. The second counter 44 may be used as a counter for counting the number of readings.

  In the above embodiment, as indicated by a broken line in FIG. 5, composite image data obtained by combining the specific data 31a and the background data 31b, that is, data output from the buffer 52 may be stored in the image memory 31.

  In the above embodiment, the specific data 31a and the background data 31b are continuous color data 72 (three color data of red (R), green (G), and blue (B)) constituting one pixel data 71. However, it may be stored for each color data as shown in FIG. In this case, the control unit 32 generates an address signal to be output to the image memory 31 so as to read a predetermined number (for example, 16) of color data from each block.

  In the above embodiment, the information of the register 61 included in the gate circuit 51a is set (“1”) so that the specific data 31a passes through the gate circuit 51a. good.

  For example, the gate circuit 91 shown in FIG. The gate circuit 91 is read from the register 92 for storing the enable signal EN, the OR circuit 93 to which the output signal of the register 92 and the selection signal SEL are input, the output signal of the OR circuit 93 and the image memory 31. And an AND circuit 94 to which the image data is input. The control unit 32 generates the selection signal SEL so that the specific data 31 a passes through the gate circuit 91 and the passage / non-passage of the background data 31 b is controlled by the state of the register 92. For example, the H level selection signal SEL is output when the specific data 31a is read, and the L level selection signal SEL is output when the background data 31b is read. With this configuration, it is not necessary to set the information in the register 92, and it is easy to control the specific data 31a to pass and the background data 31b to pass / non-pass through the register 92 (enable signal EN). be able to.

  Also, as shown in FIG. 8B, a switch 95 is provided, and the specific data 31 a read from the image memory 31 by the selection signal SEL similar to the above is provided in the buffer 52 without going through the gate circuit 51. So that the background data 31b is input to the buffer 52 via the gate circuit 51. According to this configuration, it is not necessary to set the information in the register 92, and it is easy to control the specific data 31a to be stored in the buffer 52 and the background data 31b to be stored in the buffer 52 by the register 92 (enable signal EN). Can be done.

  In the above embodiment, the target values Tg-R, Tg-G, Tg-B and the allowable values th-R, th-G, th-B are stored in the target register 53. It may be stored in a different register.

  In the above embodiment, the image composition device 30 includes the image memory 31, but the image composition device and the image memory may be configured as separate semiconductor devices. That is, one semiconductor device in which an image composition device including the control unit 32 and the image composition unit 33 is formed is connected to a semiconductor device in which the image memory 31 is formed. Even if comprised in this way, the effect similar to said each embodiment can be acquired.

In the above embodiment, the image composition processing shown in FIG. 4 may be changed as appropriate. For example, you may change to the image composition process containing steps 101-111 shown in FIG.
In this image composition processing, steps 101 to 106 are substantially the same as steps 81 to 86 shown in FIG.

  After confirming that all the pixels in the buffer 52 have been compared with the target value in step 106, the image composition apparatus 30 determines in step 107 whether or not all writing is prohibited for the corresponding pixels. Judging. Then, the image synthesizing device 30 proceeds to Step 110 when writing of all pixels is not permitted. That is, the image composition device 30 does not execute Steps 108 and 109 when writing of all pixels is not permitted. Steps 108 to 111 are substantially the same as steps 87 to 90 shown in FIG. 4. These steps 108 and 109 are processes for reading background data from the image memory 31 and storing the background data in the buffer 52. . If writing of all pixels is not permitted, the gate circuit 51 does not pass the background data. That is, reading of background data is useless. For this reason, the image synthesizing apparatus 30 skips steps 108 and 109 and executes step 110 when writing of all pixels is not permitted (all pixels do not pass through the gate circuit 51). Without reading, the image data in the buffer 52 is output as it is. With this configuration, when the writing of all pixels is not permitted, the background data is not read, so that the overall processing time can be shortened by the time required for the reading.

The technical ideas that can be grasped from the above embodiments are described below.
(Appendix 1)
In an image composition device that generates composite image data by superimposing background data on a background of a specific color for specific data having a specific color as a background,
A buffer for storing the specific data;
A comparison circuit for comparing the target value for determining the specific color with the specific data;
A gate circuit that is provided on a path for writing the background data to the buffer in which the specific data is stored, and that controls passage / non-passage of the background data according to a comparison result of the comparison circuit;
An image composition device comprising:
(Appendix 2)
An image composition unit that generates composite image data by superimposing background data on the background of the specific color for specific data having a specific color background, and a control unit that controls the image composition unit,
The image composition unit
A buffer for storing the specific data;
A comparison circuit for comparing the target value for determining the specific color with the specific data;
A gate circuit that is provided on a path for writing the background data to the buffer in which the specific data is stored, and that controls passage / non-passage of the background data according to a comparison result of the comparison circuit;
An image composition device comprising:
(Appendix 3)
An image composition unit that generates composite image data by superimposing background data on the background of the specific color with respect to specific data having a specific color as a background;
An image memory for storing the specific data and the background data;
A control unit for controlling reading of the specific data and the background data from the image memory,
The image composition unit
A buffer for storing specific data read from the image memory;
A comparison circuit for comparing the target value for determining the specific color with the specific data;
A gate circuit that is provided on a path for writing the background data read from the image memory to the buffer in which specific data is stored, and controls passage / non-passage of the background data according to a comparison result of the comparison circuit When,
An image composition device comprising:
(Appendix 4)
The gate circuit is provided on a path for writing the specific data and the background data from the image memory to the buffer,
The control unit controls passing / non-passing of pixels to be written to the buffer according to a comparison result of the comparison circuit according to a comparison result of the comparison circuit when reading the background data, while the specific data passes through the gate circuit when reading the specific data. ,
The image synthesizing device according to Supplementary Note 3, wherein
(Appendix 5)
A register for storing the target value;
A register for storing an allowable value indicating a predetermined range;
5. The image composition according to claim 1, wherein the comparison circuit determines whether the value of the specific data is within a range of the allowable value including the target value. apparatus.
(Appendix 6)
Based on the comparison result of the comparison circuit, the control unit stores all the background data to be overwritten on the specific data in the buffer without reading the background data when not passing through the gate circuit. The image synthesizing apparatus according to any one of supplementary notes 1 to 5, wherein the specific data is output as composite image data.

It is a schematic block diagram of an image composition apparatus. It is explanatory drawing which shows the arrangement | sequence of image data. It is a partial circuit diagram of a gate circuit. It is a flowchart of an image composition process. It is the schematic which shows the flow of data. It is explanatory drawing of image composition. It is explanatory drawing which shows the arrangement | sequence of another image data. (A) and (b) are some block diagrams of another image composition apparatus. It is a flowchart of another image composition process. It is a flowchart of the conventional image composition process. It is the schematic which shows the flow of the conventional data.

Explanation of symbols

DESCRIPTION OF SYMBOLS 30 Image composition apparatus 31 Image memory 31a Specific data 31b Background data 32 Control part 33 Image composition part 51,51a Gate circuit 52 Buffer 53 Register 54 Comparison circuit
Tg-R, Tg-G, Tg-B Target value
th-R, th-G, th-B tolerance

Claims (5)

In an image composition device that generates composite image data by superimposing background data on a background of a specific color for specific data having a specific color as a background,
A buffer for storing the specific data;
A comparison circuit for comparing the target value for determining the specific color with the specific data;
A gate circuit that is provided on a path for writing the background data to the buffer in which the specific data is stored, and that controls passage / non-passage of the background data according to a comparison result of the comparison circuit;
An image composition device comprising: An image composition unit that generates composite image data by superimposing background data on the background of the specific color for specific data having a specific color background, and a control unit that controls the image composition unit,
The image composition unit
A buffer for storing the specific data;
A comparison circuit for comparing the target value for determining the specific color with the specific data;
A gate circuit that is provided on a path for writing the background data to the buffer in which the specific data is stored, and that controls passage / non-passage of the background data according to a comparison result of the comparison circuit;
An image composition device comprising: An image composition unit that generates composite image data by superimposing background data on the background of the specific color with respect to specific data having a specific color as a background;
An image memory for storing the specific data and the background data;
A control unit for controlling reading of the specific data and the background data from the image memory,
The image composition unit
A buffer for storing specific data read from the image memory;
A comparison circuit for comparing the target value for determining the specific color with the specific data;
A gate circuit that is provided on a path for writing the background data read from the image memory to the buffer in which specific data is stored, and controls passage / non-passage of the background data according to a comparison result of the comparison circuit When,
An image composition device comprising: The gate circuit is provided on a path for writing the specific data and the background data from the image memory to the buffer,
The control unit controls passing / non-passing of pixels to be written to the buffer according to a comparison result of the comparison circuit according to a comparison result of the comparison circuit when reading the background data, while the specific data passes through the gate circuit when reading the specific data. ,
The image synthesizing device according to claim 3. A register for storing the target value;
A register for storing an allowable value indicating a predetermined range;
5. The comparison circuit according to claim 1, wherein the comparison circuit determines whether the value of the specific data is within a range of the allowable value including the target value. 6. Image composition device.

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