JP4576963B2 - Address calculation for DMA transfer - Google Patents

Description

  The present invention relates to an address calculation for DMA transfer.

  FIG. 12 is an explanatory diagram showing address calculation by a conventional DMA controller. The conventional DMA controller receives the start address of the source area 21A, the start address of the destination area 22A, and the transfer data length, and transfers data for the transfer data length from the source area 21A of the memory to the destination area 22A. The address calculation was performed. The transfer data at this time is data continuously stored in the source area 21A, and is continuously stored in the destination area 22A in the same order by transfer.

Japanese Patent Application No. Sho 61-235907

  By the way, the image data is often composed of data of one pixel in units of (X (auxiliary region), R (red), G (green), B (blue)). At this time, when processing is performed in units of R component (a set of elements such as R0 and R1), G component, and B component, it is desired to extract three color components from each pixel data and transfer them to different destination areas. There is a request. However, in order to realize such a transfer with the conventional DMA controller, the CPU has to issue a transfer instruction to the DMA controller many times, and there is a problem that it takes a lot of time.

  Such a problem is not limited to the transfer of image data, and is generally a problem that is common when complex data transfer is required.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a technique for performing complex address calculation for DMA transfer.

In order to solve at least a part of the above problems, a DMA controller according to the present invention includes:
A DMA controller for transferring data in a source area to a destination area,
A source address calculation unit for calculating an address of data in the source region;
A destination address calculation unit for calculating an address of the destination area;
With
Each of the source address calculation unit and the destination address calculation unit can calculate an address related to an N-layer data block having an N-dimensional (N is an integer of 2 or more) hierarchical structure,
The N-layer data block is configured as a set of data elements having a specified data length DL in a memory area after a specified start address,
When the data element is defined as a data block in the 0th layer, a data block in the i-th layer (i is an integer from 1 to N) is designated as a data block in the (i-1) -th layer. The offset L (i) -offset has a configuration in which the designated number of blocks L (i) -n is repeatedly arranged,
Each of the source address calculator and the destination address calculator is
A start address storage unit for storing the start address;
A data length storage unit for storing the data length DL;
An offset storage unit for storing N offsets L (i) -offset (i is an integer from 1 to N) for data blocks from the first layer to the Nth layer;
A block number storage unit for storing N block numbers L (i) -n (i is an integer from 1 to N) for data blocks from the first layer to the Nth layer;
Based on the start address, the data length DL, the N offsets L (i) -offset, and the N block numbers L (i) -n, the source region or the destination region An address calculation execution unit for performing an address calculation for the N-layer data block;
Equipped with a,
The destination address calculation unit, configurable der Rukoto to a value different from that of the offset L (i) -offset offset L (i) -offset in at least the i-th layer of the data block in the source address calculation unit It is characterized by.

  According to the present invention, it is possible to execute a complicated address calculation for DMA transfer by calculating an address relating to an N-layer data block. Further, it is possible to execute an address calculation required until the transfer of the N-layer data block is completed inside the DMA controller.

  The source address calculation unit and the destination address calculation unit include the start address, the data length DL, the N offsets L (i) -offset, and the N block numbers L (i) -n. These values may be set independently of each other.

  According to this, it is possible to perform an address operation in which the source region and the destination region are asymmetric with each other.

The address calculation execution unit
A signal indicating that the transfer of the data element as the data block of the 0th layer is completed once based on the relationship between the accumulated value of the amount of data transferred in one data transfer and the data length DL A data length counter to
(I-1) Transfer of the i-th layer data block from the relationship between the number of transfers of the data block in the (i-1) th layer (i is an integer from 1 to N) and the number of blocks L (i) -n N number of i-th layer counters that output a signal indicating that is completed once,
An offset selection unit that selects and outputs the offset L (i) -offset of the i-th layer each time the transfer of the data block of the (i-1) -th layer is completed once;
The amount of data transferred in the one-time data transfer is sequentially added to the start address, and when the offset L (i) -offset of the i-th layer is output from the offset selection unit, Furthermore, an addition unit that sequentially generates addresses of data to be transferred by adding the offset L (i) -offset of the i-th layer may be provided.

  Further, the amount of data transferred in the one-time data transfer may be variable.

  The present invention can be realized in various forms, for example, in the form of an address calculation device, an address calculation method, and the like.

  FIG. 1 is an explanatory diagram showing a computer system including a DMA controller (hereinafter referred to as DMAC) 1000. The DMAC 1000 is a device for transferring data in the source area 21 in the memory 20 to the destination area 22. The DMAC 1000 is connected to the bus 1100 and can transmit information to and from the CPU 10 and the memory 20.

  The DMAC 1000 includes a control unit 100, a source address arithmetic circuit 200, a destination address arithmetic circuit 300, a bus interface 400, and a buffer unit 500. The buffer unit 500 includes a source buffer 520 and a destination buffer 530.

  FIG. 2 is a block diagram showing the internal configuration of the source address arithmetic circuit 200. The source address arithmetic circuit 200 includes a start address register 210, an inter-element offset register 221, an inter-unit offset register 222, an inter-set offset register 223, a data length counter 230, an element number counter 231, and a unit number counter 232. A set number counter 233, a first multiplexer 250, a first decoder 260, a second decoder 262, a second multiplexer 252, a first adder 270, and a second adder 272. And a third multiplexer 254 and an address register 280. The registers 210 and 221 to 223 and the counters 230 to 233 respectively hold parameters set by the CPU 10.

FIG. 3 is an explanatory diagram showing the meanings of the parameters SA, Eoffset, Uoffset, and Soffset set in the registers 210 and 221 to 223 and the parameters DL, En, Un, and Sn set in the counters 230 to 233. In FIG. 3, the data area to be transferred is configured as a three-layer data block having a three-dimensional hierarchical structure. This three-layer data block has the following configuration.
(1) 0th layer data block L0DB: continuous data having a data length DL. In the example of FIG. 3, DL = 3 bytes, and one 0th layer data block L0DB is configured by 3 bytes. Note that a rectangle marked “B” inside indicates one byte. Since the 0th hierarchical data block L0DB is a basic data unit of this hierarchical structure data, it is also called a “data element”. The 0th layer data block L0DB is also simply referred to as “element”.
(2) First tier data block L1DB: A data group in which the 0th tier data block L0DB is repeatedly arranged by the number of elements En while being spaced apart from each other by an element offset Eoffset. The first tier data block L1DB is also referred to as “unit”. The element offset Eoffset corresponds to the first layer offset L (1) -offset of the present invention, and the element number En corresponds to the first layer block number L (1) -n of the present invention.
(3) Second tier data block L2DB: A data group in which the first tier data block L1DB is repeatedly arranged by the number of units Un separated from each other by an inter-unit offset Uoffset. The second tier data block L2DB is also referred to as “set”. The inter-unit offset Uoffset corresponds to the second layer offset L (2) -offset of the present invention, and the unit number Un corresponds to the second layer block number L (2) -n of the present invention.
(4) Third tier data block L3DB: a data group in which the second tier data block L2DB is repeatedly arranged by the number of sets Sn spaced apart from each other by the inter-set offset Soffset. The third hierarchical data block L3DB is also called a “set group”. The offset between sets Soffset corresponds to the offset L (3) -offset of the third layer of the present invention, and the set number Sn corresponds to the number of blocks L (3) -n of the third layer of the present invention.

  Note that the 0th layer data block L0DB can be considered as the 1st layer, and the data structure of FIG. 3 can also be considered as a four-dimensional (ie, 4 layer) data block.

  Again, returning to FIG. Each of the counters 230 to 233 sequentially subtracts the values of the parameters DL, En, Un, and Sn set therein, and when the count values DL-c, En-c, Un-c, Sn-c become zero. Then, the initial values DL, En, Un, and Sn are returned and the subtraction is repeated. These count values are referred to as “remaining data length DL-c”, “remaining element number En-c”, “remaining unit number Un-c”, and “remaining set number Sn-c”. Each of the counters 230 to 233 has a register corresponding to the block number storage unit of the present invention.

  The first decoder 260 determines the transfer data byte number Db based on the remaining data length DL-c given from the data length counter 230 and the current address Adr given from the address register 280. The transfer data byte number Db is the amount of data transferred in one data transfer. The first decoder 260 may determine the transfer data byte number Db to be a constant value, or may determine it to vary based on the number of transfers and the remaining data length DL-c. For example, the transfer data byte count Db may be changed to 1 byte, 2 bytes, 4 bytes, or 8 bytes. That is, the amount of data transferred in one data transfer can be made variable. The second multiplexer 252 selects and outputs one of the transfer data byte number Db and the value “0” in accordance with the selection signal S1 supplied from the control unit 100 (FIG. 1). Specifically, the number of transfer data bytes Db is selected during execution of data transfer, and the value “0” is selected when data transfer is not being executed.

  The second decoder 262 generates the selection signal S2 according to the count values DL-c, En-c, Un-c, Sn-c given from the four counters 230 to 233, and the first multiplexer 250. To supply. The counters 231 to 233 correspond to the i-th layer counter of the present invention.

  The first multiplexer 250 selects and outputs one of the four values of three offsets Eoffset, Uoffset, and Soffset and the value “0” in accordance with the selection signal S2. Specifically, when the remaining data length DL-c becomes 0, the inter-element offset Eoffset is selected. When the number of remaining elements En-c becomes 0, an inter-unit offset Uoffset is selected. Further, when the number of remaining units Un-c becomes 0, an inter-set offset Soffset is selected. When none of the four count values DL-c, En-c, Un-c, and Sn-c is 0, the value “0” is selected. The first multiplexer 250 corresponds to the offset selection unit of the present invention.

  The first adder 270 adds the values output from the first and second multiplexers 250 and 252. The addition result is added to the current address Adr in the second adder 272.

  The third multiplexer 254 selects and outputs one of the start address SA and the addition result of the second adder 272 according to the selection signal S3 supplied from the control unit 100. Specifically, the start address SA is selected only at the start of transfer, and thereafter, the addition result of the second adder 272 is selected. The address register 280 holds the output of the third multiplexer 254 as the current address Adr and supplies it to the bus interface 400. The first decoder 260, the second and third multiplexers 252, 254, the first and second adders 270, 272, and the address register 280 correspond to the adder of the present invention.

  The destination address calculation circuit has the same configuration as that shown in FIG. Various parameters SA, Eoffset, Uoffset, Soffset, DL, En, Un, and Sn in the source address arithmetic circuit 200 can be set independently of these parameters in the destination address arithmetic circuit 300. In the source address arithmetic circuit 200 and the destination address arithmetic circuit, the parameters SA, Eoffset, Uoffset, Soffset, DL, En, Un, and Sn may all be set to the same value. In this case, the source region 21 and the destination region 22 are symmetrical to each other (the data array is the same).

  FIG. 4 is a flowchart showing the address calculation process. In the address calculation process, the CPU 10 sets various parameters (element number En, unit number Un, set number Sn, data length DL, inter-element offset Eoffset, inter-unit offset Uoffset, inter-set offset Soffset, start address SA). After the data transfer instruction is output to the DMAC 1000, it is executed by the source address arithmetic circuit 200 and the destination address arithmetic circuit 300 (hereinafter, the source address arithmetic circuit 200 and the destination address arithmetic circuit 300 are simply referred to as address arithmetic circuits). .

  In the address calculation process, there are four loops: a set group loop rp3, a set loop rp2, a unit loop rp1, and an element loop rp0. In the element loop rp0 (0th hierarchy loop), the address calculation of the 0th hierarchy data block L0DB (element) in FIG. 3 is executed. The unit loop rp1 (first hierarchy loop) executes an address calculation in the first hierarchy data block L1DB (unit) in FIG. In the set loop rp2 (second hierarchy loop), an address operation in the second hierarchy data block L2DB (set) in FIG. 3 is executed. In the set group loop rp3 (third hierarchy loop), an address operation in the third hierarchy data block L3DB (set group) in FIG. 3 is executed. The address calculation process will be described below with reference to the circuit of FIG.

  The selection signal S3 supplied to the third multiplexer 254 is set by the control unit 100 to output the start address SA at the beginning of the address calculation process. The third multiplexer 254 stores the start address SA stored in the start address register 210 in the address register 280 in accordance with the selection signal S3. As a result, the current address Adr becomes the start address SA (step S10).

  FIG. 6 is an explanatory diagram schematically showing a memory area to be transferred. One square in FIG. 6 represents one byte. The left end of FIG. 6A is designated as the start address SA. Hereinafter, the address calculation process will be described with reference to FIG.

  When the address arithmetic circuit starts the set group loop rp3 (FIG. 4), the unit number counter 232 returns the remaining unit number Un-c to the initial value Un (step S20). When the address arithmetic circuit starts the set loop rp2, the element number counter 231 returns the remaining element number En-c to the initial value En (step S30). When the address arithmetic circuit starts the unit loop rp1, the data length counter 230 returns the remaining data length DL-c to the initial value DL (step S40). Note that these processes are necessary for returning the parameter values to the initial values before executing the loop process again because the value of each parameter becomes 0 by the counter during the address calculation process. However, since the current values are still the initial values set by the CPU 10, steps S20, S30, and S40 can be omitted at the first execution of the entire loop of FIG.

  The element loop rp0 is a loop for outputting an address corresponding to the data length DL. In the example of FIG. 6A, the data length DL is 3 bytes, and addresses of 3 bytes of data X11, data X22, and data X33 are output by the element loop rp0.

  Therefore, in the element loop rp0, first, the current address Adr is output (step S50). Since the current address Adr is now the start address SA, the leftmost start address SA in FIG. 6A is output, and the first address of the data X11 (hereinafter simply referred to as an address) is designated.

  In the element loop rp0, next, the output data byte number Db is added to the current address Adr which is the value of the address register 280 (step S60). The number of output data bytes Db indicates the number of bytes of data transferred by one data transfer. The number of output data bytes Db is normally set to a value less than or equal to the data length DL.

  The address arithmetic circuit in FIG. 2 executes the process of step S60 as follows. The first decoder 260 of FIG. 2 refers to the remaining data length DL-c and the current address Adr, and outputs the number of output data bytes Db according to how much data the control unit 100 of FIG. 1 can transfer. Is output. In the present embodiment, the first decoder 260 always sets the output data byte count Db to 1 byte.

  The second multiplexer 252 in FIG. 2 outputs the output data byte number Db (value “1”) output from the first decoder 260 to the first adder 270. The selection signal S1 supplied to the second multiplexer 252 is designated by the control unit 100 to output the output data byte number Db during execution of data transfer. On the other hand, the second decoder 262 generates the selection signal S2 based on the remaining data length DL-c. The selection signal S2 is generated so that the first multiplexer 250 outputs “0” unless the remaining data length DL-c is “0”. Since the remaining data length DL-c is 3 bytes now, the first multiplexer 250 outputs “0”. Therefore, the first adder 270 adds the output data byte number Db (value “1”) and “0”, and outputs the output data byte number Db (value “1”).

  The second adder 272 adds the current address Adr (now the start address SA) and the number of output data bytes Db (value “1”), and outputs the result to the third multiplexer 254. The selection signal S3 given to the third multiplexer 254 is controlled so as to select and output the output signal from the second adder 272 except for the beginning of the address calculation process (start address SA output in step S10). Set by the unit 100. Therefore, the third multiplexer 254 outputs a value obtained by adding the current address Adr (now the start address SA) and the number of output data bytes Db (value “1”) to the address register 280. As a result, the current address Adr which is the value of the address register 280 is replaced with (current address Adr + output data byte number Db) (step S60). Here, the current address Adr is (start address SA + 1) bytes.

  The data length counter 230 subtracts the output data byte number Db from the remaining data length DL-c (step S70). Here, the remaining data length DL-c is 2 bytes by subtracting 1 byte from 3 bytes. Since the element loop rp0 is repeated until the remaining data length DL-c becomes 0, the current address Adr is output again (step S50). That is, in FIG. 6, the address of the data X12 at the position of the start address SA + 1 byte is designated. In step S60, the current address Adr is the start address SA + 2 bytes, and in step S70, the remaining data length DL-c is 1 byte. Since the remaining data length DL-c is not 0, the current address Adr is designated again (step S50). That is, in FIG. 6, the address of the data X13 at the position of the start address SA + 2 bytes is designated. In step S60, the current address Adr becomes the start address SA + 3 bytes (position El1 in FIG. 6), and the remaining data length DL-c becomes 0 bytes in step S70. Since the remaining data length DL-c has become 0, the process exits the element loop rp0 and proceeds to step S80.

  By the way, as described above, the data area corresponding to the data length DL addressed by the element loop rp0 is referred to as an “element”. In FIG. 6A, four elements E11 to E14 are shown. The element E12 includes data X21, data X22, and data X23, and the data length of the element E12 is DL. That is, the element E12 has the same configuration as the element E11. The elements E13 and E14 have the same configuration as the element E11. The start addresses of the elements are the addresses Es1, Es2, Es3, and Es4, respectively, and the end addresses are the addresses El1, El2, El3, and El4, respectively. The inter-element offset Eoffset is the length of the gap between elements, and is 3 bytes in the example of FIG. The number of elements En is the number of elements included in the first hierarchy, and the number of elements En is 4 in the example of FIG.

  When the remaining data length DL-c becomes 0, the second decoder 262 in FIG. 2 sends a signal to the element number counter 231 to decrease the element number En by one. In response to the signal, the element number counter 231 subtracts 1 from the remaining element number En-c (step S80). By step S80, the number of remaining elements En-c is 3 here. Next, the address calculation circuit performs an element offset Eoffset setting process (step S90).

  FIG. 5 is a flowchart showing an element offset Eoffset setting process. When the number of remaining elements En-c is not 0 (step S91: NO), the current address Adr is replaced with (current address Adr + element offset Eoffset) (step S92). In the example of FIG. 6A, the number of elements En = 3 and the current address Adr is the address El1, so that in step S92, the current address Adr adds 3 bytes of the element offset Eoffset to the address El1, Address Es2.

  The address arithmetic circuit in FIG. 2 executes the process of step S92 as follows. Since the remaining data length DL-c is currently “0”, the first decoder 260 outputs the output data byte number Db as “0”. Therefore, the second multiplexer 252 outputs the number of output data bytes Db (value “0”). Note that the selection signal S1 may be set so that the control unit 100 outputs “0” instead of the output data byte count Db. Also in this case, “0” is output from the second multiplexer 252. On the other hand, when the remaining data length DL-c is 0 and the remaining element number En-c is not 0, the second decoder 262 outputs a selection signal S2 that causes the first multiplexer 250 to output the element offset Eoffset. Generate. In response to the selection signal S2, the first multiplexer 250 outputs the element offset Eoffset. The first adder 270 adds the element offset Eoffset and “0”, and outputs the element offset Eoffset to the second adder 272. The second adder 272 adds the current address Adr and the element offset Eoffset, and outputs the result to the third multiplexer 254. The third multiplexer 254 outputs (current address Adr + element offset Eoffset) to the address register 280 in accordance with the selection signal S3. As described above, the current address Adr is replaced with (current address Adr + element offset Eoffset) (step S92).

  Returning to FIG. The unit loop rp1 is repeated until the remaining element number En-c becomes “0”. In the example of FIG. 6A, since the current remaining element count En-c is “3”, the unit loop rp1 is executed again. That is, the remaining data length DL-c is returned to the initial value DL (step S40), and the element loop rp0 is executed. The element loop rp0 outputs the address of the element E12 as in the case of the element E11 in FIG. 6A, the current address Adr becomes the address El2, and the remaining data length DL-c becomes “0”. When the unit loop rp1 is repeatedly executed in this way and the remaining element count En-c becomes “0”, the current address Adr becomes the address El4. According to the element offset Eoffset setting process of FIG. 5, when the number of remaining elements En-c is “0” (step S91: YES), the current address Adr remains unchanged, so the current address Adr remains the address El4. Yes (step S90). Since the number of remaining elements En-c becomes “0”, the process exits the unit loop rp1 and proceeds to the process of step S100.

  The data area (including the inter-element offset Eoffset) that can be addressed by the unit loop rp1 is called a “unit” as described above. In the example of FIG. 6A, the address Es1 to the address El4 is one unit. FIG. 6B shows that the elements E11 to E14 constitute the first unit U11. FIG. 6B shows two units U12 and U13 in addition to the unit U11. The units U12 and U13 have the same configuration as the unit U11. The first addresses of each unit are addresses Us1, Us2, and Us3, respectively, and the last addresses are addresses Ul1, Ul2, and Ul3, respectively. The inter-unit offset Uoffset is the length of the gap between the units, and is 4 bytes in the example of FIG. 6B. The unit number Un is the number of units included in the second layer, and the unit number Un is 3 in the example of FIG.

  When the remaining element number En-c becomes 0, the second decoder 262 in FIG. 2 sends a signal to the unit number counter 232 to decrease the remaining unit number Un-c by one. In response to the signal, the unit number counter 232 subtracts 1 from the remaining unit number Un-c (step S100). In the example of FIG. 6, the remaining unit number Un-c is 2. Next, an inter-unit offset Uoffset setting process is performed (step S110). The inter-unit offset Uoffset setting process is a process in which En is changed to Un and Eoffset is changed to Uoffset in the inter-element offset Eoffset setting process in FIG.

  In the inter-unit offset Uoffset setting process, when the remaining unit number Un-c is not 0, the current address Adr is replaced with (current address Adr + inter-unit offset Uoffset). In the example of FIG. 6B, since the remaining unit number Un-c is 2 and the current address Adr is the address Ul1 (matches the address El4), the current address Adr is changed to the address by the unit offset Uoffset setting process. It becomes Us2.

  The address arithmetic circuit in FIG. 2 replaces the current address Adr with (current address Adr + unit offset Uoffset) in the same manner as in the process of step S92. At this time, the second decoder 262 determines that the remaining data length DL-c is “0”, the remaining element number En-c is “0”, and the remaining unit number Un-c is not “0”. A selection signal S2 is generated that causes the first multiplexer 250 to output the inter-unit offset Uoffset. As a result, the first multiplexer 250 outputs the inter-unit offset Uoffset.

  Returning to FIG. The set loop rp2 is repeated until the remaining unit number Un-c becomes “0”. In the inter-unit offset Uoffset setting process (step S110), when the remaining unit number Un-c is “0”, the current address Adr is not advanced, so the current address Adr remains the address Ul3. When the number of units Un reaches “0”, the set loop rp2 is exited and the process proceeds to step S120.

  The memory area addressed by the above set loop rp2 is called “set” as described above. In the example of FIG. 6B, the address Us1 to the address Ul3 is one set. FIG. 6C shows that the units U11 to U13 constitute the first set S11. FIG. 6C shows a set S12 in addition to the set S11. The set S12 has the same configuration as the set S11. The addresses at the beginning of each set are addresses Ss1 and Ss2, respectively, and the addresses at the end are addresses S11 and S12, respectively. The inter-set offset Soffset is the length of the gap between sets, and is 4 bytes in the example of FIG. The set number Sn is the number of sets included in the third hierarchy, and the set number Sn is 2 in the example of FIG.

  When the remaining unit number Un-c becomes 0, the second decoder 262 in FIG. 2 sends a signal to the set number counter 233 to decrease the remaining set number Sn-c by one. In response to the signal, the set number counter 233 subtracts 1 from the remaining set number Sn-c (step S120). In the example of FIG. 6, the remaining set number Sn-c is 1. Next, a set offset offset setting process is performed (step S130). Since the inter-set offset offset setting process is a process in which En is changed to Sn and Eoffset is changed to offset in the inter-element offset Eoffset setting process of FIG. 5, the illustration is omitted.

  In the inter-set offset offset setting processing, when the remaining set number Sn-c is not 0, the current address Adr is replaced with (current address Adr + inter-set offset Soffset). In the example of FIG. 6C, since the remaining set number Sn-c is 1 and the current address Adr is the address Sl1 (matches the address Ul3), the current address Adr is set to the address Ss2 by the inter-set offset Offset setting process. It becomes.

  The address arithmetic circuit in FIG. 2 replaces the current address Adr with (current address Adr + inter-set offset Soffset) in the same manner as in step S92. In the second decoder 262, the remaining data length DL-c is 0, the remaining element number En-c is 0, the remaining unit number Un-c is 0, and the remaining set number Sn-c is not 0. Generates a selection signal S2 that causes the first multiplexer 250 to output an inter-set offset Soffset. Accordingly, the first multiplexer 250 outputs the inter-set offset Soffset.

  Returning to FIG. The set group loop rp3 is repeated until the remaining set number Sn-c becomes “0”. When the set number Sn becomes “0”, the process exits the set group loop rp3. The memory area addressed by the above set group loop rp3 is called a “set group” as described above. In the example of FIG. 6B, the addresses Ss1 to S12 are one set group.

  Examples of address calculation that can be executed by setting various parameters in the address calculation processing will be described with reference to FIGS. 7 to 11, one square corresponds to one byte.

FIG. 7 is an explanatory diagram showing the source region 21 and the destination region 22. FIG. 7A shows the source region 21 and FIG. 7B shows the destination region 22. The image data in the source region 21 is stored in order for each pixel in units of (X (auxiliary region), R (red), G (green), B (blue)). Various parameters are set for the data in the source area 21 as follows, and the address calculation processing shown in FIGS. 4 and 5 is executed.
-Data length DL = 1 byte;
-Number of elements En = 8;
-Number of units Un = 3;
-Number of sets Sn = 1;
Inter-element offset Eoffset = 3 bytes;
Inter-unit offset Uoffset = -28 bytes;
• Offset between sets Offset = 0 bytes;

  When the parameters are set in this way, in the address calculation process performed by the source address calculation circuit 200, first, the address of the data R0 corresponding to the data length DL (1 byte) from the start address SA (hereinafter referred to as address R0). Next, the next address R1 is designated with an interval corresponding to the element offset Eoffset (3 bytes). Then, the next address R2 is specified with an interval corresponding to the element offset Eoffset (3 bytes). Such address designation is repeated for the number of elements En (eight), and the address is designated up to address R7. This means that one unit of address can be designated by the addresses R0 to R7.

  Next, an address G0 is designated with an interval corresponding to the unit offset Uoffset (−28 bytes). Next, the next address G1 is designated with an interval corresponding to the element offset Eoffset (3 bytes). Such address designation is repeated for the number of elements En (eight) to designate up to the address G7. This means that the address of the second unit can be designated by the addresses G0 to G7.

  Further, the address B0 is specified with an interval corresponding to the offset between units Uoffset (−28 bytes). Next, the next address B1 is designated with an interval corresponding to the element offset Eoffset (3 bytes). Such address designation is repeated for the number of elements En (eight) to designate up to address B7. This means that the address of the third unit can be designated by the addresses B0 to B7.

  Since the number of units Un is 3, unit addressing ends here. Since there is one set for the number of units Un (three), there is one set for addresses R0 to R7, G0 to G7, and B0 to B7. Therefore, one set of addresses can be specified. Since the set number Sn is 1, the address calculation process ends here.

  As described above, when address calculation processing is executed by designating appropriate parameters for the image data as shown in FIG. 7A, addresses R0 to R7, G0 to G7, and B0 to B7 can be obtained. Since this address calculation result is addressed for each component of R (red), G (green), and B (blue), it is useful when performing processing for each component in image processing.

When the source address arithmetic circuit 200 performs the address arithmetic processing as shown in FIG. 7A, the destination address arithmetic circuit 300 sets various parameters as described below and executes the address arithmetic processing to transfer data. The data array of the subsequent destination area 22 is as shown in FIG.
-Data length DL = 1 byte;
-Number of elements En = 8;
-Number of units Un = 3;
-Number of sets Sn = 1;
• Offset between elements Eoffset = 0 bytes;
-Unit offset Uoffset = 0 bytes;
• Offset between sets Offset = 0 bytes;

  Since the data length DL is 1 byte, 1-byte data is one element. Since the inter-element offset Eoffset is 0 byte, the interval between the element R0 and the next element R1 in FIG. 7B is 0 byte. Since the number of elements En is 8, eight elements R0 to R7 constitute one unit. Since the inter-unit offset Uoffset is 0 byte, the interval between the units in FIG. 7B is 0 byte. Since the number of units Un is 3, three units R0 to R7, G0 to G7, and B0 to B7 constitute one set. Since the set number Sn is 1, as a result, the data array of the destination area 22 is as shown in FIG.

  On the contrary, FIG. 7B can be used as the source region 21 and FIG. 7A can be used as the destination region.

FIG. 8 is an explanatory diagram showing another destination area 22. FIG. 8 shows that when the source address arithmetic circuit 200 performs the address arithmetic processing as shown in FIG. 7A, the destination address arithmetic circuit 300 sets the various parameters as follows and executes the address arithmetic processing. This is a data array of the destination area 22 after the data transfer in the case of.
-Data length DL = 24 bytes;
-The number of elements En = 1;
-Number of units Un = 1;
-Number of sets Sn = 1;
• Offset between elements Eoffset = 0 bytes;
-Unit offset Uoffset = 0 bytes;
• Offset between sets Offset = 0 bytes;

  As described above, even if the parameter setting values are different, the data array resulting from the address calculation process may be the same.

FIG. 9 is an explanatory diagram showing still another destination area 22. FIG. 9 shows that when the source address arithmetic circuit 200 performs the address arithmetic processing as shown in FIG. 7A, the destination address arithmetic circuit 300 sets various parameters as follows and executes the address arithmetic processing. This is a data array of the destination area 22 after the data transfer in the case of.
-Data length DL = 4 bytes;
-Number of elements En = 2;
-Number of units Un = 3;
-Number of sets Sn = 1;
-Offset between elements Eoffset = 1 byte;
-Unit offset Uoffset = 2 bytes;
• Offset between sets Offset = 0 bytes;

  Since the data length DL is 4 bytes, (R0 to R3), (R4 to R7), (G0 to G3), (B0 to B3), etc. are each one element. Since the element offset Eoffset is 1 byte, the interval between the elements R0 to R3 and the elements R4 to R7 in FIG. 9 is 1 byte. The offset between other elements is also 1 byte. Since the number of elements En is 2, (R0 to R7), (G0 to G7), etc. each constitute one unit. Since the inter-unit offset Uoffset is 2 bytes, the interval between the units R0 to R7 and the units G0 to G7 is 2 bytes in FIG. The interval between the units G0 to G7 and the units B0 to B7 is also 2 bytes. Since the number of units Un is 3, three units R0 to R7, G0 to G7, and B0 to B7 constitute one set. Since the set number Sn is 1, the destination area 22 is as shown in FIG.

Thus, in the source address arithmetic circuit 200 and the destination address arithmetic circuit 300, the data length DL, the element number En, the unit number Un, the set number, the inter-element offset Eoffset, and the inter-unit offset Uoffset,
At least one of the offsets between sets Soffset may be different from each other. As a result, the source address arithmetic circuit 200 and the destination address arithmetic circuit 300 can perform asymmetrically complicated address designation.

FIG. 10 is an explanatory diagram showing another destination area 22. In FIG. 10, more complicated addressing is realized than in FIGS. When the source address calculation circuit 200 performs the address calculation processing as shown in FIG. 7A, the data when the destination address calculation circuit 300 executes the address calculation processing by setting various parameters as follows: It is a data array of the destination area 22 after transfer.
-Data length DL = 2 bytes;
-Number of elements En = 2;
・ Number of units Un = 2;
・ Set number Sn = 2;
-Offset between elements Eoffset = 5 bytes;
-Unit offset Uoffset = -4 bytes;
-Inter-set offset Offset = 6 bytes;

  Since the data length DL is 2 bytes, R0 to R1 are one element. Since the element offset Eoffset is 5 bytes, the interval between the elements R0 to R1 and the next data R2 in FIG. 10 is 5 bytes. Next, since the data length DL is 2 bytes, R2 to R3 constitute one element. Since the number of elements En is 2, the two elements R0 to R3 constitute one unit. Since the inter-unit offset Uoffset is −4 bytes, the interval between the units R0 to R3 and the next data R4 in FIG. 10 is −4 bytes. Further, since the data length DL is 2 bytes, (R4 to R5), (R6 to R7), etc. are each 1 element, and the element offset Eoffset is 5 bytes, so the elements R4 to R5 and the elements R6 to R7 Is 5 bytes and the number of elements En is 2, so that R4 to R7 constitute one unit. Since the number of units Un is 2, two units R0 to R7 constitute one set. Since the inter-set offset Soffset is 6 bytes, the interval between the set R0 to R7 in FIG. 10 and the next data G0 is 6 bytes. Similarly, (G0 to G1), (G2 to G3), (G4 to G5), (G6 to G7), etc. are each one element, and (G0 to G3) and (G4 to G7) each constitute one unit. To do. Since the number of units Un is 2, G0 to G7 constitute one set. Since the set number Sn is 2, the destination area 22 is as shown in FIG.

The address calculation processing of this embodiment can be used in various ways. FIG. 11 is an explanatory diagram showing still another source region 21 and destination region 22. When a document such as that shown in FIG. 11C is read by image processing, data is normally read in the horizontal direction. FIG. 11A shows a state in which such data is stored in the source area 21. The source address arithmetic circuit 200 sets various parameters as shown in the following formulas (1.1) to (1.7), executes address arithmetic processing, and the destination address arithmetic circuit 300 When various parameters are set as shown in 2.1) to (2.7) and the address calculation process is executed, the data read in the direction indicated by the arrow in FIG. 11C is stored in the destination area 22. can do.
・ Data length DL = 3 bytes (1.1)
-Number of elements En = 3 (1.2)
-Unit number Un = 1 (1.3)
-Number of sets Sn = 1 (1.4)
-Offset between elements Eoffset = 57 bytes (1.5)
-Unit offset Uoffset = 0 bytes (1.6)
-Offset between sets Soffset = 0 bytes (1.7)
-Data length DL = 9 bytes (2.1)
-Number of elements En = 1 (2.2)
-Number of units Un = 1 (2.3)
-Number of sets Sn = 1 (2.4)
-Offset between elements Eoffset = 0 bytes (2.5)
-Unit offset Uoffset = 0 bytes (2.6)
-Offset between sets Offset = 0 bytes (2.7)

  As described above, in this embodiment, it is possible to execute a complicated address calculation for DMA transfer by performing an address calculation on a data block composed of three layers of elements, units, and sets.

Further, since complicated data transfer can be performed inside the DMAC 1000, the load on the CPU 10 can be reduced as a result. In the present embodiment, the CPU 10 can perform data transfer efficiently by once setting parameters for the DMAC 1000 and outputting a data transfer command.
Other examples:

(1) In the above embodiment, the case where the source area 21 and the destination area 22 exist in the same memory 20 has been described for data transfer during image processing. The DMA controller of the present invention is useful for data transfer during image processing, but the application is not limited thereto. For example, if 128 bits of data in the memory are to be continuously transmitted to the same port one bit at a time, in the source address calculation circuit 200, the data length DL is 1 bit, the number of elements is 128, the number of units is 1, the number of sets Is set to 1, the offset between elements Eoffset is set to 0, the offset between units Uoffset is set to 0, and the offset between sets Soffset is set to 0. In the destination address calculation circuit 300, the data length DL is set to 1 bit, the number of elements is set to 128, and the number of units is set to 1. If the number of sets is set to 1, the element offset Eoffset is set to -1 bit, the unit offset Uoffset is set to 0, and the offset between sets Soffset is set to 0, 128-bit data in the memory is continuously transmitted to the same port. Do Theft is possible.

(2) In the above embodiment, the counters 230 to 233 are subtraction counters. Instead of this, an addition counter and a comparator for comparing the addition result with each set value DL, En, Un, Sn are provided. You may make it provide. That is, generally, a counter circuit having a function indicating that the cumulative value has reached the set value can be used according to the relationship between the cumulative value to be counted and the set value.

(3) In the above embodiment, the counters 230 to 233, the first decoder 260, the second decoder 262, the first multiplexer 250, the second multiplexer 252, the third multiplexer 254, The one adder 270, the second adder 272, and the address register 280 constitute the address calculation execution unit of the present invention. However, the present invention is not limited to this, and the address calculation execution unit has various circuit configurations. Is feasible.

(4) In the above embodiment, the DMAC 1000 has been described as performing an address operation on a three-layer data block. However, the number of layers is not limited to three and can be variously set. For example, there may be two layers, or four or more layers. In that case, an offset register and a counter may be provided according to the number of layers.

  As described above, the DMA controller according to the present invention has been described based on the embodiments. However, the above-described embodiments of the present invention are intended to facilitate understanding of the present invention and are not intended to limit the present invention. For example, the present invention can be implemented as a single address arithmetic unit as shown in FIG. The present invention can be changed and improved without departing from the spirit and scope of the claims, and it is needless to say that the present invention includes equivalents thereof.

2 is an explanatory diagram showing a computer system including a DMA controller 1000. FIG. 2 is a block diagram showing an internal configuration of a source address arithmetic circuit 200. FIG. Explanatory drawing which shows the meaning of parameters SA, Eoffset, Uoffset, Soffset set to registers 210, 221 to 223 and parameters DL, En, Un, Sn set to counters 230-233. The flowchart which shows an address calculation process. The flowchart which shows the element offset Eoffset setting process. Explanatory drawing which shows typically the memory area | region used as transfer object. Explanatory drawing which shows the source region 21 and the destination area | region 22. FIG. Explanatory drawing which shows the other destination area | region 22. FIG. Furthermore, the explanatory view which shows the other destination area 22. FIG. Explanatory drawing which shows the other destination area | region 22. FIG. Further, another explanatory view showing a source region 21 and a destination region 22. FIG. Explanatory drawing which shows the address calculation by the conventional DMA controller.

Explanation of symbols

20 ... Memory 21, 21A ... Source area 22, 22A ... Destination area 100 ... Control unit 200 ... Source address arithmetic circuit 210 ... Start address register 221 ... Inter-element offset Register 222 ... Inter-unit offset register 223 ... Inter-set offset register 230 ... Data length counter 231 ... Element number counter 232 ... Unit number counter 233 ... Set number counter 250 ... First 1 multiplexer 252 ... second multiplexer 254 ... third multiplexer 260 ... first decoder 262 ... second decoder 270 ... first adder 272 ... second Adder 280 ... Address register 300 ... Destination address arithmetic circuit 400 ... Bus interface 500 ... Buffer unit 520 ... So Buffer 530 ... Destination buffer 1100 ... Bus Adr ... Current address Db ... Number of transfer data bytes DL ... Data length DL-c ... Remaining data length En ... Number of elements En- c ... Number of remaining elements Eoffset ... Element offset Un ... Number of units Un-c ... Number of remaining units Uoffset ... Inter-unit offset Sn ... Number of sets Sn-c ... Remaining set Number Soffset ... Offset between sets L1DB ... First layer data block L2DB ... Second layer data block L3DB ... Third layer data block S1-S3 ... Selection signal

Claims (4)

A DMA controller for transferring data in a source area to a destination area,
A source address calculation unit for calculating an address of data in the source region;
A destination address calculation unit for calculating an address of the destination area;
With
Each of the source address calculation unit and the destination address calculation unit can calculate an address related to an N-layer data block having an N-dimensional (N is an integer of 2 or more) hierarchical structure,
The N-layer data block is configured as a set of data elements having a specified data length DL in a memory area after a specified start address,
When the data element is defined as a data block in the 0th layer, a data block in the i-th layer (i is an integer from 1 to N) is designated as a data block in the (i-1) -th layer. The offset L (i) -offset has a configuration in which the designated number of blocks L (i) -n is repeatedly arranged,
Each of the source address calculator and the destination address calculator is
A start address storage unit for storing the start address;
A data length storage unit for storing the data length DL;
An offset storage unit for storing N offsets L (i) -offset (i is an integer from 1 to N) for data blocks from the first layer to the Nth layer;
A block number storage unit for storing N block numbers L (i) -n (i is an integer from 1 to N) for data blocks from the first layer to the Nth layer;
Based on the start address, the data length DL, the N offsets L (i) -offset, and the N block numbers L (i) -n, the source region or the destination region An address calculation execution unit for performing an address calculation for the N-layer data block;
Equipped with a,
The destination address calculation unit, Ru der settable to a value different from that of the offset L (i) -offset offset L (i) -offset in the data blocks of at least the i-th layer in the source address calculation unit, DMA controller. The DMA controller according to claim 1, comprising:
The source address calculation unit and the destination address calculation unit include the start address, the data length DL, the N offsets L (i) -offset, and the N block numbers L (i) -n. Can be set independently of each other,
DMA controller. The DMA controller according to claim 1 or 2, wherein
The address calculation execution unit
A signal indicating that the transfer of the data element as the data block of the 0th layer is completed once based on the relationship between the accumulated value of the amount of data transferred in one data transfer and the data length DL A data length counter to
(I-1) Transfer of the i-th layer data block from the relationship between the number of transfers of the data block in the (i-1) th layer (i is an integer from 1 to N) and the number of blocks L (i) -n N number of i-th layer counters that output a signal indicating that is completed once,
An offset selection unit that selects and outputs the offset L (i) -offset of the i-th layer each time the transfer of the data block of the (i-1) -th layer is completed once;
The amount of data transferred in the one-time data transfer is sequentially added to the start address, and when the offset L (i) -offset of the i-th layer is output from the offset selection unit, Furthermore, by adding the offset L (i) -offset of the i-th layer, an adder that sequentially generates addresses of data to be transferred,
A DMA controller comprising: A DMA controller according to claim 3, wherein
A DMA controller, wherein the amount of data transferred in one data transfer is variable.

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