JP2005341565A - Dynamic programmable logic array containing enable device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dynamic programmable logic array containing enable devices. <P>SOLUTION: The DPLA (Dynamic Programmable Logic Array) uses enable devices, each of which outputs the result of an OR operation to each output line eliminating the clock signal within the OR plane. The clock signal is used only in an AND plane for precharging the AND line. Such a DPLA appropriately operates even at high frequencies, without delay between the two clock signals of the AND plane and the OR plane. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to general dynamically programmable logic arrays (DPLA's), and more particularly, to a DPLA including an enable device that does not use a clock signal on an OR-plane.

  PLA (Programmable Logic Array) is generally known as a function that flexibly provides the sum of products of input signals (sum of products). PLA generally includes an AND plane and an OR plane to provide a logical sum. A DPLA (Dynamic Programmable Logic Array) includes a clock signal for control timing of DPLA operation.

  FIG. 1 shows a conventional DPLA 100 that uses a first clock signal CLK1 for an AND plane and a second clock signal CLK2 for an OR plane. The AND plane is composed of first and second logical product lines 102 and 104 that generate logical products f1 * and f2 *, respectively. The four inputs a *, b *, c, d * are applied to the four input lines 106 in FIG. (Here, “*” indicates a commonly used complement.)

CLK1, the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are connected to each other, and each transistor is connected to the high and low voltages V _DD and V _SS, and the first AND line 102 is charged / discharged according to the logic state of CLK1. It is CLK1 is connected to the gates of the second PMOS transistor MP2 and the second NMOS transistor MN2, each transistor is connected to the high and low voltages V _DD and V _SS, and the second AND line 104 is charged according to the logic state of CLK1. / Discharged.

If CLK1 is in a logic low state (ie, “0”) for the precharge time, the AND lines 102, 104 are each precharged to a logic high state (ie, “1”). By connecting the NMOS transistors MN5, MN6, MN7, and MN8 to the AND plane of FIG. 1, if CLK1 is in a logic high state during the evaluation time, each of f1 * and f2 * on the AND lines 102 and 104 is displayed. The logic state depends on the logic states of the inputs a *, b *, c, d * as follows. (Here, “x” means an AND operation, and “+” indicates an OR operation.)
f1 * = axb
f2 * = c * xd

1 is connected to the gates of the third NMOS transistor MN3, the third PMOS transistor MP3, the fourth NMOS transistor MN4, and the fourth PMOS transistor NP4. PMOS transistor MP3, MP4 is connected to the _{V DD,} NMOS transistor MN3, MN4 is connected to the _{V SS.} If CLK2 is in a logic low state for the precharge time, the pre-output line 108 has a signal F * generated by being precharged to a logic high state. The output line 110 outputs a signal F through an inverter 112 connected to the pre-output line 108.

If the CLK2 is in a logic high state during the evaluation time due to the connection of the NMOS transistors MN9 and MN10 on the OR plane in FIG. 1, the logic state of F is as follows: f1 * and f2 * It depends on the logical states of a *, b *, c, d *.
F * = f1xf2
F = f1 * + f2 * = axb + c * xd

  Therefore, the output line 110 becomes an OR operation value of the logical products f1 * and f2 *.

  2 shows a DPLA (Dynamic Programmable Logic Array) 150, and FIG. 3 shows a timing diagram when the DPLA 150 of FIG. 2 described in Patent Document 1 operates. The AND plane of the DPLA 150 generates a logical product on the logical product line 1011 from the inputs A, A *, B, and B * on the input line 1010. The OR plane of DPLA 150 generates outputs Y1 and Y2 on output line 1012.

2 and 3, DPLA 150 includes a first clock signal φ1 for the AND plane and a second clock signal φ2 for the OR plane. The first group 152 including PMOS transistors and NMOS transistors is connected to V _DD and ground, and the clock signal φ1 is input to charge / discharge the AND line 1011 according to the logic state of φ1. . The second group 154 composed of PMOS transistors and NMOS transistors is connected to V _DD and ground, and the clock signal φ2 is input to charge / discharge the AND line 1012 according to the logic state of φ2. .

  The logical product value of the logical product line 1011 is determined by AND operation of each input set by connecting the NMOS transistor N1. The value of the output line 1012 is determined by OR operation of each logical product set by connecting the NMOS transistor N2.

  2 and 3, each AND line 1011 is precharged to a logic high state if φ1 is in a logic high state during the AND plane precharge time. If φ2 is in a logic high state during the OR plane precharge time, each of the output lines 1012 is precharged to a logic high state. If φ1 is transitioned to a logic low state during AND plane evaluation time, each of the AND lines 1011 becomes valid after the transmission delay time tp has elapsed since φ1 transitioned to a logic low state.

  According to FIG. 3, φ2 for the OR plane is Δt compared to φ1 for the AND plane to ensure that the logical product value is valid before the value is generated by an OR operation such as logical product on the output line 1012. Only delayed. Therefore, Δt must be greater than tp to ensure proper operation of the prior art DPLA 150.

  Conversely, DPLA 150 requires a high speed in order to operate with φ1 and φ2 having high frequencies. Since high frequencies of φ1 and φ2 are difficult to control Δt, it becomes more difficult to maintain the delay relationship of Δt> tp. Furthermore, it becomes difficult to control tp due to the transmission delay through the AND plane.

Due to the delay between φ1 and φ2, the DPLA 150 will not operate properly with high frequencies φ1 and φ2. Therefore, in order for DPLA to operate properly at a high frequency, there should be no delay between the two clock signals φ1 and φ2 of the AND plane and the OR plane.
US Patent 5,083,047

  An object of the present invention is to provide a DPLA that operates properly even at a high frequency without delay between two clock signals of an AND plane and an OR plane.

  According to an embodiment of the present invention, an apparatus for generating an output by performing a logical operation on a plurality of inputs has a first subset of the inputs as inputs when each of the inputs is in a first input logic state. An individual switching element for accepting and outputting a first output logic state, and when any input of a second subset is in the first input logic state, accepting the second subset of the inputs and the first output And an enable device for outputting a logic state.

  In accordance with one embodiment of the present invention, an apparatus for performing a logical operation on multiple inputs to generate an output, wherein each individual input is a first input logic state, each of the first subset of the inputs is An individual switching element that accepts as an input and sets the first pre-output on the first pre-output line as the first output logic state, and if any input of the second subset is the first input logic state, A first enable device that accepts a second subset of the inputs as an input and sets the first pre-output as the first output logic state; and if the individual input is a first input logic state, An individual switching element that accepts each of the three subsets as an input and sets the second pre-output on the second pre-output line as a first output logic state; A second enable device that accepts a fourth subset of the inputs as inputs and sets the second pre-output as the first output logic state if the first input logic state; and the first and second pre-outputs And a logic device that generates the output in combination.

  According to an embodiment of the present invention, an AND plane that provides multiple logical products to multiple logical product lines, and an OR plane of at least one output line that respectively provides an ORed result of each logical product. If each of the logical products is in the first input logical state, the dynamic PLA configured as follows accepts each of the first subset of the logical products as a logical product and sets the output as the first output logical state. An individual switching element and an individual that sets up the output as the first output logic state and accepts the second subset of the AND if any AND of the second subset is the first input logic state And an enabling device.

  According to one embodiment of the present invention, the dynamic PLA provides an AND plane that provides multiple ANDs to multiple AND lines, an OR plane of at least one output line including each output line, and the output. And an apparatus for providing an individual OR operation without an OR plane clock for line precharging.

  The DPLA (Dynamic Programmable Logic Array) of the present invention uses an enable device that removes the clock signal in the OR plane and provides an OR operation result to each output line. The clock signal is used only in the AND plane for AND line precharging. Such a DPLA operates properly even at a high frequency without delay between the two clock signals of the AND plane and the OR plane.

  According to FIG. 4, the DPLA 200 according to the present invention includes an AND plane 202 and an OR plane 204. The AND plane 202 is an input set IN1, IN1 *, IN2, and IN2 * on the input lines 208, 210, 212, and 214. A logical product Pm is generated.

Each pair of PMOS and NMOS transistors is connected to each AND line and high and low voltage sources V _DD and V _SS to charge / discharge each of the AND lines. The first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the first AND line 2061, the second PMOS transistor MP2 and the second NMOS transistor MN2 are connected to the second AND line 2062, and the mth PMOS transistor MPm and the mth NMOS transistor. MNm is connected to the mth AND line 206m.

PMOS transistors MP1, MP2, ..., each of MPm is connected to the high voltage _{V DD,} NMOS transistors MN1, MN2, ..., each of MNm is connected to the low voltage _{V SS.} The gates of the PMOS transistor and the NMOS transistor are connected to the clock signal CLK of the AND plane.

If CLK is a logic low state during the precharge time, each of the AND lines 2061, 2062,..., 206m is precharged to a logic high state. Conversely, if CLK goes to a logic high state during the evaluation time, the connection of NMOS transistor MN4 in AND plane 202 connects the AND lines 2061, 2062, through the set of inputs IN1, IN1 *, IN2, IN2 *, ..., a logical product value of 206 m is provided. An example of the time between evaluation times is as follows.
P1 = IN1 * xIN2 *
P2 = IN1
Pm = IN1 * xIN2

  The OR plane 204 includes a number of pre-output lines 2161, 2162,..., 216n that are each coupled to an inverter to produce outputs OUT1, OUT2,..., OUTn on output lines 2201, 2202,. In addition, each of the pre-output lines 2161, 2162,..., 216n is coupled to enable devices 2181, 2182,.

In addition, each of the pre-output lines 2161, 2162, ..., 216n is connected to at least one NMOS transistor set. Accordingly, the first NMOS transistor MN51 is connected to the first pre-output line 2161, the second NMOS transistor MN52 is connected to the second pre-output line 2162, and the n-th NMOS transistor MN5n is connected to the n-th pre-output line 216n. By connecting the NMOS transistors MN51, MN52,..., MN5n to the outputs OUT1, OUT2,..., OUTn, each output value is determined by OR operation of each logical product set as follows.
OUT1 = P1 + P2 + Pm
OUT2 = P1 + P2
OUT3 = P2 + Pm

  FIG. 5 shows an example of an enable device 218 for a pre-output line 216 that produces an output OUT on the output line 220. This can also be applied to one of the enable devices 2181, 2182,..., 218n for one of the pre-output lines 2161, 2162,.

According to FIG. 5, the output OUT on the output line 220 is obtained from the OR operation of each set of logical products Pi, Px, Py, Pz from the AND plane 202 as follows.
OUT = Pi + Px + Py + Pz

  One of the conjunctions (Pi in FIG. 5) for the enable device 218 of the present invention will be accepted from the concatenated enable device 218. The remaining logical products Px, Py, and Pz are each connected to one gate of the NMOS transistor MN5, the source of the NMOS transistor MN5 is connected to the ground, and the drain is connected to the pre-output line 216. The output line 220 is connected to the pre-output line 216 via the inverter 222. Further, each of the logical products Pi, Px, Py, and Pz corresponds to one of the logical products Pi, Px, Py, and Pz values different from the logical product lines 2061, 2062,. Become.

According to FIG. 5, enable device 218 includes a first inverter 302 that receives a Pi input and whose output is coupled to the input of NAND gate 304 and the gate of first PMOS transistor MP5. The source of the PMOS transistor MP5 is connected to the high voltage source V _DD and the drain is connected to the input of the NAND gate 304 and the source of the first NMOS transistor MN6.

The output of the NAND gate 304 is connected to the gate of the second PMOS transistor MP4 and the input of the second inverter 306. The source of the second PMOS transistor MP4 is connected to the high voltage source _VDD, and the drain is connected to the drains of the second NMOS transistor MN7 and the first NMOS transistor MN6. The output of the second inverter 306 is connected to the gate of the first NMOS transistor MN6. Pi is connected to the gate of the second NMOS transistor MN7.

  FIG. 6 is a chart 310 illustrating the logical state during operation of enable device 218 with output line 220 of FIG. In FIG. 6, “1” indicates a logic high state, and “0” indicates a logic low state. Further, the output signal OUT has an output logic state, and each of the logical products Pi, Px, Py, and Pz has an input logic state.

  According to FIGS. 4, 5, and 6, each of the products Pi, Px, Py, Pz has a high input logic state if the clock signal CLK is in a logic low state during the precharge time. The output signal OUT has a high output logic state during the precharge time.

  If the clock signal CLK is in a logic high state during the evaluation time, eight possible combinations of AND inputs Px, Py, Pz connected to the NMOS transistor MN5 are shown as shown in the table of FIG. . If any one of the logical products Px, Py, Pz is a high input logical state, the output signal OUT is not related to the input logical state of the logical product Pi input from the enable device 218, but is a high output logical state. become. If any one of the logical products Px, Py, and Pz is in the high input logic state, at least one of the NMOS transistors MN5 is turned on, regardless of the input logical state of the logical product Pi. Becomes a high output logic state.

  On the other hand, if all of the logical product inputs Px, Py, Pz connected to the NMOS transistor MN5 have a low input logical state, the output logical state of the output signal OUT is the input of the logical product Pi input from the enable device 218. Determined by logic state. If all of the AND inputs Px, Py, Pz have a low input logic state, the NMOS transistor MN5 is all turned off and the output logic state of the output signal OUT is determined by the value output from the enable device 218.

In this case, if Pi is in the high input logic state, the output signal OUT has a high output logic state, and the second NMOS transistor MN7 connected to the pre-output line 216 and the ground low voltage is turned on. Conversely, if Pi is in a low input logic state, the output signal OUT has a low output logic state, and the second PMOS transistor MP4 connected to the pre-output line 216 and the high voltage V _DD is turned on.

  Therefore, if all of the logical product inputs Px, Py, and Pz are in the low input logic state, the output logic state of the output signal OUT becomes the input logic state of Pi. As described above, if all of the logical product inputs Px, Py, and Pz are in the low input logic state, the output signal is determined by the input logic state of Pi determined by the logic gates 302, 304, and 306 controlling the switching devices MN4 and MN7. The output logic state of OUT is determined.

  4 and 5, enable devices 2181, 2182,..., 218n can be applied similarly to enable device 218 of FIG. Each output OUT1, OUT2,..., OUTn is obtained by OR operation of each set of logical products. For each enable device 2181, 2182,... 218n, the logical product corresponding to each set of logical products is connected to the enable device, and the remaining logical product is one of the set of NMOS transistors MN51, MN52,. Connected to one.

  In one embodiment of the present invention, the conjunction is different from the enable devices 2181, 2182,..., 218 n due to the minimization of each connection length. However, any AND of the set of AND concatenated with each enabler 2181, 2182, ..., 218n of the present invention is generally available.

  Furthermore, other applications for the enabling device of the present invention would be possible. FIG. 7 shows an opposing enable device 218a that is different from the enable device 218 of FIG. According to FIG. 7, the enable device 218 a further includes a third inverter 322 and an exclusive NOR gate 324. The input of the third inverter 322 is connected to the gate of the first PMOS transistor MP5, and the output is connected to the second NMOS transistor MN7.

  The input of the exclusive NOR gate 324 is connected to the output of the first inverter 302 and the output node 216, and the output is connected to the drain of the first NMOS transistor MN6. The operation state of the enable device 218a and the NMOS transistor MN5 of FIG. 7 is the same as the table 310 of FIG. 6 showing the operation state of the enable device 218 and the NMOS transistor MN5 of FIG.

FIGS. 8A and 8B show another embodiment of the present invention, which shows that the output signal OUT is generated using one enable device 218 in FIG. 8A and two enable devices 218b and 218c in FIG. 8B. . 8A and 8B produce an output signal OUT by OR operation of logical products Pi, Pv, Pw, Px, Py, and Pz as follows.
OUT = Pi + Pv + Pw + Px + Py + Pz

  In FIG. 8A, similarly to FIG. 5, one logical product Pi connected to the enable device 218 and the remaining logical products Pv, Pw, Px, Py, and Pz respectively connected to any one of the NMOS transistors MN5 are obtained. Have. Referring to FIG. 8B, the first enable device 352 is connected to the logical product Pi and the first pre-output line 354. Each of the two remaining outputs Pw and Px is connected to the gate of the NMOS transistor MN5 connected to the first pre-output line 354.

  Referring to FIG. 8B, the second enable device 356 receives another logical product Pv and is connected to the second pre-output line 358. Each of the two remaining outputs Py and Pz is connected to the gate of the NMOS transistor MN5 connected to the second pre-output line 358. The first and second pre-output lines 354 and 358 are input to the NAND gate 360, and the NAND gate 360 generates the output signal OUT on the output line 220.

The output signal OUT generated in the same manner in FIGS. 8A and 8B is generated by OR operation of logical products Pi, Pv, Pw, Px, Py, and Pz as follows.
OUT = Pi + Pv + Pw + Px + Py + Pz
Each of the enable devices 218, 352, 356 of FIGS. 8A and 8B operates in the same manner as the enable device of FIG. 5 or FIG.

  Thus, the DPLA 200 of the present invention has no clock signal in the OR plane 204 and includes the clock signal CLK only in the AND plane 202. Instead of the clock signal, each of the enable devices 2181, 2182,..., 218 n determines the output logic state of each of the outputs OUT 1, OUT 2,. A DPLA 200 without a clock signal in the OR plane 204 will now operate properly without the limitation that the clock signals of the AND plane 202 and the OR plane 204 are delayed. Therefore, the DPLA 200 of the present invention can operate properly even at a higher frequency than the prior art.

  The embodiments described above are not intended to limit the scope of the present invention. For example, the transistors in FIGS. 4, 5, 7, 8A, and 8B are examples of switching elements, and the present invention may be applied to other types of switching elements. Further, the logical product numbers for the output lines of the OR plane are merely described by way of examples.

  Furthermore, the OR operation provided by the enable device in FIGS. 5, 7, 8A, and 8B is different from the AND example of the DPLA 200 AND plane and other applications different from the DPLA 200 OR plane example. Other types of input could also be applied. The invention could also be generalized by concatenating at least one first subset of the inputs of the enable device with at least one second subset of the inputs of the NMOS transistor MN5.

  In the above, the configuration and operation of the circuit according to the present invention have been described according to the above description and the drawings. However, this is merely described by way of example, and various modifications can be made without departing from the technical idea and scope of the present invention. Of course, various changes and modifications are possible.

FIG. 3 is a circuit diagram showing an embodiment of a DPLA (Dynamic Programmable Logic Array) according to the prior art. It is a circuit diagram which shows the other example of DPLA by a prior art. FIG. 3 is a timing diagram showing signals in the operation of the DPLA of FIG. FIG. 5 is a circuit diagram illustrating a DPLA including an enable device instead of a clock signal on an OR plane according to an embodiment of the present invention. FIG. 5 is a circuit diagram illustrating an example of an enable device for an example of the output line of the DPLA of FIG. 4 according to an embodiment of the present invention. 6 is a chart showing logic states for signals in the circuit diagram of FIG. 5 according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating another example of an enable device for an example of the output line of the DPLA of FIG. 4 according to another embodiment of the present invention. FIG. 6 is a diagram illustrating the same configuration using two enable devices instead of one enable device for the same output line according to another embodiment of the present invention. FIG. 6 is a diagram illustrating the same configuration using two enable devices instead of one enable device for the same output line according to another embodiment of the present invention.

Claims (26)

In a device that performs a logical operation with multiple inputs and generates an output,
A discrete switching element that accepts a first subset of the inputs as inputs and outputs a first output logic state when each of the inputs is a first input logic state;
An enable device that accepts the second subset of inputs and outputs the first output logic state when any input of the second subset is in the first input logic state.   2. The apparatus of claim 1, wherein the enabling device determines a logic state of the output from the second subset of inputs if all inputs of the first subset are a second input logic state. The enable device including an enable circuit includes:
A first switching element that is turned on to connect the output line and the first voltage source and sets the output in a first output logic state;
A second switching element that is turned on to connect the output line and a second voltage source and sets the output to a second output logic state;
3. The apparatus of claim 2, comprising at least one logic gate that determines which of the first and second switch elements to turn on from the second subset of the inputs.   The apparatus of claim 1, wherein the first subset and the second subset are mutually exclusive of the inputs.   The apparatus of claim 4, wherein the first subset and the second subset combine all of the inputs.   6. The apparatus of claim 5, wherein the second subset is comprised of only one of the inputs, not part of the first subset.   The apparatus of claim 1, wherein each of the switching elements is a transistor including a gate coupled to the respective input.   The apparatus according to claim 1, wherein the logical operation is an OR operation.   The apparatus of claim 8, wherein the output is generated on an output line of a dynamic PLA.   The apparatus of claim 9, wherein each of the inputs is a respective logical product corresponding to a logical product line of the dynamic PLA.   The apparatus of claim 10, wherein each of the AND lines is precharged with the output in the first output logic state during a precharge time of an AND plane clock signal.   12. The apparatus of claim 11, wherein the enable device and the individual switching element determine a logic state of the output from the input during an evaluation time of the AND plane clock signal.   The apparatus of claim 9, wherein the output line is not precharged with an OR plane clock signal.   The apparatus of claim 9, wherein the output line is not coupled to any OR plane clock signal. In a device that performs a logical operation on a large number of inputs and generates an output,
If the individual input is a first input logic state, each of the first subsets of the inputs is accepted as an input and the first pre-output on the first pre-output line is set as the first output logic state. A switching element;
A first enable device that accepts a second subset of the inputs as an input if any input of a second subset is the first input logic state, and sets the first pre-output as the first output logic state; ,
If the individual input is a first input logic state, each of the third subset of inputs is accepted as an input and the second pre-output on the second pre-output line is set as the first output logic state. A switching element;
A second enabler that accepts a fourth subset of the inputs as an input if any input of the fourth subset is the first input logic state, and sets the second pre-output as the first output logic state; ,
An apparatus comprising: a logic device that generates the output in combination of the first and second pre-outputs.   The first enable device determines the logic state of the first pre-output from the second subset of inputs if all inputs of the first subset are in a second input logic state, and the second enable device is the third subset. 16. The apparatus of claim 15, wherein if all inputs of the second input logic state are the second input logic state, the logic state of the second pre-output is determined from the fourth subset of inputs. The first, second, third and fourth subsets are mutually exclusive sets of the inputs, the first, second, third and fourth subsets represent all of the inputs;
The second subset is not part of the first, third, and fourth subsets, but consists of only one of the inputs, and the fourth subset is the first, second, and third subsets. 16. The apparatus of claim 15, comprising only one of the inputs, not a part.   The apparatus of claim 15, wherein the output is generated on an output line of a dynamic PLA, and each of the inputs is a respective logical product corresponding to a logical product line of the dynamic PLA. An AND plane that provides multiple ANDs to multiple AND lines;
In a dynamic PLA consisting of an OR plane of at least one output line each providing an ORed result of each of the ANDs,
If each of the logical products is a first input logical state, an individual switching element that accepts each of the first subset of logical products as a logical product and sets the output as a first output logical state;
A separate enable device that accepts the second subset of the AND and sets the output as the first output logic state if any of the AND of the second subset is the first input logic state; A dynamic PLA characterized by containing.   The AND plane accepts a clock signal for providing the AND to the AND line during the clock signal evaluation time after the AND line is precharged during the clock signal precharge time. The dynamic PLA according to claim 19.   21. The dynamic PLA of claim 20, wherein the OR plane is provided for the logical OR operation during the evaluation without precharging the output line.   The individual enabling device determines the logical state of the output line from the second subset of logical products if all the logical products of the first subset are second input logical states. 19. Dynamic PLA according to 19. The individual enable device includes an enable circuit;
A first switching element that is turned on to connect the output line and a first voltage source to set the output of the first output logic state;
A second switching element that is turned on to connect the output line and a second voltage source to set the output of the second output logic state;
23. The dynamic DPA of claim 22 including at least one logic gate that determines that the first and second switching elements are turned on from the second subset of logical products.   The dynamic DPA of claim 19, wherein the individual enabler for each of the output lines accepts one of the different values of the AND.   25. The behavior of claim 24, wherein individually selected ones of the ANDs accepted by the individual enable devices are not coupled to the individual switching elements for each of the output lines. DPA. An AND plane that provides multiple ANDs to multiple AND lines;
An OR plane of at least one output line including each output line;
And a device for providing an OR operation of individual logical products without an OR plane clock for precharging the output line.

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