JP2005341410A - Solid-state imaging device and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device with a simple configuration, capable of easily supplying an output used for detection of sensitivity deviation between channels, without irradiating light at the solid-state imaging device, when a signal is read from the solid state imaging device via a plurality of channels. <P>SOLUTION: The solid-state imaging device comprises an imaging means (101), composed of a plurality of photoelectric conversion devices arranged in two-dimensional form and for converting incident light into an electrical signal, a plurality of common read means (103-122, CTN, and CTS) for outputting a signal from a plurality of pixels one by one, voltage supply means (VCAL1 and VCAL2) for selectively outputting a plurality of different fixed voltages to each of the plurality of common read-out means, and a supply control means (533) for controlling an output timing used by the voltage supply means. The supply control means directs the voltage supply means, to output the fixed voltages to the plurality of common read-out means, when the signal is not read from the plurality of pixels. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device and system having a pixel having a photoelectric conversion element that converts incident light into an electrical signal.

  Conventionally, as a solid-state image sensor, there is one using mainly a CCD or a MOS. In recent years, with the increase in the number of pixels due to miniaturization and high integration of solid-state imaging devices, improvement in the readout speed of signal output is desired. Therefore, the output system of the solid-state imaging device is made multi-channel, signals for a plurality of rows and / or a plurality of columns are read in parallel, and a plurality of signals obtained from the plurality of channels are rearranged on the system side to generate an image. As a result, there is an apparent increase in the signal reading speed from the solid-state imaging device.

  FIG. 6 is a diagram showing a configuration of a solid-state imaging device and an external processing system for reading out signals by a conventional multi-channel readout method, and FIG. 7 is a timing chart showing drive timings and output signals thereof. Hereinafter, a conventional technique will be described with reference to FIGS.

  In FIG. 6, reference numeral 1 denotes a pixel having a Bayer color filter, and the numbers in () next to R (red), G (green), and B (blue) represent the coordinates of each pixel. Here, for simplification of explanation, a case where pixels are arranged in 6 × 6 is shown, but in actuality, a very large number of pixels are two-dimensionally arranged in an array.

  Each pixel 101 is connected to the row selection lines L1 to L6 for each row, and the row selection lines L1 to L6 are sequentially set to High (hereinafter, “H”) by a row selection signal supplied from the vertical scanning circuit 102. Thus, a row from which charges are read is selected. Hereinafter, a method for reading from a selected pixel, a transmission path of pixel signals in a solid-state imaging device, a signal processing system outside the imaging device, and an image processing system in the driving example illustrated in FIG. 7 will be described. .

  After exposure of the solid-state imaging device for a predetermined time and before reading a signal from each pixel, φPCTR is first set to H to reset the capacitors CTN and CTS to the predetermined potential VCTR (t0). Next, the row selection signal φL1 supplied to the row selection line L1 becomes H, and the first row is selected (t1). At substantially the same timing as when the readout row is selected, prior to reading out the charges, the signals φPTN1 and φPTN2 are set to H, the MOSs 103 and 104 are turned on, and the noise component of the selected row is read out to the capacitor CTN. Next, the signals φPTS1 and φPTS2 are set to H to turn on the MOSs 105 and 106 (t2), and the photocharge accumulated in each pixel 101 in the selected row is read out to the capacitor CTS in a form superimposed on the noise component. As a result, the noise component of each pixel 101 and the pixel signal component superimposed on the noise component are aligned in the capacitors CTN and CTS, respectively.

  Next, each set of capacitors CTN and CTS is held by a column selection signal supplied from the first to fourth horizontal scanning circuits 107 to 110 via column selection lines H1 to H6, which is constituted by a shift register or the like. Are sequentially transferred to the differential amplifiers 111 to 114. The differential amplifiers 111 to 114 output a pixel signal from which the noise component has been removed by subtracting the noise component from the pixel signal component superimposed on the noise component.

  First, when the first and second horizontal scanning circuits 107 and 108 set φH1 and φH2 to H, the corresponding MOSs 115 to 118 are turned on, and the capacitors CTN and CTS are switched from G (1,1) and R (1,2). The read charges are transferred to the differential amplifiers 111 and 112 via the signal lines 119 and 120 (t3). The differential amplifier 111 removes the noise component from the pixel signal superimposed on the noise component, and outputs a pixel signal (indicated by the same reference symbol as the pixel. G (1,1)) (OUT1). Similarly, the differential amplifier 112 outputs the pixel signal R (1,2) (OUT2).

  Then, at the timing of t4, the third and fourth horizontal scanning circuits 109 and 110 set φH3 and φH4 to H, and charge read out from the capacitors CTN and CTS from G (1,3) and R (1,4), The signal is transferred to the differential amplifiers 113 and 114 via the signal lines 121 and 122, respectively. Then, the differential amplifier 113 removes the noise component from the photocharge superimposed on the noise component, and outputs the pixel signal G (1,3) (OUT3). Similarly, the differential amplifier 114 outputs the pixel signal R (1, 4) (OUT4). Hereinafter, this noise removal method is referred to as an SN noise removal method.

  In addition, after signal transfer from the pixels of each column to the signal lines 119 to 122, before the next signal is transferred, the signal lines 119 to 122 are reset to a predetermined potential VCHR in accordance with the inverted signals of φSH1 to φSH4. To do. In FIG. 6, only the reset circuit for the signal line 119 is shown for simplification of the drawing, but a similar reset circuit is also connected to the signal lines 120 to 122.

  In this manner, the image signals OUT1 to OUT4 output from the differential amplifiers 111 to 114 of the solid-state imaging device are amplified by the amplifiers 123 to 126 which are external processing systems, and the driving force is increased. After being converted into digital signals at .about.130, they are temporarily stored in the memory 131, and then synthesized into one image by the pixel processing unit 132. FIG.

  As described above, by multiplying the output channels and outputting the signals for a plurality of columns and / or a plurality of rows in parallel, the signal reading of the solid-state imaging device and the processing of the external image processing system are apparently accelerated.

  However, in the configuration of reading signals through a plurality of channels, the gain error of the differential amplifiers 111 to 114 in the solid-state imaging device and the external processing system amplifier 123 provided corresponding to each of the differential amplifiers 111 to 114 are provided. Since the sensitivity variation of each channel due to the gain error of ~ 126 and the gain error of the amplifiers in the A / D converters 127 to 130 becomes a problem, the LSB (least significant bit) value of the signal obtained from the A / D converters 127 to 130 To adjust the gain difference of each channel. This adjustment method will be briefly described. When the solid-state imaging device is incorporated in a camera or the like, the solid-state imaging device is irradiated with two types of light at different timings, and the output obtained from the same color pixel for each channel at each timing. And the sensitivity of each channel is obtained from the change in the signal output with respect to the change in the amount of light, and output from the A / D converters 127 to 130 so that there is no sensitivity deviation (gain error) between the channels based on the obtained sensitivity. The correction value for correcting the LSB value of the received signal is obtained and adjusted (see, for example, Patent Document 1).

JP-A-5-327205

  However, the sensitivity deviation correction method described above cannot accurately measure the sensitivity deviation (gain error) unless the solid-state imaging device is uniformly irradiated with light, and the correction amount can be obtained accurately. There wasn't. Furthermore, since the measurement of the sensitivity deviation and the process for obtaining the correction amount are performed before the solid-state imaging device and the external processing system are incorporated in a device such as a camera, after the incorporation, for example, the sensitivity of each channel due to a change in the ambient temperature. Since the correction value cannot be changed in accordance with the problem caused by the difference in the use environment of the camera, such as the temperature characteristic cannot be corrected, a high-quality image may not be formed depending on the use environment.

  The present invention has been made in view of the above problems, and is used to detect a sensitivity shift between channels without irradiating the solid-state imaging device with light when reading a signal from the solid-state imaging device via a plurality of channels. It is an object to make it possible to easily obtain an output from a solid-state imaging device with a simple configuration.

  Another object of the present invention is to correct the sensitivity shift between channels using the output obtained from the solid-state imaging device as described above.

  In order to achieve the above object, a solid-state imaging device according to the present invention sequentially captures imaging means formed by two-dimensionally arranging a plurality of photoelectric conversion elements that convert incident light into electrical signals, and signals from a plurality of pixels. A plurality of common reading means for outputting, a voltage supply means for selectively outputting a plurality of different fixed voltages to each of the plurality of common reading means, and a supply control means for controlling the output timing of the power supply means The supply control means causes the plurality of common readout means to output the fixed voltage during a time when signal readout from the plurality of pixels is not performed.

  A solid-state imaging system according to the present invention includes the solid-state imaging device described above, and a plurality of signal processing units that perform predetermined signal processing and are provided corresponding to the plurality of common readout units of the solid-state imaging device, respectively. And detecting means for detecting a difference between a plurality of signals processed by the plurality of signal processing means, and a correcting means for correcting so as to reduce the difference between the detected signals.

  According to the above configuration, when a signal is read from the solid-state imaging device via a plurality of channels, the output used for detecting the sensitivity shift between the channels is easily solidified without irradiating the solid-state imaging device with light. It can be obtained from an imaging device.

  Moreover, the sensitivity shift between channels can be corrected using the output obtained from the solid-state imaging device as described above.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

<Embodiment 1>
FIG. 1 is a schematic diagram illustrating a circuit configuration of a solid-state imaging device and an external processing system according to Embodiment 1 of the present invention. In FIG. 1, the same components as those in FIG. 6 described in the conventional example are denoted by the same reference numerals, and the description thereof is omitted.

  In the first embodiment, in addition to the configuration shown in FIG. 6, a configuration that supplies fixed voltages VCAL1 and VCAL2, and a differential amplifier of the solid-state imaging device as inputs of amplifiers 123 to 126 that are external processing systems of the solid-state imaging device Switches 511 to 514 that select one of the outputs OUT1 to OUT4 of 111 to 114 and the fixed voltages VCAL1 and VCAL2 and supply them to the amplifiers 123 to 126, and a calibration controller 533 that controls the switches 511 to 514 (in FIG. 1) Only the control line for the switch 511 is shown) in the solid-state imaging device. Here, the specific configuration of the portions of the fixed voltages VCAL1 and VCAL2 is provided with two terminals for electrical connection with the outside of the solid-state imaging device, and VCAL1 is input to one terminal, The terminal may be configured to input VCAL2. Further, a configuration may be adopted in which one terminal is provided, VCAL1 is input from the terminal, a step-down circuit is provided in the solid-state imaging device, and VCAL2 is generated. In FIG. 1, for simplification of the drawing, wiring is shown only for channel 1 (reading system for a signal output via signal line 119), and only switches 512-514 are provided for channels 2-4. As shown, the outputs from the differential amplifiers 112 to 114 are input to the “0” terminals of the switches 512 to 514, the fixed voltage VCAL 1 is input to the “1” terminal, and the fixed voltage VCAL 2 is input to the “2” terminal. Wired to do so. The switches 511 to 514 are collectively controlled by a calibration controller 533.

Here, the LSB value of the output signal of the A / D converters 127 to 130 obtained for each channel when the fixed voltage VCAL1 is input to the amplifiers 123 to 126, and the channel when the fixed voltage VCAL2 is input to the amplifiers 123 to 126. Based on the LSB value output of the output signals of the A / D converters 127 to 130 obtained every time, the gains of the amplifiers 123 to 126 and the A / D converters 127 to 127 are generally larger than those of the differential amplifiers 111 to 114. A gain of 130 is obtained. Taking channel 1 as an example, the gains of amplifier 123 and A / D converter 127 are obtained by the following equation.
Gain = (VOUT1 * −VOUT1) / (VCAL1−VCAL2)

In the above formula, VOUT1 * is obtained when VCAL1 is input to the amplifier 123, LSB value of the output signal of the A / D converter 127, VOUT1 is obtained when VCAL2 is input to the amplifier 123, A / D This is the LSB value of the output signal of the converter 127.
Similarly, gains of the amplifiers 124 to 126 and the A / D converters 128 to 130 are obtained, gain errors between channels are obtained, and the LSB values of the output signals from the A / D converters 127 to 130 are adjusted to obtain the gain. Make corrections.

  The gain correction method is not limited to the method of adjusting the LSB value, and any method may be used as long as the gain difference is corrected based on the obtained gain of each channel. For example, as shown in FIG. 2, the gain of the amplifier can be adjusted using a variable resistor. The gain correction operation in the configuration shown in FIG. 2 will be briefly described below.

  First, when the fixed voltages VCAL1 and VCAL2 are supplied to the external processing amplifiers 123 to 126, respectively, as described above, the output signals of the A / D converters 127 to 130 temporarily stored in the memory 131 are gain error detectors. Read to 133. A gain error detector 133 is provided in the differential amplifiers 111 to 114 so as to eliminate the gain difference between channels by calculating the gain by the above formula using the read output signal, calculating the gain error between channels and the correction amount. The gain is corrected by changing the resistance value of the variable resistor. In the example of FIG. 2, the variable resistors are provided in the differential amplifiers 111 to 114, but it goes without saying that the variable resistors may be provided in the external processing amplifiers 123 to 126.

  As described above, according to the configuration of the first embodiment, a configuration for irradiating the solid-state imaging device uniformly with light is not required, and a simple configuration for switching the fixed voltages VCAL1 and VCAL2 to be supplied to the amplifier of the external processing system. Thus, the gain of each channel can be easily obtained, and gain correction between channels can be performed using the obtained gain.

  Further, according to the above configuration, a gain error correction value can be obtained at an arbitrary timing. For example, when the solid-state imaging device is switched on, or when it is not taking a picture every predetermined time (because a temperature change is expected) from when the switch is turned on, or at the time of shipment from the factory, the gain is set at a desired timing It is possible to appropriately control so as to obtain the gain error correction value. Therefore, it is possible to correct the sensitivity deviation using a correction value suitable for the use environment.

  In the first embodiment, the configuration in which the fixed voltages VCAL1 and VCAL2 are supplied, the switches 511 to 514, and the calibration controller 533 are described as being provided in the solid-state imaging device, but at least a part of them is externally processed. Of course, it is also possible to configure as a system. However, when configured as an external processing system, the size becomes larger than when configured in the solid-state imaging device (on the semiconductor chip of the solid-state imaging device), and the mounting area is wasted. The configuration in the solid-state imaging device is advantageous in terms of miniaturization because it requires a much smaller area.

<Embodiment 2>
FIG. 3 is a schematic diagram illustrating a circuit configuration of the solid-state imaging device and the external processing system according to the second embodiment of the present invention. Also in FIG. 3, the same reference numerals are assigned to the same components as those in FIG. 6 described in the conventional example, and the description thereof is omitted.

  In the second embodiment, instead of the configuration for supplying the reset voltage VCHR shown in FIG. 6, the configuration for supplying the reset voltage VCHRN and the variable voltage VCHRS, and the DAC 233 for controlling the variable voltage VCHRS (giving a digital signal an analog type) And MOS switches 234 and 235 for controlling ON / OFF of supply of the reset voltage VCHRN and the variable voltage VCHRS. The MOS switches 234 and 235 are turned on when the signal φCAL supplied to the gate is H and turned off when the signal φCAL is L. Here, for simplification of the figure, only the channel 3 is shown, but actually, the same function is provided for each of the channels 1, 2, and 4 or the outputs of the MOS switches 234 and 235 are respectively set. Wiring is performed so as to be supplied to the signal lines 119, 120, and 122.

  Next, a method for acquiring the gain difference in the second embodiment will be described.

  First, the DAC 233 performs control so that the voltage VCHRS becomes substantially the same voltage as the reset voltage VCHR. Then, the signal φCAL is set to H, and the MOS switches 234 and 235 are opened. For example, in the case of channel 3, VCHRS is transferred from the capacitor CTN to the signal line 121S for transferring the photocharge (including noise component) from the capacitor CTS. The reset power supply VCHRN is supplied to the signal line 121N for transferring the noise component. In this state, the output signal of the A / D converter 129 is acquired in this state.

Thereafter, the voltage VCHRS is changed, and then the output signal of the A / D converter 129 is acquired. Thus, the gain of channel 3 is obtained from the LSB value of the output signal of the A / D converter 129 when a different voltage VCHRS is applied to the signal line 121S by the following equation. In the second embodiment, gains of the amplifiers in the differential amplifier 113, the amplifier 125, and the A / D converter 129 can be obtained collectively.
Gain = (VOUT3 * −VOUT3) / (VCHRS * −VCHRS)

However, in the above equation, VOUT3 * is the LSB value of the output signal of the A / D converter 127 obtained after the potential change of VCHRS, and VOUT3 is the output signal of the A / D converter 127 obtained before the potential change of VCHRS. LSB value. That is, it is necessary to change the voltage VCHRS to at least two kinds of potentials and acquire the LSB value.
Similarly, the gains of other channels are also obtained. A gain error between channels is obtained from the gains of channels 1 to 4 thus obtained, and the gain between channels is adjusted by adjusting the LSB value by adjusting the input range of the A / D converters 127 to 130, for example. Make corrections.

  As described above, according to the configuration of the second embodiment, a configuration for uniformly irradiating light to the solid-state imaging device is not required, and the potential of the variable voltage VCHRS is changed and supplied to the differential amplifier. With this configuration, the gain of each channel can be easily obtained, and gain correction between channels can be performed using the obtained gain.

  Further, according to the above configuration, a gain error correction value can be obtained at an arbitrary timing. For example, when the solid-state imaging device is switched on, or when it is not taking a picture every predetermined time (because a temperature change is expected) from when the switch is turned on, or at the time of shipment from the factory, the gain is set at a desired timing. It is possible to appropriately control so as to obtain the gain error correction value. Therefore, it is possible to correct the sensitivity deviation using a correction value suitable for the use environment.

  Of course, the configuration for supplying the variable voltage VCHRS and the DAC 233 for controlling the variable voltage VCHRS shown in FIG. 3 can be used instead of the configuration for supplying the fixed voltages VCAL1 and VCAL2 described in the first embodiment. It is.

<Embodiment 3>
FIG. 4 is a schematic diagram illustrating a circuit configuration of a solid-state imaging device and an external processing system according to Embodiment 3 of the present invention. Also in FIG. 4, the same components as those in FIG. 6 described in the conventional example are given the same reference numerals, and the description thereof is omitted.

  When the SN noise removal method is used for the readout circuit, in the configuration in which different voltages VCHRS and VCHRN are supplied to the signal lines 221S and 221N as in the second embodiment, the variable voltage VCHRS is reset as the reset voltage to reset the signal line 121R. Even if it is controlled to the same potential as VCHRN, the potential may not be exactly the same. In this case, an offset occurs in the signal output. As a result, a signal output offset occurs, and there is a drawback that the CMRR (same window removal rate) of the readout system is inferior.

  Further, on the system side, there is a disadvantage that the system becomes complicated, for example, it is necessary to provide the DAC 233 in order to change the variable voltage VCHRS.

  On the other hand, in the third embodiment, the reset voltage VCHR and the configuration for supplying the fixed voltage VCAL different from the reset voltage VCHR, the switch 311 for selecting either the reset voltage VCHR or the fixed voltage VCAL, and the switch 311 are controlled. Calibration controller 333 and MOS switches 312 and 313 for controlling ON / OFF of supply of reset voltage VCHR and fixed voltage VCAL are provided, and when switch 311 is connected to reset voltage VCHR, signal line 121N and signal When the reset voltage VCHR is supplied to both the lines 121S and the switch 311 is connected to the fixed voltage VCAL, the reset voltage VCHR is supplied to the signal line 121N, and the fixed voltage VCAL is supplied to the signal line 121S. ing. The MOS switches 312 and 313 are turned on when the signal φCAL supplied to the gate is H and turned off when the signal φCAL is L. Here, for simplification of the figure, only the channel 3 is shown, but actually, the same function is provided for each of the channels 1, 2, and 4, or the outputs of the MOS switches 312 and 313 are provided. The signal lines 119, 120, and 122 are wired so as to be supplied.

  Next, a method for acquiring the gain difference in the third embodiment will be described.

  First, the calibration controller 333 selects the reset voltage VCHR by the switch 311. Then, the signal φCAL is set to H and the MOS switches 312 and 313 are opened. For example, in the case of channel 3, the reset voltage φVCHR is supplied to both the signal lines 121N and 121S. In this state, the output signal of the A / D converter 129 is acquired in this state.

Next, the fixed voltage VCAL is selected by the switch 311 and the output signal from the A / D converter 129 is acquired with the signal φCAL set to H. From the LSB values of the two types of output signals thus obtained, the gain of channel 3 is obtained by the following equation. Also in the third embodiment, similarly to the second embodiment, the gains of the differential amplifier 113, the amplifier 125, and the amplifiers in the A / D converter 129 can be obtained collectively.
Gain = (VOUT3 * −VOUT3) / (VCAL−VCHR)

In the above equation, VOUT3 * is the LSB value of the output signal of the A / D converter 127 when VCAL is supplied to the signal line 121S, and VOUT3 is A when the VCHR is supplied to the signal line 121S. / D converter 127 is the LSB value of the output signal.
Similarly, the gains of other channels are also obtained. A gain error between channels is obtained from the gains of channels 1 to 4 thus obtained, and gain correction between channels is performed by adjusting the LSB value of the output signals of the A / D converters 127 to 130, for example. .

  As described above, according to the third embodiment, a configuration for uniformly irradiating light to the solid-state imaging device is not required, and it is simple to change the potential of the variable voltage VCHRS and supply it to the differential amplifier. With the configuration, the gain of each channel can be obtained easily and accurately, and gain correction between channels can be performed using the obtained gain.

  Further, when the pixel signal is actually read, the reset potentials of the signal lines 121S and 121N are reset to the potential VCHR from the same power source, so that no output offset occurs as in the second embodiment.

  Further, according to the above configuration, a gain error correction value can be obtained at an arbitrary timing. For example, when the solid-state imaging device is switched on, or when it is not taking a picture every predetermined time (because a temperature change is expected) from when the switch is turned on, or at the time of shipment from the factory, the gain is set at a desired timing. It is possible to appropriately control so as to obtain the gain error correction value. Therefore, it is possible to correct the sensitivity deviation using a correction value suitable for the use environment.

<Embodiment 4>
FIG. 5 is a schematic diagram illustrating a circuit configuration of the solid-state imaging device and the external processing system according to the fourth embodiment of the present invention. Also in FIG. 5, the same reference numerals are given to the same components as those in FIG. 6 described in the conventional example, and the description will be omitted.

  In the fourth embodiment, the reset potential VCTR and a configuration for supplying a fixed potential VCAL different from the reset potential VCTR, switches 411 and 412 for selecting either the reset potential VCTR or the fixed potential VCAL, and calibration for controlling the switch are used. Controller 433 and MOS switches 413 to 416 for controlling ON / OFF of supply of reset potential VCTR and fixed potential VCAL. When switches 411 and 412 are connected to reset potential VCTR, capacitors CTN and CTS are connected to capacitors CTN and CTS. Both are supplied with the reset potential VCTR, and when the switches 411 and 412 are connected to the fixed potential VCAL, the reset potential VCTR is supplied to the capacitor CTN and the fixed potential VCAL is supplied to the capacitor CTS. The MOS switches 413 to 416 are turned on when the signal φPCTR supplied to the gate is H and turned off when the signal φPCTR is L. In FIG. 5, two systems of reset potential VCTR, fixed potential VCAL, and φPCTR are shown, but it is of course possible to have a common configuration.

  Next, a method for acquiring the gain difference in the fourth embodiment will be described.

  First, in a state where φPTS and φPTN are set to L, the calibration controller 433 selects the reset potential VCTR by the switches 411 and 412. Then, the signal φPCTR is set to H, the MOS switches 413 to 416 are opened, and the reset potential VCTR is supplied to both the capacitors CTN and CTS. In this state, according to the driving method described in the conventional example, the first to fourth horizontal scanning circuits 107 to 110 sequentially read out the charges of the capacitors CTN and CTS via H1 to H4, and output the output signal of the A / D converter 129. get.

Next, the fixed potential VCAL is selected by the switches 411 and 412, and the reset potential VCTR is supplied to the capacitor CTN and the fixed potential VCAL is supplied to the capacitor CTS in a state where the signal φPCTR is set to H. In this state, according to the driving method described in the conventional example, the first to fourth horizontal scanning circuits 107 to 110 sequentially read out the charges of the capacitors CTN and CTS via H1 to H4, and output the output signal of the A / D converter 129. get. From the LSB values of the two types of output signals thus obtained, the gain of each channel is obtained by the following equation. Also in the fourth embodiment, similarly to the second and third embodiments, the gains of the differential amplifier 113, the amplifier 125, and the amplifiers in the A / D converter 129 can be obtained collectively.
Gain = (VOUT * −VOUT) / (VCAL−VCTR)

In the above equation, VOUT * is the LSB value of the output signal of the A / D converter 127 when the fixed potential VCAL is supplied to the capacitor CTS, and VOUT is the case where the reset potential VCTR is supplied to the capacitor CTS. This is the LSB value of the output signal of the A / D converter 127.
In this way, the gain of all channels is measured, the gain error between channels is obtained, and the input range of the A / D converters 127 to 130 is adjusted to adjust the LSB value, thereby correcting the gain between channels. .

  As described above, according to the fourth embodiment, it is possible to easily and accurately obtain the gain of each channel with a simple configuration without requiring a configuration for uniformly irradiating the solid-state imaging device with light. In addition, gain correction between channels can be performed using the obtained gain.

  Further, according to the above configuration, a gain error correction value can be obtained at an arbitrary timing. For example, when the solid-state imaging device is switched on, or when it is not taking a picture every predetermined time (because a temperature change is expected) from when the switch is turned on, or at the time of shipment from the factory, the gain is set at a desired timing. It is possible to appropriately control so as to obtain the gain error correction value. Therefore, it is possible to correct the sensitivity deviation using a correction value suitable for the use environment.

  In the fourth embodiment, the configuration for supplying the reset voltage VCTR and the fixed voltage VCAL different from the reset voltage VCTR is provided, but the configuration for supplying the variable voltage VCHRS described in the second embodiment instead of the fixed voltage VCAL. Of course, it is also possible to use the DAC 233 for controlling the variable voltage VCHRS.

  In the first to fourth embodiments, the first row and the fifth row are routed through the channel 1, the second row and the fifth row are routed through the channel 2, and so on. Although the output channel has been described, the allocation method of the read channel is not limited to this. For example, various allocation methods such as a configuration in which reading is performed by a different readout system for each of the upper and lower and / or left and right regions, and a configuration in which two rows are read are included. Can be considered. In any case, the present invention can be applied as long as the pixel signal is read out by a plurality of readout systems.

It is a schematic diagram which shows the circuit structure of the solid-state imaging device and external processing system in Embodiment 1 of this invention. It is a schematic diagram which shows another circuit structure of the solid-state imaging device and external processing system in Embodiment 1 of this invention. It is a schematic diagram which shows the circuit structure of the solid-state imaging device and external processing system in Embodiment 2 of this invention. It is a schematic diagram which shows the circuit structure of the solid-state imaging device and external processing system in Embodiment 3 of this invention. It is a schematic diagram which shows the circuit structure of the solid-state imaging device and external processing system in Embodiment 4 of this invention. It is a schematic diagram which shows the circuit structure of the conventional solid-state imaging device and an external processing system. It is a timing chart which shows the drive timing and output signal of the conventional imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Pixel 102 Vertical scanning circuit 107-110 Horizontal scanning circuit 111-114 Differential amplifier 119-122 Signal line 123-126 Amplifier 127-130 A / D converter 131 Memory 132 Image processing part 133 Gain error detector 233 DAC
333, 433, 533 Calibration controller

Claims (12)

Imaging means comprising a plurality of photoelectric conversion elements that convert incident light into electrical signals in a two-dimensional array;
A plurality of common readout means for sequentially outputting signals from a plurality of pixels;
Voltage supply means for selectively outputting a plurality of different fixed voltages to each of the plurality of common readout means;
Supply control means for controlling output timing by the power supply means,
The supply control unit causes the plurality of common readout units to output the fixed voltage during a time when signal readout from the plurality of pixels is not performed.   The solid-state imaging device according to claim 1, wherein the voltage supply unit includes a plurality of supply units that respectively supply a plurality of fixed voltages, and a selection unit that selects any one of the plurality of supply units. .   The solid-state imaging device according to claim 1, wherein the voltage supply unit includes a variable voltage supply unit that can supply a plurality of voltages, and a control unit that controls a supply voltage of the variable voltage supply unit. Each of the plurality of common readout means includes a first readout system that reads out an image signal obtained by converting incident light into an electrical signal by the imaging means, and a second readout system that reads out a noise signal.
The voltage supply means includes a fixed voltage supply means for supplying a fixed voltage for resetting the second read system, a variable voltage supply means capable of supplying a plurality of voltages to the first read system, The solid-state imaging device according to claim 1, further comprising a control unit that controls a supply voltage of the variable voltage supply unit. Each of the plurality of common readout means includes a first readout system that reads out an image signal obtained by converting incident light into an electrical signal by the imaging means, and a second readout system that reads out a noise signal.
The voltage supply means selectively selects a first fixed voltage for resetting the second readout system and a second fixed voltage different from the first fixed voltage to the first readout system. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is supplied. The first readout system has first holding means for temporarily holding an image signal obtained by converting incident light into an electrical signal, and the second readout system temporarily receives a noise signal. Second holding means for holding;
6. The solid-state imaging device according to claim 4, wherein the voltage supply unit supplies a voltage to the first and second holding units.   The solid-state imaging device according to claim 1, wherein the fixed voltage is generated in the solid-state imaging device.   The solid-state imaging device according to claim 1, wherein the fixed voltage is supplied from outside the solid-state imaging device. A solid-state imaging device according to any one of claims 1 to 8,
A plurality of signal processing means for performing predetermined signal processing provided respectively corresponding to the plurality of common readout means of the solid-state imaging device;
Detecting means for detecting a difference between a plurality of signals processed by the plurality of signal processing means;
A solid-state imaging system comprising: correction means for performing correction so as to reduce a difference between the detected signals.   10. The correction unit according to claim 9, wherein the correction unit calculates a correction value for correcting a difference between the signals, and corrects an image signal read from the imaging unit using the correction value. Solid-state imaging system. The plurality of common readout means includes amplification means capable of changing a gain,
The solid-state imaging system according to claim 9, wherein the correction unit outputs a correction signal for changing the gain so that the signal difference is eliminated, to the amplification unit. The plurality of signal processing means include amplification means capable of changing a gain,
The solid-state imaging system according to claim 9, wherein the correction unit outputs a correction signal for changing the gain so as to eliminate the signal difference to the amplification unit.

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