JP2005341368A - Bit modeling computing element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bit modeling computing element used in the case of configuring an image coder adopting the JPEG 2000 coding system or the like that can attain high speed bit modeling processing with a simple configuration. <P>SOLUTION: A path computing element 26 sequentially carries out determining processing of a path for each bit in a bit plane by using 4 bits of a stripe for a path determining processing unit. Then a context computing element 28 uses 4 bits of the stripe for context determining processing unit and carries out the context determining processing of each bit of the bit plane by using a symbol, path information and significant information obtained by the path computing element 26 to carry out the context determining processing of 4 bits of the stripe. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bit modeling arithmetic unit used when configuring an image encoding apparatus of the JPEG2000 encoding method. More specifically, the present invention relates to a technology for speeding up a bit modeling arithmetic unit.

  FIG. 14 is a schematic configuration diagram of a main part of an example of a conventional image encoding apparatus according to the JPEG2000 encoding method. In FIG. 14, 10 is a wavelet transformer, 11 is an entropy encoder, and 12 is a stream generator.

  The wavelet converter 10 performs wavelet conversion on digitized input image data. The entropy encoder 11 inputs the wavelet coefficient output from the wavelet converter 10 and performs entropy encoding. The stream generator 12 receives encoded data output from the entropy encoder 11 and generates a bit stream of compressed image data.

  In the entropy encoder 11, reference numeral 13 denotes a bit modeling arithmetic unit, and reference numeral 14 denotes an arithmetic encoder. The bit modeling calculator 13 inputs the wavelet coefficient output from the wavelet converter 10 and performs a bit modeling operation. The arithmetic encoder 14 receives the symbol and context output from the bit modeling arithmetic unit 13 and performs arithmetic encoding by the MQ-CODER system to generate encoded data.

  In the conventional image encoding apparatus shown in FIG. 14, the conversion result by the wavelet converter 10 is divided into rectangular areas called code blocks and cut out, and a bit modeling operation is performed for each cut out code block.

  FIG. 15 is a diagram showing the flow of processing in the bit modeling calculator 13. In FIG. 15, 15 indicates a code block cut out to a size of M × N pixels. In the code block 15, the wavelet coefficient of each pixel is decomposed by 1 bit, and bits of the same depth are collected. Thus, it is decomposed into M × N-bit data called bit planes 16-1 to 16-6.

  Further, the bit plane 16-k also selects each bit from the processing information processed so far as one of a significance propagation pass, a magnitude refinement pass, and a cleanup pass (hereinafter referred to as an SP pass, an MR pass, and a CL pass, respectively). The context determination process is performed in order of each pass and bit by bit.

  FIG. 16 is a diagram showing a processing order when the bit modeling computing unit 13 performs context determination processing for each path. That is, when performing the context determination process for each path, first, a vertical 4-bit context determination process called a stripe is sequentially performed from the upper left of the path, and then a 4-bit context determination process for the right adjacent stripe. Are performed in order, and this is repeated.

When reaching the right end, the same context determination processing is performed while shifting from the left end to the right direction for each stripe by shifting by one stripe in the vertical direction. In this order, the context is determined bit by bit and repeated to the lower right. This is performed in the order of the SP pass, the MR pass, and the CL pass. When the context determination processing for these three passes is completed, the process proceeds to the context processing for the next bit plane.
Japanese Patent Laid-Open No. 2003-32496 Japanese Patent Laid-Open No. 2003-8906

  In the conventional bit modeling computing unit 13, the data of the input code block 15 is decomposed into bit planes 16-1 to 16-6, and further, the bit plane is decomposed into three paths, one path at a time, and Since the context determination process is performed sequentially bit by bit, there is a problem that a lot of processing time is required.

  Japanese Patent Laid-Open No. 2003-32496 discloses a technique for performing bit modeling operations in parallel on a plurality of code blocks or a plurality of bit planes. However, in this case, the circuit scale is large. There is a problem of becoming.

  Japanese Patent Laid-Open No. 2003-8906 describes a technique for processing across the SP path, the MR path, and the CL path, but does not process these simultaneously, but waits for the processing result of the SP path. Since the MR path processing is performed and the CL path processing is performed after waiting for the MR path processing result, a waiting time occurs and a storage area for storing the SP path and MR path data is required. There is a problem that the circuit scale becomes large.

  In view of this point, the present invention provides a bit modeling computing unit capable of speeding up the bit modeling process with a simple configuration, and further reducing the size of a storage area for temporarily storing a context. It is an object of the present invention to provide a bit modeling calculator that can be realized.

  The bit modeling computing unit of the present invention uses a path computing unit that performs path determination processing for each bit in the bit plane, and each bit in the bit plane using path information, symbols, and significant information obtained by the path computing unit. A context calculator that performs the context determination process.

  According to the present invention, the context arithmetic unit uses the path information obtained by the path arithmetic unit for the context determination processing of each bit in the bit plane, so that the context is determined regardless of the path to which the target bit belongs. can do. Therefore, the bit modeling process can be speeded up with a simple configuration.

  When the context calculator is configured to perform the context determination process for each bit in the bit plane by simultaneously performing the context determination process in units of a plurality of bits, the bit modeling process is further accelerated. be able to.

  FIG. 1 is a schematic configuration diagram of a main part of an image encoding apparatus according to a JPEG2000 encoding system using an embodiment of the present invention. In FIG. 1, 20 is a wavelet converter, 21 is a code block data storage device, 22 is a bit modeling arithmetic unit according to an embodiment of the present invention, 23 is a symbol / context storage device comprising SRAM, and 24 is an arithmetic encoder. , 25 are stream generators.

  The wavelet converter 20 performs wavelet conversion on digitized input image data. The code block data storage device 21 stores code block data cut out from the conversion result of the wavelet converter 20.

  The bit modeling arithmetic unit 22 inputs code block data stored in the code block data storage device 21, performs bit modeling arithmetic, and generates symbols and contexts for arithmetic coding. The symbol / context storage device 23 stores symbols and contexts output from the bit modeling computing unit 22.

  The arithmetic encoder 24 reads symbols and contexts from the symbol / context storage device 23, performs arithmetic encoding by the MQ-CODER system, and generates encoded data. The stream generator 25 receives the encoded data output from the arithmetic encoder 24 and generates a bit stream of compressed image data.

  In the bit modeling computing unit 22, 26 is a path computing unit, 27 is an intermediate data storage device, 28 is a context computing unit, 29 is a significant bit storage device, and 30 is a bit modeling control device.

  The path calculator 26 inputs bit plane data (symbols) read from the code block data storage device 21 in units of 4 bits and determines the path of each bit plane. The intermediate data storage device 27 stores path information output from the path calculator 26 together with symbols and positive / negative signs.

  The context calculator 28 uses a symbol, path information and significant bit information stored in the intermediate data storage device 27, with 4 bits in the bit plane as a context determination processing unit, and a 4-bit context determination process in the bit plane. Are performed simultaneously to perform context determination processing for each bit in the bit plane. The significant bit storage device 29 stores significant bits obtained from the context calculator 28.

  The bit modeling control device 30 performs read control on the code block data storage device 21, write / read control on the intermediate data storage device 27, write / read control on the significant bit storage device 29, and write control on the symbol context storage device 23. Is.

  In the arithmetic encoder 24, 32 is an arithmetic unit, and 33 is an arithmetic control unit. The arithmetic unit 32 performs arithmetic coding on the symbols and contexts read from the symbol / context storage device 23 using the MQ-CODER method, and generates encoded data. The arithmetic control device 33 performs read control on the symbol context storage device 23 and arithmetic control of the arithmetic unit 32.

  FIG. 2 is a diagram showing a reading order of data of each bit of the bit plane from the code block data storage device 21. In the image encoding device shown in FIG. 1, a read address is given from the bit modeling control device 30 to the code block data storage device 21.

  2A shows a bit plane. In the image coding apparatus shown in FIG. 1, first, 4-bit data (symbol) in the vertical direction called a stripe from the upper left of the bit plane is a code block data storage device. 21 to the path calculator 26.

  Then, when the path of each bit of the stripe is determined by the path calculator 26, the data of the stripe on the right side of the stripe whose path has been determined is transferred from the code block data storage device 21 to the path calculator 26.

  Thereafter, such data transfer is repeated, and when the right end of the bit plane is reached, data is transferred in the same direction for each stripe by shifting by one stripe in the vertical direction. The bit plane data will be transferred.

  Here, the column number of each bit of the bit plane is m (where m = 1, 2,..., 14), and the row number is [4 (n−1) + i] (where n = 1, 2, 3). Assuming i = 1, 2, 3, 4), the path calculator 26 follows the order indicated by the arrows in FIG. 2A, as shown in FIG. 2B, [4 (n− 1) +1] to [4 (n-1) +4] rows of bit data (symbols) are input, and the path of each bit is determined.

  The path calculation unit 26 determines the path of each bit of the bit plane in the case of the uppermost bit of the stripe (bit [4 (n−1) +1] th row of the bit plane) (1 ), (2) or (3).

(1) “1” may appear before the bit plane currently being processed at the position of the target bit (the bit currently being processed as a target of processing) (the significant information of the target bit is already “1”) The path of the bit of interest is determined as the MR path.

(2) “There is one or more bits in the surrounding 8 bits that have not appeared in the condition of (1)” and “1” may have appeared before the bit plane before the currently processed bit plane. (If there are one or more bits with significant information “1” in the vicinity of 8 ”), the path of the target bit is determined as the SP path.

(3) If the above conditions (1) and (2) are not satisfied, the path of the bit of interest is determined as the CL path.

  Also, the second and lower bits of the stripe (bits [4 (n-1) +2], [4 (n-1) +3], and [4 (n-1) +4]) of the bit plane ), The path is determined as shown in the following (4), (5) or (6).

(4) When “1” has appeared before the currently processed bit plane at the target bit position (significant information of the target bit is already “1”), the path of the target bit is set to MR. Decide with a pass.

(5) “Does not apply to condition (4)” and ““ There are one or more bits in the 8 bits that have appeared “1” before the bit plane before the bit plane currently being processed. (There are one or more bits with significant information “1” in the vicinity of 8 ”) or“ in the bit plane currently being processed, it is determined that the SP path is in the area processed before the target bit. And the symbol is “1” (the bit above the target bit is the SP path and the symbol is “1”) ”)” And decide.

(6) If the above conditions (4) and (5) are not met, the path of the bit of interest is determined as the CL path.

  3 is a schematic configuration diagram of a path determiner included in the path calculator 26. FIG. 3A is a path determiner for the top bit of the stripe, and FIG. 3B is a second or less of the stripe. This is a path determiner for the bits.

  In FIG. 3A, reference numerals 34 and 35 denote selectors. The selector 34 uses the data indicating whether the significant information of the bit of interest is already “1” as selection control data, and is true (T). Is to select and output data indicating the MR path, and in the case of false (F), to select and output the output of the selector 35.

  The selector 35 uses, as selection control data, data indicating whether or not one or more bits having significant information “1” exist in the vicinity of 8 of the target bit. When true (T), the selector 35 is an SP path. In the case of false (F), data indicating the CL path is selected and output.

  In FIG. 3B, reference numerals 36, 37, and 38 denote selectors. The selector 36 uses as a selection condition whether or not the significant information of the bit of interest is already “1”. Data indicating the MR path is selected and output. In the case of false (F), the output of the selector 36 is selected and output.

  The selector 37 uses the data indicating whether the bit path above the target bit is the SP path and the symbol of the bit above the target bit is “1” as the selection control data, and true (T) In this case, data indicating the SP path is selected and output. In the case of false (F), the output of the selector 38 is selected and output.

  The selector 38 uses, as selection control data, data indicating whether or not one or more bits having significant information “1” exist in the vicinity of 8 of the target bit, and in the case of true (T), is an SP path. In the case of false (F), data indicating the CL path is selected and output.

  The path information output from the path calculator 26 is stored in the storage area for each stripe of the intermediate data storage device 27, and the intermediate data storage device 27 is given a read address from the bit modeling control device 30.

  FIG. 4 is a diagram showing a configuration example of a storage area for one word (storage unit) of the intermediate data storage device 27. In the storage area for 1 word of the intermediate data storage device 27, it is necessary to store the data for 1 bit on the stripe in addition to the data for 4 bits of the stripe. It is necessary to memorize three data of symbol path. The intermediate data storage device 27 requires a storage area for the number of words corresponding to the size of the code block.

  FIG. 5 is a diagram for explaining a significant information generation process required by the path calculator 26. In FIG. 5, 39-1 to 39-3 and 40-1 to 40-3 are registers formed of flip-flops provided in the path calculator 26.

  The registers 39-1 to 39-3 are 6-bit registers for storing significant information read from the significant bit storage device 29, and the register 40-1 is determined from the symbol and path information stored in the intermediate data storage device 27. Registers having a 5-bit configuration in which values based on the calculated values and the calculation results of the path calculator 26 are stored, registers 40-2 and 40-3 are values determined from the symbols and path information stored in the intermediate data storage device 27. Is a 1-bit register in which is stored.

  Bits 5 to 0 of the register 39-1 are provided corresponding to the bits in the (m−1) th column of the 4 (n−1) th to [4 (n−1) +5] th row of the bit plane. , Bit 5 to bit 0 of the register 39-2 are provided corresponding to the bits of the 4 (n-1) to [4 (n-1) +5] rows of the m-th column of the bit plane. Bits 5 to 0 of 3 are provided corresponding to the bits in the 4 (n−1) to [4 (n−1) +5] rows of the (m + 1) column of the bit plane.

  Bits 5 to 1 of the register 40-1 are provided corresponding to bits in the 4 (n-1) to 4 (n-1) +4] rows of the (m-1) column of the bit plane. -2 is provided corresponding to the bit in the 4th (n-1) th row of the mth column of the bit plane, and the register 40-3 is the 4th (n-1) th row in the (m + 1) th column of the bit plane. It is provided corresponding to the bit.

  Here, when determining the bit path of the [4 (n-1) +1] to [4 (n-1) +4] rows of the m-th column of the bit plane, the bits 5 to 5 of the register 39-1 are determined. Bit 0 stores significant information of bits in the 4 (n-1) to [4 (n-1) +5] rows of the (m-1) column of the bit plane, and bits 5 to 5 of the register 39-2 are stored. Bit 0 stores significant information of bits in the 4th (n−1) to [4 (n−1) +5] rows of the m-th column of the bit plane, and bits 5 to 0 of the register 39-3. Significant information of the bits in the 4 (n-1) to [4 (n-1) +5] rows of the (m + 1) column of the bit plane is stored.

  When m = 1, the (m−1) th column is the 0th column and is the column on the left outer side of the bit plane. In this case, “0” is stored in bits 5 to 0 of the register 39-1. "Is memorized. When m = 14, the (m + 1) th column is the 15th column and is the column on the right outer side of the bit plane. In this case, “0” is set in bits 5 to 0 of the register 39-3. Remembered.

  When n = 1, the 4 (n-1) th row is the 0th row and is the upper and outer rows of the bit plane. In this case, the bit 5 of the registers 39-1 to 39-3 is “0” is stored. When n = 3, the [4 (n−1) +5] line is the 13th line, which is the lower outer line of the bit plane. In this case, the bits of the registers 39-1 to 39-3 “0” is stored in 0.

  Each of bit 5 of register 40-1 and registers 40-2 and 40-3 stores “1” when the corresponding bit of the bit plane is SP path and symbol = “1”. In other cases, “0” is stored. In bits 4 to 1 of the register 40-1, a value based on the calculation result of the path calculator 26 is stored. When the SP path and the symbol = “1” in the previous processing stripe, “1” is stored. In other cases, “0” is stored.

  When m = 1, the (m−1) th column is the 0th column and is the column on the left outer side of the bit plane. In this case, “0” is set in bits 5 to 1 of the register 40-1. "Is memorized. When n = 1, the 4 (n−1) th row is the 0th row and is the upper and outer rows of the bit plane. In this case, bit 5 of the register 40-1 and the register 40-2, 40-3 stores "0".

  Then, the path computing unit 26 performs OR processing of the corresponding bits of the registers 39-1 to 39-3 and the registers 40-1 to 40-3, and the data obtained by this OR processing is the significant information 41 of the target stripe. Are transferred to the path determiner together with the symbol 42 of the target stripe, and the path is determined. In FIG. 5C, the portion surrounded by the thick line 43 indicates the data valid area of the registers 40-1 to 40-3.

  FIG. 6 is a diagram for explaining a significant information generation process required by the context calculator 28. In FIG. 6, 44-1 to 44-3, 45-1 to 45-3, and 46-1 to 46-3 are registers formed of flip-flop circuits included in the context calculator 28.

  Registers 44-1 to 44-3 are 6-bit registers in which significant information read from the significant bit storage device 29 is stored, and registers 45-1 to 45-3 are symbols stored in the intermediate data storage device 27. Registers of 6-bit configuration in which values determined from the path information and values based on the calculation result of the path calculator 26 are stored, registers 46-1 to 46-3 are based on symbols and path information stored in the intermediate data storage device 27. This is a 5-bit register in which the value to be determined is stored.

  Bits 5 to 0 of the register 44-1 are provided corresponding to bits in the 4 (n-1) to [4 (n-1) +5] rows of the (m-1) column of the bit plane. Bits 5 to 0 of 44-2 are provided corresponding to bits of 4 (n-1) to [4 (n-1) +5] rows of the mth column of the bit plane, and are bits of the register 44-3. 5 to 0 are provided corresponding to the bits in the 4 (n-1) to [4 (n-1) +5] rows of the (m + 1) column of the bit plane.

  Bits 5 to 0 of the register 45-1 are provided corresponding to the bits in the 4 (n-1) to [4 (n-1) +5] rows of the (m-1) column of the bit plane. Bits 5 to 0 of 45-2 are provided corresponding to bits of 4 (n-1) to [4 (n-1) +5] rows of the mth column of the bit plane, and are bits of the register 45-3. 5 to 0 are provided corresponding to the bits in the 4 (n-1) to [4 (n-1) +5] rows of the (m + 1) column of the bit plane.

  Bits 5 to 1 of the register 46-1 are provided corresponding to the bits in the 4 (n-1) to [4 (n-1) +4] rows of the (m-1) column of the bit plane. Bits 5 to 1 of 46-2 are provided corresponding to bits of 4 (n-1) to [4 (n-1) +4] rows of the m-th column of the bit plane, and are bits of the register 46-3. 5 to 1 are provided corresponding to the bits in the 4 (n-1) to [4 (n-1) +4] rows of the (m + 1) column of the bit plane.

  Here, when determining the context of the bits in the [4 (n−1) +1] to [4 (n−1) +4] rows in the m-th column of the bit plane, bits 5 to 5 of the register 44-1 are determined. Bit 0 stores significant information of bits in the 4 (n-1) to [4 (n-1) +5] rows of the (m-1) column of the bit plane, and bits 5 to 5 of the register 44-2 are stored. Bit 0 stores significant information of bits in the 4th (n-1) to [4 (n-1) +5] rows of the m-th column of the bit plane, and bits 5 to 0 of the register 44-3. Significant information of the bits in the 4 (n-1) to [4 (n-1) +5] rows of the (m + 1) column of the bit plane is stored.

  When m = 1, the (m−1) th column is the 0th column and is the column on the left outer side of the bit plane. In this case, bits 5 to 0 of the register 44-1 are “0”. Is memorized. When m = 14, the (m + 1) -th column is the 15th column and is the right outer column of the bit plane. In this case, “0” is set in bits 5 to 0 of the register 44-3. Remembered.

  In addition, when n = 1, the 4 (n−1) th row is the 0th row and is the upper and outer rows of the bit plane. In this case, the bit 5 of the registers 44-1 to 44-3 “0” is stored. When n = 3, the [4 (n-1) +5] -th row is the 13th row, which is the lower outer row of the bit plane. In this case, the bits of the registers 44-1 to 44-3 are used. “0” is stored in 0.

  Each of bits 5 to 0 of the registers 45-1 to 45-3 stores “1” when the corresponding bit of the bit plane is SP path and symbol = “1”. In this case, “0” is stored. Bit 0 of the registers 45-1 to 45-3 stores a value based on the calculation result of the path calculator 26. When the SP path and symbol = “1”, “1” is stored. “0” is stored in.

  When m = 1, the (m−1) th column is the 0th column and is the column on the left outer side of the bit plane. In this case, “0” is stored in bits 5 to 0 of the register 45-1. "Is memorized. When m = 14, the (m + 1) -th column is the 15th column and is a column on the right outer side of the bit plane. In this case, “0” is set in bits 5 to 0 of the register 45-3. Remembered.

  When n = 1, the 4 (n−1) th row is the 0th row and is the upper and outer rows of the bit plane. In this case, the registers 45-1, 45-2, 45-3 Bit 5 stores “0”. When n = 3, the [4 (n-1) +5] -th row is the 13th row, which is the lower outer row of the bit plane. In this case, the registers 45-1, 45-2, 45 “0” is stored in bit 0 of −3.

  Each of bits 5 to 1 of the registers 46-1 to 46-3 stores "1" when the corresponding bit of the bit plane is a CL path and the symbol = "1". In this case, “0” is stored.

  When m = 1, the (m−1) -th column is the 0th column and is a column on the left outer side of the bit plane. In this case, “0” is set in bits 5 to 1 of the register 46-1. "Is memorized. When m = 14, the (m + 1) -th column is the fifteenth column, which is the right outer column of the bit plane. In this case, “0” is set in bits 5 to 1 of the register 46-3. Remembered. When n = 1, the 4 (n-1) th row is the 0th row and is the upper and outer rows of the bit plane. In this case, the bit 5 of the registers 46-1 to 46-3 “0” is stored.

  FIG. 6D shows significant information 48 in the SP path around the target stripe created by the context computing unit 28, and portions 49 surrounded by bold lines are registers 44-1 to 44-3 and registers 45-1 to 45-1. The OR of the corresponding part 45-3 is taken and the code block end is taken into consideration, and the other part 50 takes the code block end from the registers 44-1 to 44-3 into consideration.

  FIG. 6E shows significant information 51 in the CL path around the stripe of interest created by the context calculator 28. The portions 52 surrounded by thick lines are the registers 44-1 to 44-3 and the registers 45-1 to 45-1. 45-3 and the registers 46-1 to 46-3 are ORed to take account of the end of the code block, and the other part 53 is composed of registers 44-1 to 44-3 and registers 45-1. OR of the corresponding portions of .about.45-3 is taken into account and the code block end is taken into consideration.

  FIG. 7 is a diagram for explaining the context determination process performed by the context calculator 28. The context calculator 28 simultaneously performs a 4-bit context determination process for the stripe of interest. In each case, the context is determined as follows.

(C1) When all four bits of the target stripe are CL paths, the run length context calculator 55 determines the run length context as shown in FIG.

(C2) When the target bit is the SP path and the first bit of the stripe, as shown in FIG. 7B, 8 from the significant information 48 in the SP path around the target stripe shown in FIG. Using the neighborhood significant information, the context is determined by referring to the context table 56 based on the information indicating whether or not “1” has appeared up to the previous bit plane in the 8 bits around the bit of interest.

(C3) When the target bit is the SP pass and the second and lower bits of the stripe, as shown in FIG. 7C, the target bit of the significant information 48 in the SP path around the target stripe shown in FIG. 6D Significant information of 8 neighborhoods excluding the bits above, “1” if the bit above the target bit is SP pass and symbol = “1”, “0” otherwise, and the periphery of the target stripe The context is determined by referring to the context table 56 using the information obtained by ORing the significant information of the bit above the target bit among the significant information 48 in the SP path.

(C4) If the target bit is an MR path, as shown in FIG. 7D, the 8-neighbor significant information from the significant information 48 in the SP path around the target stripe shown in FIG. The context is determined by referring to the context table 56 using the information on whether or not.

(C5) When the target bit is a CL path and the first bit in the stripe, as shown in FIG. 7E, 8 from the significant information 51 in the CL path around the target stripe shown in FIG. Using the neighborhood significant information, the context is determined by referring to the context table 56 based on the information indicating whether or not “1” has appeared up to the previous bit plane in the 8 bits around the bit of interest.

(C6) When the target bit is a CL pass and the second or lower bit of the stripe, as shown in FIG. 7F, the target bit of the significant information 51 in the CL path around the target stripe shown in FIG. Significant information of 8 neighborhoods excluding the bits above, “1” if the bit above the target bit is a CL path and symbol = “1”, “0” otherwise, and the periphery of the target stripe The context is determined with reference to the context table 56 using the information obtained by ORing the significant information of the bit above the target bit among the significant information 51 in the CL path.

  As described above, the context calculator 28 determines the context as shown in (C1) to (C6). Therefore, as shown in FIG. 8, the 4 bits of the stripe are used as the context determination processing unit. A 4-bit context determination process can be performed simultaneously. As a result, the context processing can be performed at a speed 12 times faster than the case of processing one pass at a time and one bit at a time as in the context determination processing in the bit modeling computing unit 13 shown in FIG.

  FIG. 9 is a diagram showing the relationship between the path calculation position on the bit plane and the context calculation position in the bit modeling calculator 22. In FIG. 9, 58 is an area where context calculation has been completed, 59 is a position where context calculation is currently being performed, 60 is an area where only path calculation has been completed, and 61 is a position where path calculation is being performed.

  Here, in order to determine the 4-bit context of the target stripe, the path of the bits under the target stripe must be determined. For this reason, the context calculation position 59 needs to be delayed by one stage or more from the path calculation position 61. However, the context calculation position 59 is delayed by one bit in the vertical direction and two bits in the horizontal direction from the path calculation position 61. In this case, the calculation result of the path calculation unit 26 one stage below the context calculation position 59 can be transferred to the context calculation unit 28 without using a storage device.

  Therefore, in this case, an extra storage device is not required and the circuit scale can be prevented from becoming larger than necessary. Further, when only the path information in the area 60 where only the path calculation is completed is stored in the intermediate data storage device, the scale of the intermediate data storage device 27 can be reduced.

  FIG. 10 is a diagram illustrating an example of context output from the bit modeling calculator 22 according to the embodiment of the present invention. As illustrated in FIG. The contexts of the path, MR path, and CL path are mixed and output. However, in the arithmetic encoder 24, the processing of the MR path data is performed after all the SP path data in the same bit plane is processed, and the processing of the CL path data is completed after the processing of the MR path data is completed. Is done.

  Therefore, if the data output from the bit modeling arithmetic unit 22 is stored in the symbol context storage device 23 in the output order as it is, as shown in FIG. There is a waiting time until the data is output. This waiting time slows down the arithmetic coding process and increases the overall processing time.

  As a method for solving this problem, for example, as shown in FIG. 11, the symbol context storage device 23 includes an SP path SRAM 62, an MR path SRAM 63, a CL path SRAM 64, and SRAMs 62- It can be considered that a selector switch circuit 65 for selecting 64 outputs is provided.

  In this case, at the time of writing, the SP path data, the MR path data, and the CL path data are written to the SP path SRAM 62, the MR path SRAM 63, and the CL path SRAM 64, respectively, and read out. Sometimes the SP path data stored in the SRAM 62 is read first, and then the MR path data and the CL path data are read in this order.

  However, since the number of paths is indefinite and all bit plane data may be MR paths or CL paths, the SRAMs 62 to 64 for each path may be used when data is the largest. In comparison with an SRAM in which data of three paths are stored in order in one SRAM, a capacity three times as large is required.

  Therefore, as shown in FIG. 12, one SRAM 67 is used as the symbol context storage device 23, and the number of bits belonging to the SP path, MR path, and CL path of the bit plane being processed in advance is determined by the bit modeling control device 30. A method is conceivable in which the area of the SRAM 67 is divided into an SP path data storage area 68, an MR path data storage area 69, and a CL path data storage area 70.

  In this case, SP path data, MR path data, and CL path data are stored in the SP path data storage area 68, MR path data storage area 69, and CL path data storage area 70, respectively, at the time of writing, and SP path data storage at the time of reading. The SP path data, MR path data, and CL path data are read in this order from the area 68, the MR path data storage area 69, and the CL path data storage area 70.

  In this case, an increase in the capacity of the symbol context storage device 23 can be suppressed. Here, since the bits belonging to the MR path are bits whose symbols have been “1” by the previous bit plane, the MR in the bit plane to be processed this time is processed when the processing of the previous bit plane is completed. Although it is easy to know the number of bits in the path, the number of bits belonging to the SP path and the CL path changes during the bit plane processing, so it is difficult to know before the processing.

  Therefore, it is conceivable that the symbol context storage device 23 is constituted by one SRAM 67 and used as shown in FIG. In this usage example, the number of bits in the MR path is measured by the bit modeling control device 30 during the processing of the previous bit plane, and when the processing of the previous bit plane is completed, the bit modeling control device 30 detects the MR path of the SRAM 67. That is, only a certain data storage area 71 is determined from one end of the storage space of the SRAM 67 as the MR path data storage area 71, and the remaining storage area 72 is set as the SP path / CL path data storage area. .

  MR path data storage area 71 sequentially stores MR path data as indicated by arrow Y1, and SP path / CL path data storage area 72 stores SP path data and CL path data. As shown by arrows Y2 and Y3, the data is stored in opposite directions from both ends of the storage space of the data storage area 72, respectively.

  Here, since the total number of bits of the final SP pass and the number of bits of the CL pass does not change, the respective data areas do not overlap. With such a configuration, the SRAM 67 can be used effectively, and it is not necessary to use an extra SRAM, and the symbol context storage area can be reduced in size. At the time of reading, as indicated by arrows Y4 and Y5, SP path data, MR path data, and CL path data are read in this order.

  In this case, the write control for the symbol context storage device 23 is performed by giving a write address from the bit modeling control device 30 to the symbol context storage device 23, and the read control for the symbol context storage device 23 is performed by an arithmetic operation. This is performed by giving a read address from the control device 33 to the symbol context storage device 23.

  As described above, according to the bit modeling computing unit 22 of one embodiment of the present invention, the path computing unit 26 performs the path determination processing of each bit in the bit plane using the 4 bits of the stripe as the path determination processing unit. The context calculation unit 28 performs the context determination processing for each bit in the bit plane by simultaneously performing the 4-bit context determination processing for the stripe using the 4 bits of the stripe as the context determination processing unit.

  Since the context calculator 28 uses the path information obtained by the path calculator 26 for the context determination processing of each bit in the bit plane, no matter which path the target bit belongs to, the context calculator 28 Can be determined. Therefore, the bit modeling process can be speeded up with a simple configuration.

  In the bit modeling computing unit 22 according to the embodiment of the present invention, the context computing unit 28 performs the 4-bit context determination processing for the stripe at the same time. However, the 4-bit context determination processing for the stripe is performed bit by bit. It can also be configured to do.

  In such a configuration, the bit modeling processing speed is slower than in the case of the bit modeling computing unit 22 according to the embodiment of the present invention. However, the context computing unit 28 still does not use the bit computing unit 22 of each bit plane. Since the path information obtained by the path calculator 26 is used for the context determination process, the context can be determined regardless of the path to which the target bit belongs. Therefore, the bit modeling process can be speeded up with a simple configuration.

It is a schematic block diagram of the principal part of the image coding apparatus by the JPEG2000 coding system which uses one Embodiment of this invention. It is a figure which shows the reading order of the data of each bit of the bit plane from the code block data storage apparatus with which the image coding apparatus shown in FIG. 1 is provided. It is a schematic block diagram of the path | pass decision unit with which the path | pass calculator with which the bit modeling calculator of one Embodiment of this invention is provided is provided. It is a figure which shows the structural example of the storage area for 1 word of the intermediate data storage apparatus with which the bit modeling calculating unit of one Embodiment of this invention is provided. It is a figure for demonstrating the production | generation process of the significant information required by the path | pass calculator with which the bit modeling calculator of one Embodiment of this invention is provided. It is a figure for demonstrating the production | generation process of the significant information required by the context computing unit with which the bit modeling computing unit of one Embodiment of this invention is provided. It is a figure for demonstrating the context determination process performed with the context calculator with which the bit modeling calculator of one Embodiment of this invention is provided. It is a figure for demonstrating the context determination processing speed in the bit modeling arithmetic unit of one Embodiment of this invention. It is a figure which shows the relationship between the path calculation position on a bit plane in the bit modeling calculating unit of one Embodiment of this invention, and a context calculation position. It is a figure which shows the example of an output of the context from the bit modeling calculating unit of one Embodiment of this invention. It is a figure which shows the 1st structural example of the symbol context memory | storage device with which the image coding apparatus shown in FIG. 1 is provided. FIG. 3 is a diagram for explaining a second configuration example and a first usage example of a symbol / context storage device included in the image encoding device shown in FIG. 1. It is a figure for demonstrating the 2nd structural example and 2nd usage example of the symbol context memory | storage device with which the image coding apparatus shown in FIG. 1 is provided. It is a schematic block diagram of the principal part of an example of the conventional image coding apparatus by a JPEG2000 coding system. It is a figure which shows the flow of a process in the bit modeling calculating unit with which the conventional image coding apparatus shown in FIG. 14 is provided. It is a figure which shows the process order in case the bit modeling arithmetic unit with which the conventional image coding apparatus shown in FIG. 14 is provided performs a context determination process about each path | pass.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Wavelet converter 11 ... Entropy encoder 12 ... Stream generator 13 ... Bit modeling calculator 14 ... Arithmetic encoder 15 ... Code block 16-1 to 16-6 ... Bit plane 20 ... Wavelet converter 21 ... Code block data storage device 22 ... Bit modeling computing unit (one embodiment of the present invention)
DESCRIPTION OF SYMBOLS 23 ... Symbol / context storage device 24 ... Arithmetic encoder 25 ... Stream generator 26 ... Path calculator 27 ... Intermediate data storage device 28 ... Context calculator 29 ... Significant bit storage device 30 ... Bit modeling control device 32 ... Calculator 33 ... arithmetic control devices 34 to 38 ... selectors 39-1 to 39-3 ... registers 40-1 to 40-3 ... registers 44-1 to 44-3 ... registers 45-1 to 45-3 ... registers 46-1 46-3. Register 65 ... Changeover switch circuit

Claims (4)

A path calculator that performs path determination processing for each bit in the bit plane;
A bit modeling arithmetic unit comprising a context arithmetic unit that performs context determination processing of each bit in the bit plane using path information, symbols, and significant information obtained by the path arithmetic unit.   The bit modeling arithmetic unit according to claim 1, wherein the context arithmetic unit performs a context determination process for each bit in the bit plane by simultaneously performing a context determination process in units of a plurality of bits. The path determination process and the context determination process are performed by raster scanning the bit plane in units of stripes composed of a plurality of vertical bits.
The path computing unit and the context computing unit are controlled in operation positions so that a path of a bit below one bit of a stripe on which the context computing unit actually performs context determination processing has already been determined. The bit modeling arithmetic unit according to claim 1. A control device for controlling a storage device for storing output data of the context calculator;
The control device calculates the number of bits belonging to the MR path in units of the bit plane, and from one end of the storage space of the storage device to a certain storage area, a storage area for output data belonging to the MR path, and the remaining storage area Is a storage area for data belonging to the SP path and data belonging to the CL path, and data belonging to the SP path and data belonging to the CL path are respectively stored in opposite directions from both ends of the storage space of the remaining storage area. The bit modeling arithmetic unit according to claim 1, wherein:

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