JP2005340409A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor that dispenses with the alignment among a gate electrode, a source electrode, and a drain electrode, and can obtain both of a high on/off ratio and high-speed operation even if finishing dimensions deviate, and to provide a method for manufacturing the field effect transistor. <P>SOLUTION: In the field effect transistor having the source electrode 2 and the drain electrode 3 via an insulating layer 5 and an active layer 4 on the gate electrode 1, a recessed groove in an inverted trapezoidal shape is formed at the surface section of the active layer 4, and the source electrode 2 and the drain electrode 3 are formed on one inclined plane and the other inclined one of the recessed groove in an inverted trapezoidal shape, respectively. As its manufacturing method, the recessed groove in an inverted trapezoidal shape is formed by selectively removing one portion of the active layer, resin is formed so that the active layer including the recessed groove is covered, and only resin at the inclined plane section of the recessed groove in an inverted trapezoidal shape is removed, for example, by ashing the resin, thus forming the source and drain electrodes at the inclined plane section. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a field effect transistor, and more particularly to a field effect transistor suitable for driving a liquid crystal and a method for manufacturing the field effect transistor.

  For example, a field effect transistor having a structure as shown in FIG. 9 is known as a conventional field effect transistor for driving a display device such as a liquid crystal. This field effect transistor has a structure in which a gate electrode is provided on a substrate, and a source electrode and a drain electrode are formed via an insulating layer and an active layer (channel layer) provided on the gate electrode. .

On the other hand, field effect transistors have been increasingly required to operate at high speed in recent years. For this reason, for example, a field effect transistor having a structure as shown in FIG. In the field effect transistor shown in FIG. 10, a gate electrode is formed on a channel layer on the surface of a semi-insulating GaAs substrate, and a source electrode and a drain electrode are formed with the gate electrode interposed therebetween. The electrode and the n ⁺ source region / drain region are configured to be self-aligned. Then, the channel length is shortened to about 1 μm so that the capacitance between the source electrode and the drain electrode with respect to the gate electrode is reduced, so that high speed operation is achieved. In this case, the alignment accuracy is about 1 μm when a mask aligner is used, and about 0.5 μm when an electron beam exposure apparatus is used.
JP-A-5-13444

By the way, when driving a display device such as a liquid crystal, it is required to satisfy both an on / off ratio of 10 ⁶ or more and a high-speed operation. Therefore, ideally, the channel length (distance between source / drain) ) And the gate length are desirable. However, in practice, in such alignment, it is difficult to avoid a deviation between the finished size and the design size.
Therefore, in the field effect transistor having the structure shown in FIG. 10 of the conventional example, the ON / OFF ratio becomes small when misalignment occurs due to the alignment accuracy during alignment between the gate electrode, the source electrode, and the drain electrode. It will be.

Further, in the conventional field effect transistor having the structure shown in FIG. 9, since the source electrode and the drain electrode overlap with the gate electrode, the on / off ratio can be increased. Since the capacitance between the gate electrode and the source / drain electrode is increased, the cutoff frequency is decreased, which causes a problem in performing high-speed operation.
As described above, in the field effect transistor of the conventional example, it is difficult to satisfy both the ON / OFF ratio of 10 ⁶ or more and the high-speed operation required for driving a display device such as a liquid crystal.

  Therefore, in view of the above problems, the present invention eliminates the need for alignment between the gate electrode, the source electrode, and the drain electrode, and obtains both a high on / off ratio and high-speed operation even if the finished dimensions are displaced. It is an object of the present invention to provide a field effect transistor and a method for manufacturing the field effect transistor that enable the above.

The present invention provides a field effect transistor configured as follows and a method for manufacturing the field effect transistor.
That is, the field effect transistor of the present invention is a field effect transistor having a source electrode and a drain electrode via an insulating layer and an active layer on a gate electrode, and an inverted trapezoidal groove is formed on the surface of the active layer. And a source electrode is formed on one slope of the inverted trapezoidal concave groove, and a drain electrode is formed on the other slope.
The field effect transistor of the present invention is a field effect transistor having a source electrode and a drain electrode on an insulating layer and an active layer on a gate electrode, and an inverted trapezoidal groove is formed on the surface of the insulating layer. And a source electrode is formed on one slope of the inverted trapezoidal concave groove through the active layer, and a drain electrode is formed on the other slope through the active layer.
In the method of manufacturing the field effect transistor of the present invention, a part of the active layer is selectively removed to form an inverted trapezoidal groove, and the active layer including the groove is covered. In addition, a step of forming a resin, a step of removing only the resin on the inclined surface of the inverted trapezoidal groove by ashing or etching the resin, and a region of the inclined surface portion from which the resin has been removed, And at least a step of forming a source electrode and a drain electrode.
In the method of manufacturing the field effect transistor of the present invention, a part of the active layer is selectively removed to form an inverted trapezoidal groove, and the active layer including the groove is covered. In addition, a photoresist is formed, and the photoresist is exposed from the opposite side of the surface coated with the photoresist and then developed, so that only the photoresist on the inclined surface of the inverted trapezoidal groove is developed. And a step of forming a source electrode and a drain electrode in a region of the slope portion from which the photoresist has been removed.
In the method of manufacturing a field effect transistor according to the present invention, a part of the insulating layer is selectively removed to form an inverted trapezoidal groove, and the insulating layer including the groove is covered. A step of forming an active layer and a resin, a step of removing only the resin on the inclined surface of the inverted trapezoidal groove by ashing or etching the resin, and a region of the inclined surface from which the resin is removed And at least a step of forming a source electrode and a drain electrode.
In the method of manufacturing a field effect transistor according to the present invention, a part of the insulating layer is selectively removed to form an inverted trapezoidal groove, and the insulating layer including the groove is covered. And forming the active layer and the photoresist, and exposing the photoresist from the opposite side of the surface coated with the photoresist, and developing the photoresist, thereby developing the slope of the inverted trapezoidal groove. The method includes at least a step of removing only the photoresist and a step of forming a source electrode and a drain electrode in the region of the slope portion from which the photoresist has been removed.

  According to the present invention, it is not necessary to align the gate electrode, the source electrode, and the drain electrode, and it is possible to obtain both a high on / off ratio and high-speed operation even if the finished dimensions are shifted. A field effect transistor and a method of manufacturing the field effect transistor can be realized.

  The best mode for carrying out the invention is further illustrated by the following examples.

[Example 1]
The first embodiment of the present invention applies the above-described configuration of the present invention, and a specific configuration thereof will be described with reference to the drawings.
FIG. 1 is a cross-sectional view schematically showing the structure of a field effect transistor in the present embodiment, in which 1 is a gate electrode, 2 is a source electrode, 3 is a drain electrode, 4 is an active layer, 5 is an insulating layer, 6 is a substrate.
FIG. 2 is a cross-sectional view schematically showing the process for producing the field effect transistor in this embodiment of FIG. 1, in which the process for producing the field effect transistor proceeds in alphabetical order.
In FIG. 2, 10 is a photoresist and 20 is a resin.

Next, a manufacturing process of the field effect transistor of this example will be described with reference to FIG.
First, as shown in FIG. 2A, a gate electrode 1 (thickness 300 nm) made of Al, a silicon nitride insulating layer (thickness 300 nm) 5, an amorphous silicon active layer (thickness 1 μm) 4 on a glass substrate 6. Is formed.
Then, AZ-1350 (Hoechst) is applied as a photoresist 10 to the amorphous silicon active layer 4 so as to have a film thickness of 1 μm.
After pre-baking at 80 ° C. for 30 minutes, the wafer is exposed with a mask.
The photoresist 10 after development and rinsing has a slightly tapered shape as shown in FIG.

Next, when reactive ion etching (RIE) is performed using the photoresist 10 as an etching mask and CF ₄ —O ₂ gas, the amorphous silicon active layer 4 is selectively etched.
When the photoresist 10 is removed after the etching is completed, a groove narrower than the opening of the photoresist 10 is formed as shown in FIG. That is, a channel length shorter than that of a pattern that can be formed by a mask aligner can be realized.
At this time, the width of the bottom of the groove is 1 μm, and the thickness of the amorphous silicon active layer 4 at the bottom of the groove is 10 nm.

Next, a photoresist is applied as the resin 20 so as to cover the amorphous silicon active layer 4. The film thickness of the resin 20 after application is 1 μm at the bottom of the groove.
Thereafter, after pre-baking and heat treatment at 80 ° C. for 30 minutes, the resin 20 is ashed using O ₂ gas as shown in FIG.
Since the resin 20 at the bottom of the groove is thicker than the other parts, the resin 20 remains only in the region at the bottom of the groove after ashing as shown in FIG. Here, the photoresist used as the resin 20 is ashed using O ₂ gas, but may be etched using Ar gas or the like.

When an Al electrode is deposited so as to cover the resin 20 and lift-off is performed, the source electrode 2 and the drain electrode 3 are formed as shown in FIG. Thereafter, as shown in FIG. 2G, a photoresist 10 is formed so as to cover the source electrode 2 and the drain electrode 3 inside the groove, and the source electrode 2 and the drain in the region where the photoresist 10 is not formed. When the electrode 3 is removed, as shown in FIG. 2 (h), the field effect transistor having the structure of FIG. 1 in this embodiment in which the source electrode 2 and the drain electrode 3 are formed on the slope of the inverted trapezoidal groove is obtained. .
The material system is not limited to the above, and a semiconductor such as polysilicon or GaAs or an organic layer may be used as the active layer 4, and the electrode may be selected according to the active layer. Furthermore, the insulating layer 5 is not limited to silicon nitride, and may be anything as long as it satisfies the specifications.

Next, the characteristics of the structure of this embodiment will be described.
FIG. 3 is a diagram showing current-voltage characteristics of the field-effect transistor prototyped by the manufacturing process of FIG. 2, in which (a) shows the relationship between drain current and drain voltage (parameter is gate voltage VG), (B) shows the relationship between the drain current and the gate voltage (the parameter is the drain voltage VD). The channel width is 10 μm.

As shown in FIG. 3A, as the drain voltage increases, the drain current tends to saturate, indicating the characteristics of a typical field effect transistor. As shown in FIG. 3B, when the drain voltage VD is 10 V, the ratio of the drain current when the gate voltage is 10 V and 0 V, that is, the on / off ratio is 6.98 × 10 ^8. It can be seen that the on / off ratio required for driving the display device is larger than 10 ⁶ and satisfies the specifications.

Next, the cutoff frequency will be described.
In the structure of FIG. 1, the source electrode 2 and the drain electrode 3 are formed on the slope of the groove. Therefore, the gate-source capacitance and the gate-drain capacitance are smaller and the cutoff frequency is larger than the conventional example of FIG. For example, the cutoff frequency when the source electrode and the drain electrode overlap with the gate electrode by 1 μm is 3.16 MHz in the conventional example of FIG. 9, whereas the structure of FIG. 1 is improved to 4.51 MHz. As a result, high-speed operation can be achieved.
Therefore, according to the present embodiment, it is possible to obtain both a high on / off ratio and a high-speed operation required when driving a display device such as a liquid crystal.

[Example 2]
The second embodiment of the present invention applies the above-described configuration of the present invention, and a specific configuration thereof will be described with reference to the drawings.

FIG. 4 is a cross-sectional view schematically showing a manufacturing process of the field effect transistor of this example. In the figure, the same components as those in FIG. Reference numeral 11 denotes a negative photoresist.
Next, a manufacturing process of the field effect transistor of this example will be described.
First, as shown in FIG. 4A, an amorphous silicon active layer (thickness 1 μm) 4 and a silicon nitride insulating layer (thickness 300 nm) 5 are stacked.
Then, AZ-1350 (Hoechst) is applied as a photoresist 10 to the amorphous silicon active layer 4 so as to have a film thickness of 1 μm. After pre-baking at 80 ° C. for 30 minutes, the wafer is exposed with a mask. The photoresist 10 after development and rinsing has a slightly tapered shape as shown in FIG. Next, when reactive ion etching (RIE) is performed using the photoresist 10 as an etching mask and CF ₄ —O ₂ gas, the amorphous silicon active layer 4 is selectively etched. When the photoresist 10 is removed after the etching is completed, the result is as shown in FIG. At this time, the width of the bottom of the groove is 1 μm, and the thickness of the amorphous silicon active layer 4 at the bottom of the groove is 10 nm.

Next, a negative photoresist RU-1100 (manufactured by Hitachi Chemical Co., Ltd.) 11 was applied so that the film thickness at the bottom of the groove was 1 μm, and after heat treatment at 80 ° C. for 30 minutes as a prebake, As shown in FIG. 4D, the negative photoresist 11 is exposed to ultraviolet light from the silicon nitride insulating layer 5 side.
The intensity of the ultraviolet light after propagating through the thick part of the active layer 4 is smaller than the intensity of the ultraviolet light after propagating through the thin part of the active layer 4, so that after development and rinsing, as shown in FIG. Thus, the negative photoresist 11 remains only in the region at the bottom of the groove.

  Next, an Al electrode is deposited so as to cover the negative photoresist 11, lift-off is performed, the source electrode 2 and the drain electrode 3 are formed on the slope of the groove, and the gate electrode on the insulating layer 5 and the substrate 6 is formed. The structure of FIG. 4F is formed by bonding. Thereafter, as shown in FIG. 4G, a photoresist 10 is formed so as to cover the source electrode 2 and the drain electrode 3 inside the groove, and the source electrode 2 and the drain in the region where the photoresist 10 is not formed. When the electrode 3 is removed, the structure of FIG. 1 is formed as shown in FIG.

Note that a substrate that supports a wafer as appropriate may be used in the above steps. In addition, the material system is not limited to the above, and a semiconductor such as polysilicon or GaAs or an organic layer may be used as the active layer 4, and an electrode may be selected according to the active layer. Furthermore, the insulating layer 5 is not limited to silicon nitride, and may be anything as long as it satisfies the specifications.
According to the field effect transistor having the structure of FIG. 1 made in the manufacturing process of FIG. 4 of the present embodiment, the characteristics shown in FIG. 3 can be obtained as in the case of the manufacturing process of FIG.

[Example 3]
The third embodiment of the present invention applies the above-described configuration of the present invention, and a specific configuration thereof will be described with reference to the drawings.
FIG. 5 is a cross-sectional view schematically showing the structure of the field effect transistor in this embodiment. In FIG. 5, the same components as those in FIG. The difference between this example and Example 1 is that a groove was formed in the active layer 4 in Example 1 of FIG. 1, whereas a groove was formed in the insulating layer 5 in this example of FIG.
FIG. 6 is a cross-sectional view schematically showing the process for producing the field effect transistor in this embodiment of FIG. 5 described above, in which the process for producing the field effect transistor proceeds in alphabetical order.

Next, a manufacturing process of the field effect transistor of this example will be described with reference to FIG.
First, as shown in FIG. 6A, a gate electrode 1 (thickness 300 nm) and a silicon nitride insulating layer (thickness 1 μm) 5 made of Al are formed on a glass substrate 6.
Then, AZ-1350 (manufactured by Hoechst) is applied to the silicon nitride insulating layer 5 as the photoresist 10 so that the film thickness becomes 1 μm. After pre-baking at 80 ° C. for 30 minutes, the wafer is exposed with a mask.
The photoresist 10 after development and rinsing has a slightly tapered shape as shown in FIG. Next, when reactive ion etching (RIE) is performed using the photoresist 10 as an etching mask and CF ₄ —O ₂ gas, the silicon nitride insulating layer 5 is selectively etched.

When the photoresist 10 is removed after the etching is finished, a groove narrower than the opening of the photoresist 10 is formed as shown in FIG. That is, a channel length shorter than that of a pattern that can be formed by a mask aligner can be realized. At this time, the width of the bottom of the groove is 1 μm, and the thickness of the silicon nitride insulating layer 5 at the bottom of the groove is 300 nm. Next, an amorphous silicon active layer 4 (thickness 10 nm at the bottom of the groove) and a resin 20 (thickness 1 μm at the bottom of the groove) are formed so as to cover the silicon nitride insulating layer 5 and prebaked at 80 ° C. at 30 ° C. After performing the heat treatment for a minute, as shown in FIG. 6D, the resin 20 is etched using Ar gas and the amorphous silicon active layer 4 is etched using CF ₄ —O ₂ gas.

Since the resin 20 at the bottom of the groove is thicker than the other portions, after etching, the resin 20 remains only in the region at the bottom of the groove as shown in FIG. When an Al electrode is deposited so as to cover the resin 20 and lift-off is performed, the source electrode 2 and the drain electrode 3 are formed as shown in FIG.
Thereafter, as shown in FIG. 6G, a photoresist 10 is formed so as to cover the source electrode 2 and the drain electrode 3 inside the groove, and the source electrode 2 and the drain in the region where the photoresist 10 is not formed. When the electrode 3 is removed, the structure of FIG. 5 is formed as shown in FIG.
The material system is not limited to the above, and a semiconductor such as polysilicon or GaAs or an organic layer may be used as the active layer 4, and the electrode may be selected according to the active layer. Furthermore, the insulating layer 5 is not limited to silicon nitride, and may be anything as long as it satisfies the specifications.

FIG. 7 is a diagram showing current-voltage characteristics of the field-effect transistor prototyped by the manufacturing process of FIG. 6, in which (a) is the relationship between the drain current and the drain voltage (the parameter is the gate voltage VG), (B) shows the relationship between the drain current and the gate voltage (the parameter is the drain voltage VD). The channel width is 10 μm.
As shown in FIG. 7A, as the drain voltage increases, the drain current tends to saturate, indicating typical field effect transistor characteristics. As shown in FIG. 7B, when the drain voltage VD is 10 V, the ratio of the drain current when the gate voltage is 10 V and 0 V, that is, the on / off ratio is 6.98 × 10 ^8. It can be seen that the on / off ratio required for driving the display device is larger than 10 ⁶ and satisfies the specifications.

Next, the cutoff frequency will be described.
In the structure of FIG. 5, the source electrode 2 and the drain electrode 3 are formed on the slope of the groove. Therefore, the gate-source capacitance and the gate-drain capacitance are smaller and the cutoff frequency is larger than in the conventional example of FIG. For example, the cut-off frequency when the source electrode and the drain electrode overlap with the gate electrode by 1 μm is 3.16 MHz in the conventional example of FIG. 9, but is improved to 4.51 MHz in the structure of FIG. As a result, high-speed operation can be achieved.
Therefore, according to the present embodiment, it is possible to obtain both a high on / off ratio and a high-speed operation required when driving a display device such as a liquid crystal.

[Example 4]
The fourth embodiment of the present invention applies the above-described configuration of the present invention, and a specific configuration thereof will be described with reference to the drawings.
FIG. 8 is a cross-sectional view schematically showing a manufacturing process of the field effect transistor in this embodiment of FIG. 5 described above. In FIG. 8, the same components as those in FIG.

Next, a manufacturing process of the field effect transistor of this example will be described with reference to FIG.
First, as shown in FIG. 8A, a silicon nitride insulating layer (thickness 1 μm) 5 is prepared. Then, AZ-1350 (manufactured by Hoechst) is applied to the silicon nitride insulating layer 5 as the photoresist 10 so that the film thickness becomes 1 μm. After pre-baking at 80 ° C. for 30 minutes, the wafer is exposed with a mask.
The photoresist 10 after development and rinsing has a slightly tapered shape as shown in FIG. Next, when reactive ion etching (RIE) is performed using the photoresist 10 as an etching mask and CF ₄ —O ₂ gas, the silicon nitride insulating layer 5 is selectively etched. When the photoresist 10 is removed after the etching is completed, the result is as shown in FIG. At this time, the width of the bottom of the groove is 1 μm, and the thickness of the silicon nitride insulating layer 5 at the bottom of the groove is 300 nm.

Next, an amorphous silicon active layer 4 (thickness at the bottom of the groove of 10 nm) and a negative photoresist RU-1100 (manufactured by Hitachi Chemical) 11 (thickness at the bottom of the groove of 1 μm) are successively formed and prebaked as 80 After heat treatment at 30 ° C. for 30 minutes, as shown in FIG. 8D, the negative photoresist 11 is exposed by irradiating ultraviolet light from the silicon nitride insulating layer 5 side.
The intensity of the ultraviolet light after propagating through the thick part of the silicon nitride insulating layer 5 is smaller than the intensity of the ultraviolet light after propagating through the thin part of the silicon nitride insulating layer 5, so that after development and rinsing, FIG. As shown in (e), the negative photoresist 11 remains only in the bottom region of the groove.

  Next, an Al electrode is deposited so as to cover the negative photoresist 11, and lift-off is performed. The source electrode 2 and the drain electrode 3 are formed on the slope of the groove through the active layer, and the insulating layer 5 and the substrate. Then, the structure shown in FIG. 8F is formed. Thereafter, as shown in FIG. 8G, a photoresist 10 is formed so as to cover the source electrode 2 and the drain electrode 3 inside the groove, and the source electrode 2 and the drain in the region where the photoresist 10 is not formed. When the electrode 3 is removed, the structure of FIG. 5 is formed as shown in FIG.

Note that a substrate that supports a wafer as appropriate may be used in the above steps. In addition, the material system is not limited to the above, and a semiconductor such as polysilicon or GaAs or an organic layer may be used as the active layer 4, and an electrode may be selected according to the active layer. Furthermore, the insulating layer 5 is not limited to silicon nitride, and may be anything as long as it satisfies the specifications.
According to the field effect transistor having the structure of FIG. 5 made in the manufacturing process of FIG. 8 of the present embodiment, the characteristics shown in FIG. 7 can be obtained in the same manner as that made in the manufacturing process of FIG.

As described above, according to each of the above-described embodiments, there is no problem in alignment, and a field effect transistor that satisfies both an on / off ratio of 10 ⁶ or more and high-speed operation even when the finished dimension deviates from the design dimension, and It is possible to provide a method for manufacturing a field effect transistor.

Sectional drawing which shows typically the structure of the field effect transistor in Example 1 and Example 2 of this invention. Sectional drawing which shows the manufacturing process of the field effect transistor in Example 1 of this invention. The figure which shows the current-voltage characteristic of the field effect transistor in Example 1 of this invention. Sectional drawing which shows the manufacturing process of the field effect transistor in Example 2 of this invention. Sectional drawing which shows typically the structure of the field effect transistor in Example 3 and Example 4 of this invention. It is sectional drawing which shows the manufacturing process of the field effect transistor in Example 3 of this invention. It is a figure which shows the current-voltage characteristic of the field effect transistor in Example 3 of this invention. It is sectional drawing which shows the manufacturing process of the field effect transistor in Example 4 of this invention. It is sectional drawing which shows the structure of the conventional field effect transistor. It is sectional drawing which shows the structure of the conventional field effect transistor.

Explanation of symbols

1: gate electrode 2: source electrode 3: drain electrode 4: active layer 5: insulating layer 6: substrate 10: photoresist 11: negative photoresist 20: resin

Claims (6)

In a field effect transistor having a source electrode and a drain electrode on an insulating layer and an active layer on a gate electrode,
An electric field having a reverse trapezoidal groove on the surface of the active layer, wherein a source electrode is formed on one inclined surface of the inverted trapezoidal groove and a drain electrode is formed on the other inclined surface. Effect transistor. In a field effect transistor having a source electrode and a drain electrode on an insulating layer and an active layer on a gate electrode,
The insulating layer has an inverted trapezoidal groove on the surface, the source electrode is provided on one slope of the inverted trapezoidal groove via the active layer, and the drain is provided on the other slope via the active layer. A field effect transistor, characterized in that an electrode is formed. In a method of manufacturing a field effect transistor having a source electrode and a drain electrode via an insulating layer and an active layer on a gate electrode,
Selectively removing a part of the active layer to form an inverted trapezoidal groove,
Forming a resin so as to cover the active layer including the concave groove;
Removing only the resin on the inclined surface of the inverted trapezoidal groove by ashing or etching the resin; and
Forming a source electrode and a drain electrode in a region of the slope portion from which the resin has been removed;
A method for manufacturing a field effect transistor, comprising: In a method of manufacturing a field effect transistor having a source electrode and a drain electrode via an insulating layer and an active layer on a gate electrode,
Selectively removing a part of the active layer to form an inverted trapezoidal groove,
Forming a photoresist so as to cover the active layer including the concave groove;
Removing the photoresist only on the inclined surface of the inverted trapezoidal concave groove by developing after exposing the photoresist from the opposite side of the surface coated with the photoresist; and
Forming a source electrode and a drain electrode in the region of the slope portion from which the photoresist has been removed;
A method for manufacturing a field effect transistor, comprising: In a method of manufacturing a field effect transistor having a source electrode and a drain electrode via an insulating layer and an active layer on a gate electrode,
Selectively removing a part of the insulating layer and forming an inverted trapezoidal groove,
Forming an active layer and a resin so as to cover the insulating layer including the concave groove;
Removing only the resin on the inclined surface of the inverted trapezoidal groove by ashing or etching the resin; and
Forming a source electrode and a drain electrode in a region of the slope portion from which the resin has been removed;
A method for manufacturing a field effect transistor, comprising: In a method of manufacturing a field effect transistor having a source electrode and a drain electrode via an insulating layer and an active layer on a gate electrode,
Selectively removing a part of the insulating layer to form an inverted trapezoidal concave groove;
Forming an active layer and a photoresist so as to cover the insulating layer including the concave groove;
Removing the photoresist only on the inclined surface of the inverted trapezoidal concave groove by developing after exposing the photoresist from the opposite side of the surface coated with the photoresist; and
Forming a source electrode and a drain electrode in the region of the slope portion from which the photoresist has been removed;
A method for manufacturing a field effect transistor, comprising:

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