JP2005339588A - Inspection method of semiconductor memory and semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection method of a semiconductor memory with which a defective state inspected quickly, in which a bit line and a cell plate are short-circuited. <P>SOLUTION: Short circuit of a bit line BL and a cell plate 4 is discriminated by measuring continuity between a pre-charge line BP and a cell plate line CP applying voltage to the cell plate 4 in the timing at which connection of the pre-charge line BP connected to an output side of a bit line equalize-transistor 6 and a bit line pre-charge power source 3 is turned off and a bit line equalize-signal ϕBLP connected to an input side of the bit line equalize-transistor 6 is turned on. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection method for detecting a defect in manufacturing a semiconductor memory device and a semiconductor memory device capable of carrying out this inspection method. The present invention relates to detecting a defect in which, after replacement with a redundant cell array, the defect affects a memory cell plate power supply and the memory does not operate normally.

  DRAM memory cells are miniaturized, memory cell access transistors and bit line contacts are extremely close to each other, and the bit line placement method (CUB) has a bit line wired on a memory cell plate which is a common electrode of a cell capacitor. After opening a window in a part of the memory cell plate, a contact between the bit line and the access transistor of the memory cell is formed.

For this reason, a short circuit or a leak between the memory cell plate and the bit line is likely to occur due to poor contact formation or the like.
FIG. 11 shows a basic array block of a DRAM found in (Patent Document 1).

  1 is a sense amplifier, 2 is a cell plate power supply (VCP), 3 is a bit line precharge power supply (VBP), 4 is a cell plate line, 5 is a memory cell, 6 is a bit line equalizing transistor, and BL and / BL are bit lines A pair, WL is a word line, φBLP is a bit line equalize signal, and Ys is a column selection line.

  In FIG. 11, the cell plate 4 of the basic array block is connected to the cell plate line CP connected to the output of the cell plate power supply (VCP) 2 and connected to the output of the bit line precharge power supply (VBP) 3. The bit line BP of the basic array block is connected to the precharge line BP. Further, an example in which the bit line BL and the cell plate 4 are short-circuited by the resistor R is given, and the short-circuited bit line BL becomes defective.

Finally, the basic array block having the defective bit line BL is found in the inspection process and replaced with the redundant bit line, and is compensated so that all the memory cells operate normally.
Conventionally, in the inspection method in this inspection process, specific data is written in the basic array block of the entire DRAM, and after reading this, the defective bit is specified by comparing with the written data.

Even if a basic array block having a defective bit line is replaced with a redundant bit line, the defective bit line remains in a short state.
Normally, the voltage _{V CP} of the cell plate line CP, 1/2 of the power supply voltage from the relationship of the electric field relaxation of the cell capacitor (1 / 2VDD) is given. The bit line precharge voltage (V _BP ) is also supplied with the ½ power supply voltage (½ VDD) as the reference voltage of the sense amplifier 1.

  Therefore, even if the short bit line is present, there is no problem when the DRAM is in a precharge (standby) state. However, when the DRAM is activated and a sense amplifier having this short circuit is activated, the sense amplifier is activated. The bit line BL is driven to a high level (VDD) or a low level (VSS) by the amplifier 1.

As a result, the cell plate 4 cannot maintain the 1/2 power supply voltage (1 / 2VDD), and an unstable phenomenon appears that is somewhat higher or lower than the 1/2 power supply voltage.
Then, since the cell plate is connected to other memory cells, the cell plate potential of the entire chip changes from a desired value due to leakage between the defective bit line and the cell plate, and the defective bit line is Replacing with redundant bit lines may not be good. Moreover, such defects due to cell plate voltage fluctuations due to leakage between defective bit lines and cell plates (defects appearing in memory cells other than defective bit lines) are caused by a long cycle when the cell plate potential changes gradually due to leakage.・ It was difficult to detect unless special inspections such as reading after page mode were performed.

This will be described in more detail.
As described above, the phenomenon in which the voltage of the cell plate 4 fluctuates due to a short circuit is caused by a decrease in the potential of the cell plate line when accessing the same word line in a long cycle such as a page mode in a write cycle as shown in FIG. Since the accumulated charge amount of the memory cell storing the L level is reduced, the operation is unstable due to a change in the access state of the memory such as a failure in a normal read cycle.

Therefore, in this (Patent Document 1), the fuse Fu is inserted into the cell plate 4 corresponding to each bit line pair, and the leakage path between the bit line BL and the cell plate 4 is removed by cutting the fuse Fu. It is configured.
JP-A-10-208497

  The cell plate line CP is a common electrode for the entire DRAM, and has a large capacitance of several thousand picofarads. The sense amplifier 1 connected to the short-circuited bit line BL is driven to change the voltage several times. The bit line BL that takes 10 microseconds to several milliseconds and has a short circuit is a pattern defect in manufacturing such as dust, and is randomly generated.

For this reason, the DRAM inspection that determines whether the short-circuit defect affects other normal memory cells and determines whether the entire DRAM is non-defective or defective has a problem that requires an enormous amount of time.
Further, in the technique of Patent Document 1, since a fuse Fu must be provided for each bit line pair BL, / BL, the chip area becomes large and is not suitable for practical use.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for inspecting a semiconductor memory device that can quickly determine a basic array block in which a short circuit defect has occurred and complete a non-defective / defective inspection of the entire DRAM in a shorter time than before.

  It is another object of the present invention to provide a semiconductor memory device having a configuration capable of avoiding a situation in which even if a short circuit failure occurs in a part of bit lines, a cell plate power supply of a basic array block to which the bit line belongs falls to cause an operation failure. And

  The inspection method for a semiconductor memory device according to the present invention includes a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. When testing a semiconductor memory device that reads data written in the memory cell through a sense amplifier, the connection between the precharge line connected to the bit line equalizing transistor and the bit line precharge power supply is turned off. Measuring a continuity between the precharge line and a cell plate line for applying a voltage to the cell plate at a timing when the bit line equalizing transistor is turned on to determine a short circuit between the bit line and the cell plate. It is characterized by.

  According to another aspect of the present invention, there is provided a semiconductor memory device inspection method comprising: a memory cell connected between a bit line and a cell plate; and a bit line precharge power source connected to the bit line via a bit line equalizing transistor. When inspecting a semiconductor memory device that precharges and reads out data written in the memory cell via a sense amplifier, connection between a cell plate line for applying a voltage of a cell plate power source to the cell plate and the cell plate power source And measuring the continuity between the reference potential of the bit line precharge power supply and the cell plate line at the timing when the bit line equalizing transistor is turned on to determine whether the bit line and the cell plate are short-circuited. Features.

  The semiconductor memory device of the present invention has a memory cell connected between a bit line and a cell plate, and precharges the bit line by a bit line precharge power source connected via a bit line equalizing transistor, A semiconductor memory device that reads data written in a memory cell via a sense amplifier, and controls a connection between a cell plate line that applies a voltage of a cell plate power source to the cell plate and the cell plate power source. A switch, a second switch for controlling connection between the bit line precharge power source and a precharge line for applying a voltage of the bit line precharge power source to the bit line via the bit line equalizing transistor; A first external connection terminal and a second switch connected to a connection point between the switch of the cell plate and the cell plate line. Wherein a pitch, characterized in that a second external connection terminal connected to a connection point between the precharge line.

  The semiconductor memory device of the present invention has a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. A semiconductor memory device for reading out data written in the memory cell via a sense amplifier, and controls connection between a cell plate line for applying a voltage of a cell plate power source to the cell plate and the cell plate power source. 1 switch, and a first external connection terminal connected to a connection point between the first switch and the cell plate line.

  The semiconductor memory device of the present invention has a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. A semiconductor memory device for reading data written in the memory cell through a sense amplifier, comprising: a cell plate line that applies a voltage of the bit line precharge power source to the cell plate; and a bit line precharge power source. A first switch for controlling connection, and a second switch for controlling connection between the bit line precharge power source and a precharge line for applying a voltage of the bit line precharge power source to the output side of the bit line equalizing transistor And a first external connection connected to a connection point between the first switch and the cell plate line And children, characterized in that a second external connection terminal connected to a connection point between said precharge line and the second switch.

  The semiconductor memory device of the present invention has a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. A semiconductor memory device for reading data written in the memory cell through a sense amplifier, comprising: a cell plate line that applies a voltage of the bit line precharge power source to the cell plate; and a bit line precharge power source. A first switch for controlling connection and a first external connection terminal connected to a connection point between the first switch and the cell plate line are provided.

  The semiconductor memory device of the present invention has a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. A semiconductor memory device in which layout portions of a plurality of basic array blocks for reading out data written in the memory cells via a sense amplifier are arranged in parallel on a semiconductor chip, wherein the bit line precharge power source is provided on the cell plate. A cell plate line for applying a voltage of the above and a precharge line for applying a voltage of the bit line precharge power source to the output side of the bit line equalizing transistor are drawn out from the basic array block, respectively, outside the layout unit, and Cell plate power supply for applying voltage to cell plate lines Connected, characterized in that said precharge line connected to said bit line precharge power.

  The semiconductor memory device of the present invention has a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. A semiconductor memory device in which layout portions of a plurality of basic array blocks for reading out data written in the memory cells via a sense amplifier are arranged in parallel on a semiconductor chip, wherein the bit line precharge power source is provided on the cell plate. A cell plate line for applying a voltage of the above and a precharge line for applying a voltage of the bit line precharge power source to the output side of the bit line equalizing transistor are drawn out from the basic array block, respectively, outside the layout unit, and Cell plate power supply for applying voltage to cell plate lines Connected via a first switch, connected the precharge line to the bit line precharge power supply via a second switch, and connected to a connection point between the cell plate line and the first switch. And an external connection terminal connected to a connection point between the precharge line and the second switch.

  The semiconductor memory device of the present invention has a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. A semiconductor memory device in which layout portions of a plurality of basic array blocks for reading out data written in the memory cells via a sense amplifier are arranged in parallel on a semiconductor chip, wherein the bit line precharge power source is provided on the cell plate. A cell plate line for applying a voltage of the above and a precharge line for applying a voltage of the bit line precharge power source to the output side of the bit line equalizing transistor are drawn out from the basic array block, respectively, outside the layout unit, and Cell plate power supply for applying voltage to cell plate lines An external connection terminal connected to the connection point between the cell plate line and the first switch is provided via the first switch, the precharge line connected to the bit line precharge power source It is characterized by that.

The semiconductor memory device according to the present invention is characterized in that the first switch is connected to a cell plate power source via a fuse.
In the semiconductor memory device of the present invention, power is supplied to the cell plate line from a global wiring connected to a cell plate power supply, and the bit line precharge power supply is supplied from a global wiring connected to the bit line precharge power supply. It is characterized by being fed.

  The semiconductor memory device of the present invention has a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. A semiconductor memory device for reading data written in the memory cell through a sense amplifier, comprising: a cell plate line that applies a voltage of the bit line precharge power source to the cell plate; and a bit line precharge power source. A first switch for controlling connection, and a second switch for controlling connection between the bit line precharge power source and a precharge line for applying a voltage of the bit line precharge power source to the output side of the bit line equalizing transistor And is provided.

  The inspection method for a semiconductor memory device according to the present invention includes a memory cell connected between a bit line and a cell plate, and the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor. When testing a semiconductor memory device that reads data written in the memory cell through a sense amplifier, the cell plate line for applying a voltage to the cell plate and a cell plate power supply are turned off, and the cell A voltage different from a voltage applied to a precharge line connected to the bit line equalizing transistor is applied to the plate line, and data of the memory cell is read to determine a short circuit between the bit line and the cell plate line. It is characterized by that.

  In the semiconductor memory device inspection method of the present invention, the voltage of the word line connected to the gate of the access transistor of the memory cell is longer than that during normal read operation after transitioning to the voltage level for turning on the access transistor. After waiting for a time, the sense amplifier is activated.

  According to the semiconductor memory device inspection method and semiconductor memory device of the present invention, leaks occurring in the cell plate and the bit line can be quickly detected and removed, so that a normal write operation and a read operation are ensured, and a defective product flows out. Can be prevented.

The semiconductor memory device inspection method of the present invention will be described below based on specific embodiments. In addition, the same code | symbol is attached | subjected and demonstrated to the same thing as the structural requirement shown in the prior art example of FIG.
(Embodiment 1)
FIG. 1 shows a semiconductor memory device that implements the inspection method of the present invention and a connection state during the inspection.

  In the basic array block of this DRAM, the first external connection terminal 7 connected to the cell plate line CP and the second external connection terminal 8 connected to the precharge line BP shown in the conventional example are added. Yes. Further, a first switch SW1 is provided between the connection point between the cell plate line CP and the first external connection terminal 7 and the output of the cell plate power supply (VCP) 2. A second switch SW2 is provided between the connection point between the precharge line BP and the second external connection terminal 8 and the output of the bit line precharge power supply (VBP) 3. The first and second external connection terminals 7 and 8 are provided on a semiconductor chip 9 in which a DRAM is constructed.

  The layout in the semiconductor chip 9 is configured by laying out cell plate lines CP and precharge lines BP so as to penetrate through the layout portions of a plurality of basic array blocks.

  In a state other than the inspection time, the first and second switches SW1 and SW2 are in the on state, and the output of the cell plate power supply (VCP) 2 is energized to the cell plate line CP, and the bit line precharge power supply (VBP) 3 Is supplied to the precharge line BP.

  At the time of inspection, the first and second switches SW1 and SW2 are switched to the OFF state by the switching signals S1 and S2, and the voltage source 10 and current detecting means are used between the first and second external connection terminals 7 and 8. Then, the ammeter 11 is connected (generally, an LSI tester or the like is used), and the bit line equalize signal φBLP is set to the H level.

  If the bit line BL and the cell plate 4 are short-circuited by the resistor R, the voltage source 10 to the second external connection terminal 8, the bit line equalize transistor 6, the bit lines BL, / BL, the resistor R Through the loop of the cell plate 4, the cell plate line CP, the first external connection terminal 7, and the voltage source 10, a larger current than normal flows through the ammeter 11. Therefore, it can be determined whether or not the cell plate 4 is short-circuited.

Thus, according to the inspection method of (Embodiment 1) of the present invention, the presence / absence of a short circuit between the bit line and the cell plate can be rapidly inspected.
(Embodiment 2)
FIG. 2 shows a semiconductor memory device according to (Embodiment 2) of the present invention.

The layout of the semiconductor chip 9 in (Embodiment 1) is that a cell plate line CP and a precharge line BP are arranged in a plurality of basic array block layout portions 12 ₁ , 12 ₂ ,. In this (Embodiment 2), the cell plate line CPg and the precharge line BPg are arranged in a plurality of basic array block layout portions 12 ₁ , 12 ₂ ,. ..., arranged outside 12n. Furthermore, cell plate line CPg and precharge line BPg are formed of global wiring that is thicker than cell plate line CP and precharge line BP in the first embodiment.

  The cell plate line CP in each basic array block is wired to the cell plate line CPg via the first switch SW1 and the fuse Fu. The precharge line BP in each basic array block is wired to the precharge line BPg via the second switch SW2.

Further, the semiconductor chip 9 includes first external connection terminals 7 ₁ , 7 ₂ ,... 7n connected to a connection point between the cell plate line CP and the first switch SW1 in each basic array block. , the external connection terminals _81, 82 pre-charge line BP and the second connected to a connection point between the second switch SW2 in each basic array _blocks, · · · 8n are provided.

  In a state other than the inspection time, the first and second switches SW1 and SW2 connected to any of the basic array blocks are in an on state, and the output of the cell plate power supply (VCP) 2 is energized to the cell plate line CP. The output of the bit line precharge power supply (VBP) 3 is energized to the precharge line BP.

During inspection of the layout section 12 of _the basic array block, first connected to the basic array block layout section 12 _1, the switching by the switching signal S in the off-state second switch SW1, SW2, first, second In the same manner as in the first embodiment, the voltage source 10 and the ammeter 11 are connected between the external connection terminals 7 ₁ and 8 ₁ and the bit line equalize signal φBLP is set to the H level.

If the bit line BL and the cell plate 4 are short-circuited by the resistor R, the voltage source 10 to the second external connection terminal 8 ₁ , the bit line equalize transistor 6, the bit lines BL, / BL, the resistor A current larger than that in the normal state flows through the ammeter 11 through the loop of the cell plate 4, the cell plate line CP, the first external connection terminal 7 ₁ , and the voltage source 10 via R. Therefore, it can be determined whether or not the cell plate 4 is short-circuited. The inspection for the presence or absence of a short circuit in the cell plate 4 of the basic array block of the layout portions 12 ₂ ,.

  For the basic array block having a defective bit line that is found to be defective in this inspection, the fuse Fu contained in the basic array block having the defective bit line is replaced with a redundant bit line in a later process of the inspection. By disconnecting, the cell plate power supply (VCP) 2 is separated.

  Thus, according to (Embodiment 2) of the present invention, not only can inspection be performed quickly, but a single fuse Fu is provided for each basic array block so that it can be disconnected when a defect occurs. The chip area can be slightly increased as in the conventional case where the fuse Fu is interposed for each cell plate 4 inside the basic array block, which is practical.

In this DRAM, since the cell plate line CPg and the precharge line BPg are arranged outside the layout portions 12 ₁ , 12 ₂ ,..., 12n, the same pattern is used for a plurality of basic array blocks. Can do. In addition, since the cell plate line CPg and the precharge line BPg are global wirings, the circuit impedance is low and stable operation can be expected.

Further, since the cell plate line CP and the precharge line BP, which are common electrodes of the capacitor of the memory cell 5, are connected in units of the layout units 12 ₁ , 12 ₂ ,..., 12n of the basic array block, they are not activated. No noise or fluctuations in the precharge power supply are applied to these blocks. Further, by arranging the layout portions 12 ₁ , 12 ₂ ,..., 12n of the basic array block, it is possible to cope with the increase in capacity, and thus the layout becomes easy.

(Embodiment 3)
FIG. 3 shows (Embodiment 3) of the present invention.
In (Embodiment 1) shown in FIG. 1, two external connection terminals 7 and 8 are provided in a semiconductor chip 9 for a single basic memory block, and the voltage source 10 and the external connection terminals 7 and 8 are connected between the external connection terminals 7 and 8. Although the ammeter 11 is connected and inspected, in this (Embodiment 3), one external connection terminal 7 is provided for inspection with respect to a single basic memory block, and the voltage source 10 is not required.

  Specifically, the external connection terminal G is a terminal provided on the semiconductor chip 9 and connected to the reference potential of the bit line precharge power supply (VBP) 3, and if the bit line BL and the cell plate 4 are connected to each other by resistance, When short-circuited by R, the bit line precharge power supply (VBP) 3 passes through the bit line equalizing transistor 6, the bit lines BL and / BL, and the resistor R, and the cell plate 4, cell plate line CP, A current larger than that in a normal state flows through the ammeter 11 in the loop of one external connection terminal 7. Therefore, it is possible to determine whether or not the cell plate 4 is short-circuited by checking the indicated value of the ammeter 11.

A basic array block having a defective bit line that is found to be defective by this inspection is replaced with a redundant bit line in a subsequent process of this inspection.
(Embodiment 4)
FIG. 4 shows a semiconductor memory device according to (Embodiment 4) of the present invention.

In this (Embodiment 4), the basic configuration shown in FIG. 3 is expanded as the entire basic configuration shown in FIG. 1 is expanded as shown in FIG. Is.
The layout of the semiconductor chip 9 in (Embodiment 3) is such that the cell plate line CP and the precharge line BP have a plurality of basic array block layout portions 12 ₁ , 12 ₂ ,. In this (Embodiment 4), the cell plate line CPg and the precharge line BPg are arranged in a plurality of basic array block layout portions 12 ₁ , 12 ₂ ,. ..., arranged outside 12n. Furthermore, cell plate line CPg and precharge line BPg are formed of global wiring that is thicker than cell plate line CP and precharge line BP in the third embodiment.

  The cell plate line CP in each basic array block is wired to the cell plate line CPg via the first switch SW1 and the fuse Fu. The precharge line BP in each basic array block is wired to the precharge line BPg.

Furthermore, the semiconductor chip 9 has first external connection terminals 7 ₁ , 7 ₂ ,... 7n connected to connection points between the cell plate line CP and the first switch SW1 in each basic array block. Is provided. The external connection terminal G is a terminal provided on the semiconductor chip 9 and connected to the reference potential of the bit line precharge power supply (VBP) 3.

  In a state other than the inspection time, the first switch SW1 connected to any basic array block is also in the on state, the output of the cell plate power supply (VCP) 2 is energized to the cell plate line CP, and the bit line precharge power supply. The output of (VBP) 3 is energized to the precharge line BP.

During inspection of the layout section 12 of _the basic array block, with switching by the switching signal S in the off state the first switch SW1 connected to the basic array block layout section 12 _1, the first external connection terminal ₇₁ and the external The ammeter 11 is connected between the connection terminals G in the same manner as in the third embodiment, and the bit line equalize signal φBLP is set to the H level.

If the bit line BL and the cell plate 4 are short-circuited by the resistor R, the bit line precharge power source (VBP) 3 passes through the bit line equalizing transistor 6, the bit lines BL, / BL, and the resistor R. In the loop of the cell plate 4, the cell plate line CP, and the first external connection terminal 7, a larger current flows through the ammeter 11 than normal. Therefore, it is possible to determine whether or not the cell plate 4 is short-circuited by checking the indicated value of the ammeter 11. The inspection for the presence or absence of a short circuit in the cell plate 4 of the basic array block of the layout portions 12 ₂ ,.

  A basic array block having a defective bit line that is found to be defective by this inspection is replaced with a redundant bit line in a later process of this inspection, and the basic array block having the defective bit line cuts the fuse Fu. Is separated from the cell plate power supply (VCP) 2.

  Thus, according to the (Embodiment 4) of the present invention, not only can the inspection be performed quickly, but a single fuse Fu is provided for each basic array block so that it can be disconnected when a defect occurs. The chip area can be slightly increased as in the conventional case where the fuse Fu is interposed for each cell plate 4 inside the basic array block, which is practical.

In this DRAM, since the cell plate line CPg and the precharge line BPg are arranged outside the layout portions 12 ₁ , 12 ₂ ,..., 12n, the same pattern is used for a plurality of basic array blocks. Can do. In addition, since the cell plate line CPg and the precharge line BPg are global wirings, the circuit impedance is low and stable operation can be expected.

(Embodiment 5)
FIG. 5 shows a semiconductor memory device according to (Embodiment 5) of the present invention.
In (Embodiment 1) shown in FIG. 1, the circuit is configured by using two power sources of the cell plate power source (VCP) 2 and the bit line precharge power source (VBP) 3, but the cell plate power source (VCP) ) 2 is a power supply circuit having a current capacity smaller than that of the bit line precharge power supply (VBP) 3, so that when the cell plate 4 is short-circuited, the output voltage of the cell plate power supply (VCP) 2 is lower than specified. In this (Embodiment 5), the cell plate line CP is connected to the second switch SW2 and the bit through the first switch SW1. The bit line precharge power supply (VBP) 3 is connected to the connection point with the output of the line precharge power supply (VBP) 3 and has a larger current capacity than the cell plate power supply (VCP) 2. It has been created. Others are the same as (Embodiment 1).

  Thus, in the same manner as in the first embodiment, at the time of inspection, the first and second switches SW1 and SW2 are turned off by the switching signals S1 and S2, and the first and second externals are switched. The voltage source 10 and the ammeter 11 are connected between the connection terminals 7 and 8, and the bit line equalize signal φBLP is set to the H level.

  If the bit line BL and the cell plate 4 are short-circuited by the resistor R, the voltage source 10 to the second external connection terminal 8, the bit line equalize transistor 6, the bit lines BL, / BL, the resistor R , A larger current than normal flows through the ammeter 11 in the loop of the cell plate 4, the cell plate line CP, the first external connection terminal 7, and the voltage source 10. Therefore, it can be determined whether or not the cell plate 4 is short-circuited.

  In the (Embodiment 1), a defective basic array block may affect the voltage of the cell plate line CP. Therefore, in (Embodiment 2), a single fuse Fu is provided for each basic array block. In this (Embodiment 5), power is supplied from the bit line precharge power supply (VBP) 3 to the cell plate line CP, so that it is connected to another normal bit line. Even when the read memory cell is read, it is not affected, and a reliable operation can be expected without providing the fuse Fu.

(Embodiment 6)
FIG. 6 shows a semiconductor memory device according to (Embodiment 6) of the present invention.
In (Embodiment 3) shown in FIG. 3, the circuit is configured using two power sources, ie, the cell plate power source (VCP) 2 and the bit line precharge power source (VBP) 3, but the cell plate power source (VCP) ) 2 is a power supply circuit having a current capacity smaller than that of the bit line precharge power supply (VBP) 3, so that when the cell plate 4 is short-circuited, the output voltage of the cell plate power supply (VCP) 2 is lower than specified. In this (Embodiment 6), the cell plate line CP is connected to the bit line precharge power supply (VBP) via the first switch SW1. ) Connected to the output of 3, the current capacity larger than that of the cell plate power supply (VCP) 2 is operated by the bit line precharge power supply (VBP) 3. Others are the same as (Embodiment 3).

  Since it is configured in this manner, similarly to (Embodiment 3), at the time of inspection, the first switch SW1 is switched to the OFF state by the switching signal S1, and between the first external connection terminal 7 and the external connection terminal G. The ammeter 11 is connected to the bit line, and the bit line equalize signal φBLP is set to the H level to determine whether or not the cell plate 4 is short-circuited.

  In (Embodiment 3), a defective basic array block may affect the voltage of the cell plate line CP. Therefore, in (Embodiment 4), a single fuse Fu is provided for each basic array block. In this (Embodiment 6), power is supplied from the bit line precharge power supply (VBP) 3 to the cell plate line CP, so that it is connected to another normal bit line. The memory cell is not affected at the time of reading, and a reliable operation can be expected without providing the fuse Fu.

(Embodiment 7)
7 is obtained by removing the first and second switches SW1 and SW2 and the first and second external connection terminals 7 and 8 from the fifth embodiment shown in FIG. In this (Embodiment 7), the current capacity larger than that of the cell plate power supply (VCP) 2 is supplied from the bit line precharge power supply (VBP) 3 in this (Embodiment 7) as compared with the DRAM described above. Therefore, the memory cell connected to another normal bit line is not affected at the time of reading, and a reliable operation can be expected without providing the fuse Fu.

(Embodiment 8)
FIG. 8 shows a semiconductor memory device according to (Embodiment 8) of the present invention.
The precharge line BP and the cell plate CP in each basic array block are wired to the precharge line BPg.

Thus, since power is supplied to each basic array block from the precharge line BPg of the global wiring, stable operation can be expected.
(Embodiment 9)
The following method can be used to inspect the presence or absence of a short between the bit line and the cell plate using the circuit of FIG. The switch SW1 is turned off, and a voltage higher than the bit line precharge voltage VBP is applied as the cell plate voltage VCP from the external connection terminal. In this state, if there is a leak due to the resistance R between the bit line BL and the cell plate 4, the memory cell is connected to the bit line BL by activation of the word line WL, and the bit line BL corresponds to the memory cell data. After the slight potential change has occurred, the potential of the bit line BL gradually rises due to leakage by the resistor R. Therefore, even when the bit line potential is initially lower than the precharge level due to zero reading, it gradually increases. If data is read by activating the sense amplifier after rising up to a malfunction, erroneous data is read. That is, if there is a leak due to a short between the bit line and the cell plate, erroneous data is read out by such a method, so that it is possible to check whether there is a short.

  If this method is used to inspect a short between the bit line and the cell plate, the bit line / cell plate is written in a shorter time than the inspection in which the long cycle write in the page mode described above is executed and then the read is performed. It is possible to detect a defect due to a short circuit.

  Note that the ammeter 11 is not used when performing this inspection. Further, the voltage of the precharge line BP can be supplied from the external connection terminal 8 or can be supplied from the precharge power supply VBP on the chip via the switch SW2.

  FIGS. 9 and 10 show the timing and circuit in the case of delaying the activation timing of the sense amplifier in order to reliably detect a leak due to a short between the bit line and the cell plate in (Embodiment 9) of the present invention. Indicates.

  FIG. 9 is a timing chart of the activation signal SS of the sense amplifier 1 at the normal time and at the time of inspection. After the voltage of the word line WL, which is the gate of the access transistor of the memory cell 5, transitions to a voltage level that turns on the access transistor, the sense amplifier 1 is activated after waiting for a longer time than in the normal read operation.

  As a result, when a short circuit occurs between the bit line BL and the cell plate 4, the bit line potential rises above the precharge potential even if a slight leak occurs or the L level is written in the memory cell 5. Can be detected as a defective bit.

FIG. 10 shows a specific generation circuit for the activation signal SS of the sense amplifier 1.
Here, the resistor 13 formed in the same manner as the wiring pattern used for the gate of the access transistor of the memory cell 5 and the cell capacitor of the memory cell 5 are formed in the output of the inverter 13 and the inverter 13. This is realized by a delay circuit composed of a plurality of capacitors 15 and an inverter 16.

  As a result, variations in the wiring pattern and the cell capacitor during manufacturing can be absorbed, and the delay time can be made relatively equal. Needless to say, this circuit may be used as a normal delay means.

  The method for inspecting a semiconductor memory device according to the present invention has an effect of detecting or eliminating leaks occurring in the cell plate and the bit line, and is useful as an inspection process for the semiconductor memory device.

1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. Configuration diagram of a semiconductor memory device according to a second embodiment of the present invention Configuration diagram of a semiconductor memory device according to a third embodiment of the present invention. Configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention. Configuration diagram of a semiconductor memory device according to a fifth embodiment of the present invention Configuration diagram of a semiconductor memory device according to a sixth embodiment of the present invention. Configuration diagram of a semiconductor memory device according to a seventh embodiment of the present invention Configuration diagram of a semiconductor memory device according to an eighth embodiment of the present invention Timing diagram of Embodiment 9 of the present invention Circuit diagram of the embodiment Circuit diagram of conventional semiconductor memory device Timing chart of failure in conventional semiconductor memory devices

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sense amplifier 2 Cell plate power supply 3 Bit line precharge power supply 4 Cell plate 5 Memory cell 6 Bit line equalizing transistor 7 First external connection terminal 8 Second external connection terminal 9 Semiconductor chip 10 Voltage source 11 Ammeter (Current detection means)
12 ₁ , 12 ₂ ,..., 12n Layout section of basic array block BL bit line BP precharge line CP cell plate line φBLP bit line equalize signal SW1 first switch SW2 second switch Fu fuse CPg global wiring cell Plate line BPg Global wiring precharge line SS Sense amplifier 1 activation signal SS

Claims (14)

A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is When inspecting a semiconductor memory device read through a sense amplifier,
Turning off the connection between the precharge line connected to the bit line equalize transistor and the bit line precharge power supply;
A semiconductor memory device for determining a short circuit between the bit line and the cell plate by measuring conduction between the precharge line and the cell plate line for applying a voltage to the cell plate at a timing when the bit line equalizing transistor is turned on. Inspection method. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is When inspecting a semiconductor memory device read through a sense amplifier,
Turn off the connection between the cell plate power supply and the cell plate power supply for applying the voltage of the cell plate power supply to the cell plate,
Method for inspecting semiconductor memory device for measuring short circuit between bit line and cell plate by measuring continuity between reference potential of bit line precharge power supply and cell plate line at timing when bit line equalizing transistor is turned on . A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is A semiconductor memory device that reads through a sense amplifier,
A first switch for controlling connection between a cell plate line for applying a voltage of a cell plate power source to the cell plate and the cell plate power source;
A second switch for controlling connection between the bit line precharge power source and a precharge line for applying a voltage of the bit line precharge power source to the bit line via the bit line equalizing transistor;
A first external connection terminal connected to a connection point between the first switch and the cell plate line; and a second external connection terminal connected to a connection point between the second switch and the precharge line. Provided semiconductor memory device. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is A semiconductor memory device that reads through a sense amplifier,
A cell plate line for applying a cell plate power supply voltage to the cell plate; a first switch for controlling connection between the cell plate power supply; and a first switch connected to a connection point between the first switch and the cell plate line. A semiconductor memory device provided with one external connection terminal. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is A semiconductor memory device that reads through a sense amplifier,
A first switch for controlling connection between a cell plate line for applying a voltage of the bit line precharge power source to the cell plate and the bit line precharge power source;
A second switch for controlling connection between a precharge line for applying a voltage of the bit line precharge power source to an output side of the bit line equalize transistor and the bit line precharge power source;
A first external connection terminal connected to a connection point between the first switch and the cell plate line;
A semiconductor memory device provided with a second external connection terminal connected to a connection point between a second switch and the precharge line. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is A semiconductor memory device that reads through a sense amplifier,
A first switch for controlling connection between the cell plate line and the bit line precharge power source for applying a voltage of the bit line precharge power source to the cell plate;
A semiconductor memory device provided with a first external connection terminal connected to a connection point between a first switch and the cell plate line. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is A semiconductor storage device in which a layout portion of a plurality of basic array blocks read out via a sense amplifier is arranged in parallel on a semiconductor chip,
A cell plate line for applying the voltage of the bit line precharge power source to the cell plate and a precharge line for applying the voltage of the bit line precharge power source to the output side of the bit line equalizing transistor are respectively provided from the basic array block. A semiconductor memory device that is pulled out and connected to a cell plate power source for applying a voltage to the cell plate line outside the layout unit, and the precharge line is connected to the bit line precharge power source. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is A semiconductor storage device in which a layout portion of a plurality of basic array blocks read out via a sense amplifier is arranged in parallel on a semiconductor chip,
A cell plate line for applying the voltage of the bit line precharge power source to the cell plate and a precharge line for applying the voltage of the bit line precharge power source to the output side of the bit line equalizing transistor are respectively provided from the basic array block. Pull out and connect to a cell plate power source for applying a voltage to the cell plate line outside the layout unit via a first switch, and connect the precharge line to the bit line precharge power source via a second switch. Connect
And an external connection terminal connected to a connection point between the cell plate line and the first switch;
A semiconductor memory device provided with an external connection terminal connected to a connection point between the precharge line and the second switch. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is A semiconductor storage device in which a layout portion of a plurality of basic array blocks read out via a sense amplifier is arranged in parallel on a semiconductor chip,
A cell plate line for applying the voltage of the bit line precharge power source to the cell plate and a precharge line for applying the voltage of the bit line precharge power source to the output side of the bit line equalizing transistor are respectively provided from the basic array block. Pull out and connect to a cell plate power source for applying a voltage to the cell plate line via a first switch outside the layout unit, connect the precharge line to the bit line precharge power source, and A semiconductor memory device provided with an external connection terminal connected to a connection point between a cell plate line and a first switch. 10. The semiconductor memory device according to claim 8, wherein the first switch is connected to the cell plate power supply via a fuse. The power supply from the global wiring connected to the cell plate power supply to the cell plate line, and the power supply from the global wiring connected to the bit line precharge power supply to the bit line precharge power supply. The semiconductor memory device according to claim 9. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is A semiconductor memory device that reads through a sense amplifier,
A first switch for controlling connection between a cell plate line for applying a voltage of the bit line precharge power source to the cell plate and the bit line precharge power source;
A semiconductor memory device comprising a precharge line for applying a voltage of the bit line precharge power supply and a second switch for controlling connection between the bit line precharge power supply on the output side of the bit line equalize transistor. A memory cell connected between a bit line and a cell plate, the bit line is precharged by a bit line precharge power source connected via a bit line equalizing transistor, and data written in the memory cell is When inspecting a semiconductor memory device read through a sense amplifier,
Turn off the connection between the cell plate line for applying a voltage to the cell plate and the cell plate power supply,
A voltage different from the voltage applied to the precharge line connected to the bit line equalizing transistor is applied to the cell plate line, and the bit line and the cell plate line are short-circuited by reading the data of the memory cell. A method for inspecting a semiconductor memory device. After transitioning the voltage of the word line connected to the gate of the access transistor of the memory cell to a voltage level for turning on the access transistor, the sense amplifier is activated after waiting for a longer time than in the normal read operation. 14. A method for inspecting a semiconductor memory device according to claim 13, wherein:

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