JP2005338916A - Lsi layout device, method therefor and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LSI layout device capable of performing distinction of each layer in a circuit layout pattern belonging to each circuit design, in pattern data wherein respective layers are composed by an including process between the plurality circuit designs. <P>SOLUTION: This LSI layout device has: a layout database storing the pattern data of the circuit layout pattern; an editing buffer storing the read pattern data; a design table provided in each the circuit design, storing design information showing the editing buffer storing the pattern data; a display table storing display information about the displayed circuit layout pattern; and a display part reading the layer of the circuit layout pattern from the editing buffer by the design information, and displaying the pattern data of each the layer. The LSI layout device imparts identification information in each layer unit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an LSI layout apparatus used when designing an LSI (Large Scale Integrated circuit), a layout method thereof, and a layout program.

Usually, when manufacturing an LSI, from the LSI specification determination to mass production, basic design based on the specification, circuit configuration description by RTL (Register Transfer Level) in the hardware description language, logic synthesis at the hardware description language level, A plurality of processes are performed in the order of logic verification of the synthesized circuit, layout pattern design for creating a mask pattern of the synthesized circuit, trial production using the created mask, mass production after trial production, testing of mass-produced products, and the like.
In an LSI manufacturing process, a plurality of elements constituting a circuit function are formed on a substrate such as silicon using the mask.
Further, in designing LSI, layout pattern design for forming an element structure is relatively automated and has reached a practical level.

Normally, in an automatic design tool, a layout pattern corresponding to a logic-synthesized circuit is prepared in advance as a layout database as circuit layout information.
Patent Documents 1 to 3 listed below describe LSI layout apparatuses that create the layout database described above and perform layout pattern design using this layout database.
JP 09-237839 A Japanese Patent Laid-Open No. 11-297836 JP 2000-314954 A

The layout database described above is composed of a set of layers according to a predetermined functional device, that is, a circuit layout pattern in a circuit design.
Here, when a single LSI is configured by combining a plurality of functional devices, for example, two types, two types of layout databases (for example, layer set A and layer set B) are used in order to connect them. ) Belonging to each layer must be simultaneously displayed on the display device.
In the conventional LSI layout apparatus, in the editing process, for example, the layer pattern data in the layer set A is read into the editing buffer, and then the layer pattern data in the layer set B is read in the editing buffer. The pattern data of the layer set B is overwritten on the pattern data of the layer set A, and the pattern data of the two layout sets are mixed.

That is, in the editing buffer, the pattern data of the layer set B is included in the layer set A.
Thereby, the layout pattern mixed in the editing buffer is displayed on the display device of the apparatus.
Here, the editing buffer is a storage unit that temporarily holds pattern data of each layer of the layout database to be edited when a layout pattern is edited on the display screen.

However, in the conventional LSI layout device, when the layers of the layout pattern have the same layer number, the pattern data of each layer of layer set A and layer set B will be mixed in the editing buffer. It becomes impossible to distinguish in data which layer set the mixed layout pattern belongs to.
Therefore, the conventional LSI layout apparatus has an undo function for canceling the work, but once it is separated from the layout database in the editing buffer in which the inclusion has been performed, to restore the original. I can't.

For this reason, in the conventional LSI layout device, the contents of the editing buffer are updated one after another when different layout sets are mistakenly included or an include is executed multiple times for an arbitrary layout set. As a result, there is a problem that the initial state cannot be restored and the editing process cannot be easily performed again.
The present invention has been made in view of such circumstances, and in the pattern data in which layers of a plurality of circuit designs are synthesized by an include process between a plurality of circuit designs, the pattern data of the layers belonging to each circuit design It is an object of the present invention to provide an LSI layout device, a layout method thereof, and a layout program.

  To achieve the above object, according to the present invention, when circuit layout patterns belonging to different circuit designs are used and an LSI layout pattern is designed, pattern data of each layer constituting the circuit layout pattern is displayed and edited. In an LSI layout apparatus, pattern data of each layer constituting the circuit layout pattern is displayed on a display database and a layout database (for example, layout database 11 in one embodiment) stored for each circuit design. An editing buffer for storing the circuit layout pattern read from the layout database (for example, the editing buffer 25 in one embodiment), and the circuit layout pattern stored for each circuit design. A design table (for example, the design table 24 in one embodiment) in which design information including address information of the diting buffer is stored, and display information corresponding to the display screen and indicating a circuit layout pattern to be displayed on the display screen are provided. With reference to the stored display table (for example, the display table 22 in one embodiment) and the display information, a layer of a predetermined circuit layout pattern is read from each editing buffer according to the design information, A display unit that displays pattern data on the display screen (for example, the display unit 4 in one embodiment), and stores each layer of the circuit layout pattern in the editing buffer. Indicates whether it is included The identification information is a LSI layout apparatus characterized by imparting to the respective layer units.

  The present invention is an LSI layout method for displaying and editing pattern data of each layer constituting the circuit layout pattern when designing the LSI layout pattern using circuit layout patterns belonging to different circuit designs, A storage process (for example, step S0 in one embodiment) in which pattern data of layers constituting a circuit layout pattern is stored in a layout database corresponding to each circuit design, and when displayed on a display screen, the layout database A buffer process (for example, steps S7 and S8 in one embodiment) for storing the circuit layout pattern to be read in the editing buffer, and the editing buffer provided for each circuit design and storing the circuit layout pattern A design table storage process (for example, steps S3 to S6 in one embodiment) for storing design information including address information of the circuit in the design table, and a circuit layout pattern corresponding to the display screen and displayed on the display screen Display table storage process for storing display information in a display table (for example, steps S9 to S14 in one embodiment), and referring to the display information, a layer of a predetermined circuit layout pattern is read from each editing buffer, A display process (for example, steps S17 and S18 in one embodiment) of reading out the design data and displaying the pattern data of each layer on the display screen. Each layer of the circuit layout pattern is stored in the editing buffer. Store That time, the identification information indicating whether included in any of the circuit design, a LSI layout method, which comprises applying to the respective layer units.

  In the present invention, when a circuit layout pattern belonging to a different circuit design is used and an LSI layout pattern is designed, LSI layout processing for displaying and editing pattern data of each layer constituting the circuit layout pattern is executed on a computer. And a storage process (for example, step S0 in one embodiment) for storing the pattern data of the layers constituting the circuit layout pattern in the layout database corresponding to each circuit design and displayed on the display screen. A buffer process (for example, steps S7 and S8 in one embodiment) for storing the circuit layout pattern read from the layout database in an editing buffer, and the circuit layout pattern provided for each circuit design. Corresponding to a design table storage process (for example, steps S3 to S6 in one embodiment) for storing design information including address information of the editing buffer stored in a design table, the display screen Display table storage processing for storing display information indicating a circuit layout pattern to be displayed in the display table (for example, steps S9 to S14 in one embodiment), and a layer of a predetermined circuit layout pattern with reference to the display information Is read out from each editing buffer according to the design information, and the pattern data of each layer is displayed on the display screen (for example, steps S17 and S18 in one embodiment). ,Previous When storing each layer of the circuit layout pattern, the identification information indicating whether included in any of the circuit design, a computer-executable LSI layout program characterized by imparting to the respective layer units.

With the above-described configuration, the LSI layout apparatus, method and program thereof according to the present invention provides identification information for each circuit design to each layer when other circuit layout patterns are included in an arbitrary circuit layout pattern. Therefore, even if each layer of the above arbitrary circuit layout pattern has the same layer number, it is written in different editing buffers, so even if it is displayed in a synthesized state, Since different circuit layout patterns are not synthesized by one editing buffer, the pattern data of each layer can be easily recognized for each circuit design.
Thereby, the LSI layout apparatus, method and program thereof according to the present invention refer to the identification information given to each layer when returning the editing result to the layout database, and each layer corresponding to each circuit design. Pattern data can be read from the editing buffer, and the pattern data of each layer can be written into the corresponding layout database, and the pattern data of a plurality of circuit designs can be combined and restored to the initial state as in the past. It is possible to prevent a destructive editing operation that cannot be performed on the layout database.

  In addition, the present invention provides a buffer header table (for example, an editor in one embodiment) provided corresponding to each design table and storing layer buffer information including a layer number indicating each layer and an address of an editing buffer. A display buffer table (corresponding to the display buffer table 21) and the display header table (for example, display layer information including the layer number and necessary for displaying each circuit layout pattern on the display screen) , And when displaying each layer on the display screen according to the display information of the display table, the pattern data of the layer corresponding to the layer number stored in the display header table The buffer Via Ddateburu an LSI layout and wherein the reading from the editing table.

The present invention provides a buffer header table storage process (for example, one implementation) that is provided corresponding to each design table and stores layer buffer information including a layer number indicating each layer and an address of an editing buffer in the buffer header table. And display information necessary for displaying each circuit layout pattern on the display screen, which is provided corresponding to the display table and includes the layer number, is stored in the display header table. Display header table storage process (for example, steps S13 and S14 in one embodiment), and when displaying each layer on the display screen according to the display information of the display table, the display header table stored in the display header table Layer number The pattern data of response to the layer, through the buffer header table is an LSI layout method, characterized in that read from the editing table.
With the above-described configuration, the LSI layout apparatus and method of the present invention can manage the layer editing buffer for each circuit layout pattern independently for each layout database and display screen by the above-described configuration. Regardless of the circuit layout pattern to which each layer belongs, it is possible to easily select a layer to be displayed on the display screen.

According to another aspect of the present invention, there is provided an LSI layout apparatus comprising a plurality of the display tables and providing a display header table corresponding to each display table.
With the configuration described above, the LSI layout device of the present invention can manage each display screen independently when displaying a plurality of display screens (windows) on the display of the device, and displays each display screen on each display screen. A layer to be displayed on the display screen can be easily selected regardless of the circuit layout pattern to which the layer belongs.

Also, the present invention is the LSI layout device characterized in that the identification information is represented by a predetermined character or number added to the layer number of each layer.
With the above-described configuration, the LSI layout apparatus of the present invention can easily add identification information for identifying a preset circuit design by OR operation or the like on the original layer number. It is possible to easily perform the determination processing of each layer in the editing buffer by a simple means.

  As described above, according to the present invention, when the pattern data of each layer in each circuit pattern read from the layout database is stored in the editing buffer, it is indicated which circuit design is included in each layer unit. Since an identification number is assigned, when returning the editing result to the layout database, the pattern data of each layer corresponding to each circuit design is read from the editing buffer by referring to the identification information given to each layer. The pattern data of each layer can be written in the layout database of the corresponding circuit design.

An LSI layout apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of the embodiment.
In this figure, the LSI layout device is composed of a main storage unit 1 and an LSI layout unit 6. The main storage unit 1 is provided with a plurality of layout databases 11 corresponding to each circuit design and storing circuit layout information including circuit layout patterns belonging to each circuit design.
Here, the circuit design is, for example, a circuit having a predetermined function that can be manufactured with the same processing dimensions in the manufacturing process, that is, is separately designed with a library of memory circuits and logic circuits having the same mask design rules and the like. Design information (for example, layout pattern information in each layout hierarchy (layer) of a hard macro and a soft macro).

The LSI layout unit 6 includes an auxiliary storage unit 2, a control unit 3, and a display unit 4.
The auxiliary storage unit 2 has storage areas such as an editing buffer header 21, a display header 23, a display table 22, a design table 24, an editing buffer 25, and the like. In each of these storage areas, when a circuit layout pattern belonging to a plurality of different circuit designs is used for each of the storage areas and these are combined to perform an editing operation of the circuit layout pattern of the LSI, the control unit 3 Management data for managing each circuit layout pattern, which is used when editing processing of each circuit layout pattern and display processing on the display unit 5, is stored.

The editing buffer 25 corresponds to each circuit layout pattern, is provided for each layer, and stores pattern data for each layer.
Here, the pattern data of each layer in the circuit layout pattern indicated by the design table 24 and the pattern data of the layer in each editing buffer 25 are associated by the editing buffer header 21 as shown in FIG. Yes.
That is, as shown in FIG. 2, the design table 24 includes the above-described editing buffer header address, the design name of this circuit design, the initial creator name, the last modified person name, the initial created date, the last modified date, It has design information such as the maximum number of layer layers and the entire memory use area.
Here, the editing buffer header address described in the design table 24 indicates the address of the editing buffer header 21 corresponding to each layer in the circuit layout pattern of the circuit design described in the design table 24.
The editing buffer header 21 stores layer buffer information corresponding to each layer of the circuit layout pattern read into the editing buffer 25 on a one-to-one basis.

Here, the circuit layout pattern is “poly”, “n-well”, “p-well”, “contact”, “diff p +”, “diff n +”, “via-1”, “via-2”, “ When the pattern data of each layer named “metal-2” and “metal-3” is configured, the above entry is assigned to each of these layers (a mask layer corresponding to each mask used for photolithography in the manufacturing process). There is a one-to-one correspondence, and the layer number is also linked (associated) with the layer name.
In this entry, as shown in FIG. 2, in the entry field, the design number indicating which circuit design belongs, the name of the layer, the layer number, and the pattern data of the layer corresponding to this entry are stored. It has layer buffer information such as the head address of the buffer 25.

The control unit 3 forms the design table 24 and the editing buffer header 21 when the circuit layout pattern read from the main storage unit 1 is written to the editing buffer 25 corresponding to each layer in each circuit layout pattern.
Further, when writing the layer number in each entry field of the editing buffer header 21, the control unit 3 uses a predetermined numerical value or a character identifier as identification information as to which circuit design the layer belongs to. To grant.
That is, as in the circuit designs A and B shown in FIG. 3, in the circuit layout pattern of the circuit design, the layout apparatus conventionally assigns each layer number in the layout pattern, and the same layer type is the same for the same layer type. Numbers are often used.

For example, when the same layer number “101” is used for both the circuit designs A and B as the layer number of the layer name “poly”, when the layout pattern is edited using the circuit designs A and B, the circuit number The circuit layout pattern of design A is read first, and then the circuit layout pattern of circuit design B is included in this circuit layout pattern.
Thereby, in the display screen, the pattern data of the same layer number of the layer number “101” in the circuit layout pattern of the circuit design A and the layer number “101” in the circuit layout pattern of the circuit design B are mixed. It becomes a state.

At this time, when writing each layer number in the entry field in the editing buffer header 21, the control unit 3 performs a logical OR operation (OR operation) on the layer number as an identifier as described above. And a new layer identification number is generated, and this layer identification number is written in the entry field. Here, a predetermined numerical value or character to be ORed is an identifier for identifying the circuit design.
The predetermined numerical value as the identifier is a numerical value having a larger number of digits than the original layer number used in the layout database 11 in the main storage unit 1, and when OR operation is performed, each digit of the original layer number Those that do not change the numerical value facilitate management.
Also, a predetermined character as an identifier may be added after the least significant digit of the layer number (“101A”) or added above the most significant digit of the layer number (“A101”) by OR operation. good.
Further, the control unit 3 writes the correspondence relationship between the design name or design number of the circuit design and the identifier added to this circuit design in the correspondence table 5 provided in the auxiliary storage unit 2.

Returning to FIG. 1, the display unit 4 generates a display screen (window) for each display table 22, refers to the display header 23 indicated in the display table 22 on each display screen, and displays the display header 23. The pattern data stored in one or a plurality of editing buffers 25 described is displayed.
The display table 22 is created for each display screen in the display unit 4 and, as shown in FIG. 4, includes the display header address described above and the name of the display screen (for example, the display screen 4-1 in FIG. 5). It has display information such as a display name, the initial creator of this display screen, the initial creation date, the last modification date, the maximum number of layers, and the entire memory use area. Here, each layer of the circuit layout pattern indicated by the display table 22 and a layer in the display screen unit in the display unit 4 are associated one-to-one by the display header 23 as shown in FIG.

That is, the display header address described in the display table 22 indicates the address of the display header 23 that manages the layer displayed in the corresponding display screen unit. The display header 23 stores an entry indicating display information in a one-to-one correspondence with each layer displayed on the display screen to be displayed.
As shown in FIG. 4, this entry includes not only the display header address described above but also a layer number indicating which layer, a display color indicating a color when displaying this layer, and a layout pattern in each entry field. The display pattern indicating the pattern, the display order indicating the display priority, the display enable indicating whether to perform display, the display coordinates indicating the display position of this layout pattern, and the rotation angle when displaying It has information such as display rotation.

Next, an operation example of the LSI layout apparatus according to the embodiment of the present invention is described with reference to FIGS. FIG. 5 is a conceptual diagram illustrating the relationship between the editing buffer header 21 and the display header 23 for each display screen when two different display screens are displayed on the display unit 4. FIG. 6 is a sequence diagram showing a flow of screen processing of the LSI layout apparatus.
Here, the circuit layout patterns of the circuit designs A and B are read from the layout database 11 of different devices in the main storage unit 1, and each of the circuit designs A and B is displayed on the two display screens displayed on the display unit 4. A case where layers are combined and displayed for each display screen will be described as an operation example. Further, the circuit design A is a memory device, and the circuit design B is a logic device.
In the main storage unit 1, a circuit design necessary for a desired LSI layout design is input from the outside by the user and stored in advance (step S0).

The user inputs a read command for performing a process of reading a circuit layout pattern in order to make the wiring of the circuit design A correspond to the wiring of the circuit design B and to perform a new device design by combining both.
As a result, the control unit 3 reads out the circuit design A to be edited and the circuit design B that includes the circuit design A from the layout database 11 of the main storage unit 1 (steps S1 and S2). ).
Then, the control unit 3 uses the read command to design the design name, initial creator name, last modifier name, initial creation date, final modification date, maximum number of layer layers, from the layout database 11. The design information including the entire memory use area is read, and the design table 24-1 of the design circuit A and the design table 24-2 of the design circuit B are generated in the auxiliary storage unit 2 (steps S3 and S4).

Next, in the auxiliary storage unit 2, the control unit 3 generates an editing buffer header 21-1 corresponding to the editing buffer 25-1 that stores the circuit layout pattern of the circuit design A corresponding to the circuit design A. Similarly, the editing buffer header 21-2 corresponding to the editing buffer 25-2 for storing the circuit layout pattern of the circuit design A corresponding to the circuit design B is generated (step S6). .
At this time, the control unit 3 writes the editing buffer header addresses of the generated editing buffer headers 21-1 and 21-2 in the design tables 24-1 and 24-2.

In the editing buffer header 21-1, layer buffer information of the circuit design A is stored in an entry for each area corresponding to each layer of the editing buffer 25-1, and each layer number in the circuit layout pattern of the circuit design A is stored. And the area of the editing buffer 25-1 in which the pattern data of this layer is stored.
Similarly, the editing buffer header 21-2 stores the layer buffer information of the circuit design B in the entry for each area corresponding to each layer of the editing buffer 25-2. Each layer number is associated with an area of the editing buffer 25-2 in which pattern data of this layer is stored.

Here, the control unit 3 assigns a predetermined numerical value as an identifier to each layer number.
That is, when editing each layer in the circuit layout pattern in the layout database 11, the control unit 3 adds a numerical value as an identifier to the original layer number at the time when the editing buffer header 21 is generated. As a layer identification number.
As a result, the layer identification number has no original significance as the layer number, and the LSI layout apparatus has a meaning as a management number for managing layer pattern data internally.
At this time, for example, a layer number inherent to the circuit design in the layout database 11 is set within a range of 1000 digits, and a numerical value as an identifier is set within a range of 10,000 digits or more.

Thus, when the editing buffer header 21-1 corresponding to the circuit design A is generated, as shown in FIG. 3, an identifier indicating the circuit design A with respect to the layer number inherent in the circuit layout pattern of the circuit design A As a result, a logical sum operation (or addition) of 50000 is performed and converted into a layer identification number starting from 50101.
Similarly, when the control unit 3 generates the editing buffer header 21-2 corresponding to the circuit design B, as shown in FIG. 3, the control unit 3 generates a circuit for the layer number inherent in the circuit layout pattern of the circuit design B. As an identifier indicating the design B, 60000 is ORed and converted into a layer identification number starting from 60101.
At this time, the control unit 3 writes the correspondence relationship between the circuit design A and the identifier 50000 and the correspondence relationship between the circuit design B and the identifier 60000 in the correspondence table 5.

In the conventional case, since the layer with the same number overwritten is mixed in the same editing buffer, it is impossible to distinguish between the circuit design A and the circuit design B.
Therefore, as described above, when an LSI layout apparatus performs editing using a plurality of different circuit designs, the original layer number is not managed, but is temporarily converted to another layer identification number that can identify the circuit design. , Store in different editing buffers for management.
As a result, similar layers in different circuit designs are not managed by the same layer number, so that they are not stored in the same editing buffer as described above, and destructive editing is not performed.
Even after the circuit layout patterns of the circuit designs A and B to be edited are synthesized and displayed on the display screen of the display unit 4, it is possible to distinguish the pattern data of each layer in different circuit layout patterns. It becomes.

Next, the control unit 3 reads the pattern data of each layer in the circuit layout pattern of the circuit design A from the layout database 11 of the circuit design A of the main storage unit 11, and edits each entry of the editing buffer header 21-1. Corresponding to the editing buffer address, the read layer data is written in a predetermined area of the editing buffer 25-1 (step S7).
Similarly, the control unit 3 reads the layer data of each circuit layout pattern of the circuit design B from the layout database 11 of the circuit design B of the main storage unit 11, and edits each entry of the editing buffer header 21-2. Corresponding to the buffer address, the read layer data is written in a predetermined area of the editing buffer 25-2 (step S8).

Next, the user inputs a display command for displaying the display screen 4-1 and the display screen 4-2 on the display unit 4 to the LSI layout device (steps S9 and S10).
Thereby, the control unit 3 displays the display name, which is the name of the display screen, the initial creator name, the last modified person name, the initial created date, the last modified date, the maximum number of layer layers, which is input by the user according to the display command. Based on the entire memory use area and the like, the display table 22-1 of the screen 1 and the display table 22-2 of the screen 2 are generated in the auxiliary storage unit 2 (steps S11 and S12).

And the control part 3 produces | generates the display header 23-1 which memorize | stores the information of the layer displayed on the display screen 4-1, in the auxiliary storage part 2, and the information of the layer displayed on the display screen 4-2 similarly Is generated.
In addition, the control unit 3 writes the generated display header addresses of the display headers 23-1 and 23-2 in the display tables 22-1 and 22-2.
Here, the user selects a layer to be displayed on the display screen 4-1 and the display screen 4-2 from the layer list in the circuit layout of each of the circuit designs A and B displayed on the display unit 4.
Thereby, the control unit 3 writes the display information of the layers respectively displayed on the display screen 4-1 and the display screen 4-2 input by the user in the areas of the entries in the display headers 23-1 and 23-2, respectively. .

Here, it is assumed that the circuit layout pattern of the circuit design A includes layers A1 to A7, and the circuit layout pattern of the circuit design B includes layers B1 to B7.
Then, in order for the user to edit the connection position of each wiring layer between the memory device of circuit design A and the logic device of circuit design B, the layers A2, A3, A4, A5, A6 in circuit design A and the circuit design B Layers B2 and B7 are displayed on display screen 4-1, while layers A1, A7, A6 and A3 in circuit design A and layers B1, B3 and B6 in circuit design B are displayed on display screen 4-2. On the selection screen of the display unit 4, a layer selection process in each circuit layout pattern is performed.

As a result, the control unit 3 creates entries corresponding to the layers A2, A3, A4, A5, A6, B2, and B7 in the display header 23-1, as shown in FIG. Layer display information is written (step S13).
Similarly, the control unit 3 creates entries corresponding to the layers A1, A7, A6, A3, B1, B3, and B6 in the display header 23-2, and displays the layer display information in each entry field. Write (step S14).
Here, the display color, display pattern, display order, display enable, display coordinates, and display rotation in the display information are set by user input.

Next, the control unit 3 refers to the display table 22-1 and sets the editing buffer headers 21-1 and 211-2 according to each layer identification number described in each entry of the corresponding display header 23-1. Then, the image data which is the layout pattern of each layer is read from the editing buffers 25-1 and 25-2.
Then, the control unit 3 writes the image data of each layer read from the editing buffers 25-1 and 25-2 in the display buffer area corresponding to the display screen 4-1 of the display unit 4 (step S15).

Similarly, the control unit 3 refers to the display table 22-2, and based on the corresponding display header 23-2, via the editing buffer headers 21-1, 21-2, the editing buffers 25-1, The image data of each layer read from 25-2 is written in the display buffer area corresponding to the display screen 4-1 of the display unit 4 (step S16).
And the control part 3 displays the image data of the screen 1 and the screen 2 which were written in each said display buffer on the display part 4 (step S17, S18).

  As described above, the design circuit A to be edited and the circuit design B included in the design circuit A are not distinguished as pattern data in the same layer. By providing an identifier, the editing buffer to be stored is different even in the same layer in the layout pattern. Therefore, the layers are not mixed and mixed, and any of the circuit designs A and B is not mixed. It can be clearly determined whether it belongs to the circuit layout pattern.

Then, when the user's command to end editing is input, the control unit 3 ends editing of each layer of the circuit designs A and B, and returns the editing result to the layout database 11.
At this time, the control unit 3 reads the layer identification number described in the editing buffer 23-1, and refers to the correspondence table 5 to store it in the editing buffer 25-1 from the relationship between the circuit design and the identifier. It is determined that the current layer corresponds to the circuit design A, the identifier is selectively removed from the layer number, and each layer of the editing buffer 25-1 is changed to the circuit design based on the obtained layer number. The area corresponding to each layer of the layout database 11 of A is overwritten.

  Similarly, the control unit 3 reads the layer identification number described in the editing buffer 23-2, refers to the correspondence table 5, and stores it in the editing buffer 25-2 from the relationship between the circuit design and the identifier. It is determined that the applied layer corresponds to the circuit design B, the identifier is selectively removed from the layer identification number, and each layer of the editing buffer 25-2 is changed to the circuit based on the obtained layer number. The area corresponding to each layer in the layout database 11 of the design B is overwritten.

  Note that a program for realizing the function of the LSI layout unit in FIG. 1 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system and executed, thereby executing the LSI layout. Processing may be performed. Here, the “computer system” includes an OS and hardware such as peripheral devices. The “computer system” includes a WWW system having a homepage providing environment (or display environment). The “computer-readable recording medium” refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM, and a CD-ROM, and a storage device such as a hard disk built in the computer system. Further, the “computer-readable recording medium” refers to a volatile memory (RAM) in a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. In addition, those holding programs for a certain period of time are also included.

  The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

It is a block diagram which shows the structural example of the LSI layout apparatus by one Embodiment of this invention. It is a conceptual diagram which shows the relationship between the design table in FIG. 1, an editing buffer header, and an editing buffer. It is a figure which shows the relationship between the original layer number of each layer of the circuit design A and the circuit design B, and the new layer number which added the identifier. It is a conceptual diagram which shows the relationship between a display table and a display header. It is a conceptual diagram explaining the display process of each layer in the circuit layout pattern of the circuit design A and the circuit design B. FIG. 10 is a sequence diagram illustrating display processing of each layer in a circuit layout pattern of circuit design A and circuit design B.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Main memory part 2 ... Auxiliary memory part 3 ... Control part 4 ... Display part 5 ... Correspondence table 6 ... LSI design part 4-1, 4-2 ... Display screen 11 ... Layout database 21, 21-1, 21-2 ... Editing buffer headers 22, 22-1, 22-2 ... Display tables 23, 23-1, 23-2 ... Display headers 24, 24-1, 24-2 ... Design tables 25, 25-1, 25-2 ... editing buffer

Claims (7)

An LSI layout apparatus that displays and edits pattern data of each layer constituting a circuit layout pattern when designing a layout pattern of an LSI using circuit layout patterns belonging to different circuit designs,
A layout database in which pattern data of each layer constituting the circuit layout pattern is stored for each circuit design;
An editing buffer for storing the circuit layout pattern read from the layout database when displayed on the display screen;
A design table storing design information including address information of the editing buffer provided for each circuit design and storing a circuit layout pattern;
A display table corresponding to the display screen and storing display information indicating a circuit layout pattern to be displayed on the display screen;
A display unit that refers to the display information, reads a layer of a predetermined circuit layout pattern from each editing buffer by the design information, and displays pattern data of each layer on the display screen;
An LSI layout apparatus, wherein identification information indicating which circuit design is included is assigned to each layer unit. A buffer header table provided corresponding to each design table, in which layer buffer information including a layer number indicating each layer and an address of an editing buffer is stored;
A display header table that is provided corresponding to the display table and stores display information necessary for displaying each circuit layout pattern on the display screen, including the layer number;
When displaying each layer on the display screen according to the display information of the display table, the pattern data of the layer corresponding to the layer number stored in the display header table is transferred to the editing table via the buffer header table. The LSI layout device according to claim 1, wherein the LSI layout device is read out from.   3. The LSI layout apparatus according to claim 2, wherein a plurality of the display tables are provided, and a display header table is provided for each display table.   4. The LSI layout apparatus according to claim 1, wherein the identification information is represented by a predetermined character or number added to a layer number of each layer. An LSI layout method for displaying and editing pattern data of each layer constituting a circuit layout pattern when designing a LSI layout pattern using circuit layout patterns belonging to different circuit designs,
A storage process in which pattern data of layers constituting the circuit layout pattern corresponds to each circuit design and is stored in a layout database;
A buffer process of storing the circuit layout pattern read from the layout database in an editing buffer when displayed on a display screen;
A design table storing step for storing design information including address information of the editing buffer provided for each circuit design and storing a circuit layout pattern in a design table;
A display table storing step for storing display information corresponding to the display screen and indicating a circuit layout pattern to be displayed on the display screen in a display table;
A display step of referring to the display information, reading out a layer of a predetermined circuit layout pattern from each editing buffer according to the design information, and displaying pattern data of each layer on the display screen;
An LSI layout method, wherein identification information indicating which circuit design is included is assigned to each layer unit. A buffer header table storing step for storing layer buffer information including a layer number indicating each layer and an address of an editing buffer, which is provided corresponding to each design table, in a buffer header table;
A display header table storage process for storing display information provided for the display table and necessary for displaying each circuit layout pattern on the display screen, including the layer number, in the display header table. And
When displaying each layer on the display screen according to the display information of the display table, the pattern data of the layer corresponding to the layer number stored in the display header table is transferred to the editing table via the buffer header table. The LSI layout method according to claim 5, wherein the LSI layout method is read out from. A program for causing a computer to execute LSI layout processing for displaying and editing pattern data of each layer constituting a circuit layout pattern when designing a layout pattern of an LSI using circuit layout patterns belonging to different circuit designs. And
A storage process in which the pattern data of the layers constituting the circuit layout pattern corresponds to each circuit design and is stored in a layout database;
A buffer process for storing the circuit layout pattern read from the layout database in an editing buffer when displayed on a display screen;
Design table storage processing for storing design information including address information of the editing buffer provided for each circuit design and storing a circuit layout pattern in a design table;
Display table storage processing for storing display information corresponding to the display screen and indicating a circuit layout pattern to be displayed on the display screen in a display table;
A display process of referring to the display information, reading a layer of a predetermined circuit layout pattern from each editing buffer by the design information, and displaying pattern data of each layer on the display screen;
A computer-executable LSI layout program, wherein identification information indicating which circuit design is included is assigned to each layer unit.

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