JP2005333699A - Switching power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain an operation delay period sufficient for avoiding lack of a sync signal for instantaneous lack of the sync signal. <P>SOLUTION: The switching power supply comprises a free running oscillation circuit 26 generating a frequency lower than the synchronizing frequency of a sync signal and delivering an oscillation output when the sync signal is inputted, a section 28 for controlling the on interval of a switching element Q1 such that the output voltage has a target value by determining the on timing of the switching element Q1 based on the output from the free running oscillation circuit 26 or the sync signal, and a lack period generation circuit 23 for stopping operation when the sync signal is iputted and starting operation when the sync signal is not iputted. When the sync signal is not iputted, the on interval control section 28 performs switching operation of the switching element Q1 at the on timing of the free running oscillation circuit 26 and performs intermittent switching operation based on the output from the lack period generation circuit 23 upon elapsing a predetermined time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for reducing standby power by operating a switching element intermittently in accordance with a standby operation of a load in a switching power supply apparatus that performs a switching operation of the switching element in synchronization with an external synchronization signal.

  A switching power supply device that drives a switching element at a frequency synchronized with an external synchronization signal and supplies power to a load is horizontal for the purpose of reducing screen noise in, for example, a cathode ray tube (CRT) display device (display). The switching frequency of the switching power supply is synchronized with the synchronization frequency.

  In this case, when the load enters a standby state, the switching power supply device is switched from the operation mode to the standby operation mode, and the switching element is operated intermittently, thereby suppressing the loss of the power supply unit and reducing the input power. This switching power supply device detects the presence or absence of the aforementioned synchronization signal, and determines the state of the load based on the presence or absence of the synchronization signal. For this reason, since the state of the load can be determined without requiring a special signal from the load, the configuration is simple and inexpensive.

  FIG. 7 is a diagram showing a circuit configuration of a conventional switching power supply device. In this switching power supply device, a series circuit of a primary winding NP of a transformer T and a switching element Q1 is connected to both ends of a DC power supply Vin. The switching element Q1 is composed of, for example, a MOSFET, the drain is connected to the primary winding NP, the source is connected to the negative electrode (earth) of the DC power supply Vin, and the gate is connected to the switching element drive unit 19. . The switching element Q1 is turned on / off by a drive signal supplied from the switching element drive unit 19 to the gate.

  A rectifying / smoothing circuit including a diode D1 and a smoothing capacitor C1 is connected to the secondary winding NS of the transformer T, and a load (not shown) is connected to the output terminal of the rectifying / smoothing circuit. An error amplifier 11 is connected between the output terminals of the rectifying and smoothing circuit, and the light amplifier of the photocoupler PC is connected to the error amplifier 11.

  The synchronization signal detection circuit 12 detects a synchronization signal Vtrig (hereinafter abbreviated as a synchronization signal), and includes a diode D2, a capacitor C2, a resistor R1, and a comparator 121. The intermittent cycle generation circuit 13 generates an intermittent signal for causing the switching element Q1 to perform an intermittent operation that repeats the switching operation and the stop by the free-running oscillation circuit 16 when the synchronization signal detection circuit 12 does not detect the synchronization signal.

  The free-running oscillation circuit 16 intermittently oscillates depending on the presence / absence of an intermittent signal from the intermittent cycle generation circuit 13, stops oscillation when the intermittent signal is at the H level, and oscillates when the intermittent signal is at the L level. The OR circuit 17 takes the OR of the synchronization signal and the output of the free-running oscillation circuit 16. The ON period control unit 18 sets the ON width of the pulse so that the output voltage of the rectifying and smoothing circuit becomes a target value determined by the error amplifier 11 based on the output of the OR circuit 17 and the current flowing in the light receiving unit of the photocoupler PC. Control. The switching element driving unit 19 generates a control signal based on the ON width of the pulse controlled by the ON period control unit 18, and controls the switching operation of the switching element Q1 by the control signal.

  In the switching power supply device configured as described above, when the synchronization signal is input to the synchronization signal detection circuit 12, the synchronization signal is rectified and smoothed by the diode D 2 and the capacitor C 2, and the rectified and smoothed voltage is not applied to the comparator 121. Input to the inverting terminal. Since the rectified and smoothed voltage exceeds the reference voltage Vref, the output of the comparator 121 becomes H level, and the intermittent cycle generation circuit 13 does not output the intermittent signal to the free-running oscillation circuit 16. When the synchronization signal is input to the free-running oscillation circuit 16, the oscillation output is not output, but the synchronization signal input to the OR circuit 17 is sent to the ON period control unit 18. That is, when there is a synchronization signal, the switching element Q1 is driven during the ON period in which the output voltage is controlled to the target value while the switching operation is synchronized with the synchronization signal, and the output voltage is supplied to the load.

  When no synchronization signal is input, the free-running oscillation circuit 16 generates an oscillation output and outputs it to the OR circuit 17. Further, the output of the comparator 121 becomes L level, the intermittent cycle generation circuit 13 generates an intermittent signal, and the intermittent signal is input to the free-running oscillation circuit 16. The free-running oscillation circuit 16 performs an intermittent oscillation operation according to the input intermittent signal. That is, when there is no synchronization signal, an intermittent operation that repeats a switching operation and a stop based on the free-running oscillation circuit 16 by an intermittent signal is performed.

  In this way, the presence / absence of the synchronization signal is determined, and when it is detected that there is no synchronization signal, the switching power supply is intermittently operated to set the operation mode suitable for the standby load.

Further, as a technique related to the conventional technique, there is, for example, Patent Document 1.
JP-A-9-9174

  However, in the switching power supply device shown in FIG. 7 described above, there is a problem that a part for rectifying the synchronization signal (synchronization signal detection circuit 12) is required, and the number of parts increases.

  Further, in the case of a CRT horizontal synchronization signal, there is a case in which a loss of several milliseconds is generated when the synchronization signal is switched. For this reason, when the detection circuit for the synchronization signal loss is integrated in the integrated circuit for the switching power supply device to reduce the number of parts and the cost, an operation delay of several tens of milliseconds is taken as a countermeasure against the instantaneous loss of the synchronization signal. Necessary. However, integrating such a time constant circuit having a long time constant as it is in an integrated circuit requires a large mounting area and requires external components. The intermittent cycle generation circuit is also the same, and it is difficult to integrate both.

  In particular, since the switching power supply device is directly connected to the input commercial AC power supply, an abnormal test such as a short circuit and an open circuit between terminals of each component is performed for safety standards. For this reason, the increase in the number of external components and the number of terminals due to this increases not only the cost and mounting area, but also increases the number of test items for confirming safety, reducing the number of external components as much as possible. It is desirable to reduce the possibility of a decrease in safety.

  The present invention integrates a circuit for performing a standby mode operation in an integrated circuit for controlling a switching power supply device in response to the detection of a synchronization signal and the disappearance of the synchronization signal, to prevent an instantaneous loss of the synchronization signal. An object of the present invention is to provide a switching power supply device that can obtain a sufficient operation delay period that avoids the loss of a synchronization signal and can prevent an increase in the number of components.

  The present invention employs the following means in order to solve the above problems. The invention according to claim 1 is a switching power supply device that converts a voltage of an input power supply into a DC output voltage by performing a switching operation of a switching element in synchronization with a synchronization signal, and generates a frequency lower than the synchronization frequency of the synchronization signal. A self-running oscillation circuit that does not output an oscillation output when the synchronization signal is input, and an on-timing of the switching element is determined based on an output of the free-running oscillation circuit or the synchronization signal, and the output voltage becomes a target value. An on-period controller that controls the on-period of the switching element, and an intermittent period generation circuit that stops operation while the synchronization signal is input and starts operation when the synchronization signal is not input, The on-period control unit is configured to switch the switching element at an on-timing of the free-running oscillation circuit when the synchronization signal is not input. Performs switching operation, after a predetermined time, characterized in that for intermittently operating the switching operation based on an output of said intermittent cycle generating circuit.

  The invention according to claim 2 is the switching power supply device according to claim 1, further comprising a history storage circuit that stores that the synchronization signal is input for the first time after the input power supply is activated, and the on-period control unit includes: When the history storage circuit does not store the input of the synchronization signal, the switching operation of the switching element is continued based on the output of the free-running oscillation circuit regardless of the presence or absence of the synchronization signal. It is characterized by.

  A third aspect of the present invention is the switching power supply device according to the second aspect, further comprising a current detection circuit that detects a switching current flowing through the switching element and detects whether or not the switching current exceeds a predetermined current value. When the switching operation of the switching element is performed based on the output of the intermittent cycle generation circuit, when the current detection circuit detects that a switching current greater than or equal to the predetermined current value flows, the history storage It has a memory releasing means for releasing the memory to which the synchronizing signal of the circuit is inputted.

  According to the first aspect of the present invention, the intermittent cycle generation circuit stops operating while the synchronization signal is input, starts operation when the synchronization signal is not input, and the on period control unit does not receive the synchronization signal. When the self-running oscillation circuit is turned on, the switching element performs a switching operation, and after a predetermined time has elapsed, the switching operation is intermittently performed based on the output of the intermittent cycle generation circuit. In other words, the time until the first rise of the intermittent cycle during standby operation is used as the operation delay time for the detection of the synchronization signal and the instantaneous loss of the synchronization signal. Thus, an increase in the number of parts can be prevented at the same time as obtaining a sufficient operation delay period.

  According to the invention of claim 2, when the history storage circuit does not store that the synchronization signal is input, the on-period control unit outputs to the output of the free-running oscillation circuit regardless of the presence or absence of the synchronization signal. Based on this, the switching operation of the switching element is continued. That is, after the power is turned on, a state in which no synchronization signal is input is determined as the time when the power is turned on. .

  According to the invention of claim 3, the current detection circuit detects whether the switching current flowing through the switching element is equal to or greater than a predetermined current value, and the memory release means is configured to detect the switching element based on the output of the intermittent period generation circuit. When the switching operation is performed, if the current detection circuit detects that a switching current of a predetermined current value or more is flowing, the storage to which the synchronization signal of the history storage circuit is input is released. That is, it is possible to determine whether or not to perform an intermittent operation by detecting whether or not the load state is sufficiently light at that time in addition to the disappearance of the synchronization signal.

  Embodiments of a switching power supply apparatus according to the present invention will be described below in detail with reference to the drawings.

  1 is a diagram showing a circuit configuration of a switching power supply apparatus according to Embodiment 1 of the present invention. In this switching power supply, the configurations of the DC power supply Vin, the transformer T, the switching element Q1, the diode D1, the smoothing capacitor C1, the photocoupler PC, and the error amplifier 11 are the same as those of the conventional switching power supply shown in FIG. Since it is the same structure, those description is abbreviate | omitted.

  The switching power supply control unit 21 includes a flip-flop FF1 including a synchronization signal storage circuit 22, an intermittent cycle generation circuit 23, a control unit power supply 24, a flip-flop FF2 including an intermittent signal storage circuit 25, OR circuits U1 and U4, an inverter circuit IV2, A NOR circuit U3, a free-running oscillation circuit 26, an ON period control unit 28, and a switching element drive circuit 29 are provided. The switching power supply control unit 21 is integrated in an integrated circuit for controlling the switching power supply device.

  The flip-flop FF1 stores the synchronization signal by inputting the synchronization signal to the set terminal S, and inputs the output of the free-running oscillation circuit 26 to the reset terminal R to operate the free-running oscillation circuit 26. Release the memory of the sync signal.

The intermittent cycle generation circuit 23 stops the operation while the flip-flop FF1 stores the input of the synchronization signal, and has an OR circuit U2, an inverter circuit IV1, an FET Q2, an FET Q3, and a comparator CP1. Yes. The OR circuit U2 takes an OR of the output of the flip-flop FF1 and the output of the comparator CP1. The source of the FET Q2 and the drain of the FET Q3 are commonly connected, the drain of the FET Q2 is connected to the control unit power supply 24 through a constant current source, and the source of the FET Q3 is grounded. A connection point between the source of the FET Q2 and the drain of the FET Q3 is connected to one end of the capacitor Ct and the non-inverting terminal of the comparator CP1. The output of the OR circuit U2 is connected to the gate of the FET Q2 via the inverter circuit IV1, and is directly connected to the gate of the FET Q3. The comparator CP1 is a hysteresis comparator, and outputs an H level when the voltage between both ends of the capacitor Ct reaches the voltage V _t2 (V _t1 <V _t2 ) and is in the range of the voltage V _{t2 to} V _t1 . voltage across when less than zero voltage ~V _t2 and outputs the L level. That is, the intermittent cycle generation circuit 23 generates an intermittent cycle signal that is an output of the comparator CP1 based on the voltage across the capacitor Ct when no synchronization signal is input.

  The flip-flop FF2 inputs the comparator CP1 output of the intermittent cycle generation circuit 23 to the set terminal S, inputs the output of the flip-flop FF1 to the reset terminal R, stores the rising edge of the first pulse of the intermittent cycle generation circuit 23, and synchronizes When a signal is input, the memory is released. That is, the flip-flop FF2 stores the intermittent operation based on the output of the comparator CP1 of the intermittent cycle generation circuit 23 and the synchronization signal.

  Inverter circuit IV2 inverts the output of flip-flop FF2. The NOR circuit U3 inverts the output of the comparator CP1, inverts the output of the inverter circuit IV2, and takes the AND of these two inverted outputs. The OR circuit U1 takes an OR of the synchronization signal and the NOR circuit U3 output.

  The free-running oscillation circuit 26 has an OR circuit U1 output and has a time constant circuit that oscillates at a frequency lower than the synchronization frequency of the synchronization signal. The time constant circuit is reset by the synchronization signal and the synchronization signal is input. During this period, no oscillation output is output, and when no synchronization signal is input, the oscillation output is output. The OR circuit U4 takes an OR of the synchronization signal and the output of the free-running oscillation circuit 26.

  The ON period control unit 28 determines the ON timing of the switching element Q1 based on the output of the OR circuit U4, that is, the output of the free-running oscillation circuit 26 or the synchronization signal, and based on the current flowing in the light receiving unit of the photocoupler PC, The ON period of the switching element Q1 is controlled so that the output voltage becomes a target value determined by the error amplifier 11. The on-period control unit 28 controls the free-running oscillation circuit 26 based on the output of the comparator CP1 of the intermittent period generation circuit 23 while the flip-flop FF2 stores the rising edge of the first pulse of the intermittent period generation circuit 23. The switching operation of the based switching element Q1 is intermittently operated.

  The switching element drive circuit 29 generates a control signal based on the ON period of the pulse controlled by the ON period control unit 28, and controls the switching operation of the switching element Q1 by the control signal.

  Next, the operation of the switching power supply apparatus according to the first embodiment configured as described above will be described with reference to an operation waveform diagram shown in FIG.

(1) A synchronization operation when a synchronization signal is input will be described.

  In the period T1, the period T3, and the period T6 illustrated in FIG. 2, first, a synchronization signal is input to the on period control unit 28 via the OR circuit U4. This synchronization signal determines the on-timing of the switching element Q1. For this reason, the ON period control unit 28 determines the ON timing of the switching element Q1 by the pulse of the synchronization signal, and the ON period signal of the switching element Q1 by the signal from the photocoupler PC that is a feedback signal from the secondary side of the transformer T. Is generated.

  The switching element driving circuit 29 drives the switching element Q1 by the on period signal generated by the on period control unit 28. Thereby, the on period control unit 28 turns on the switching element Q1 after turning it on for the on period. For this reason, since a current flows through the switching element Q1 in synchronization with the synchronization signal, the switching element Q1 performs a synchronization operation.

  On the other hand, the synchronization signal is input to the free-running oscillation circuit 26 via the OR circuit U1, but the free-running oscillation circuit 26 does not generate an oscillation output while the synchronization signal is continuously input.

  Further, when the synchronization signal is input to the set terminal S of the flip-flop FF1, the flip-flop FF1 stores that the synchronization signal has been input. That is, since the flip-flop FF1 is set while the synchronization signal is input, the H level FF1 output voltage is output to the inverter circuit IV1 and the FET Q3 via the OR circuit U2. Therefore, the FET Q2 is turned off and the FET Q3 is turned on. Then, since the electric charge of the capacitor Ct is discharged through the FET Q3, the voltage at the non-inverting terminal of the comparator CP1 becomes substantially zero voltage, so that the intermittent period oscillation circuit 23 is held in a stopped state. For this reason, the output of the comparator CP1 becomes L level.

  Next, the flip-flop FF2 inputs the L level, which is the output of the comparator CP1 of the intermittent oscillation circuit 23, to the set terminal S, and inputs the output of the flip-flop FF1 to the reset terminal R, so that the memory is released by the synchronization signal. That is, while the synchronization signal is input, the flip-flop FF1 is set and the flip-flop FF2 is continuously reset. For this reason, the NOR circuit U3 output is held at the L level.

  As a result, only the synchronization signal is output from the OR circuit U1, and the free-running oscillation circuit 26 does not output the oscillation output because the time constant of the time constant circuit is continuously reset by the synchronization signal from the OR circuit U1.

  As described above, in the period T1, the period T3, and the period T6 in which the synchronization signal is input, the switching element Q1 is in the on period in which the output voltage is controlled to the target value while performing the synchronization operation that is the switching operation synchronized with the synchronization signal. To supply the output voltage to the load.

(2) Next, the free-running oscillator operation when the synchronization signal disappears instantaneously will be described.

  In the period T2 and the period T4 shown in FIG. 2, first, when the synchronization signal is not input to the free-running oscillation circuit 26 via the OR circuit U1, the oscillation output of the free-running oscillation circuit 26 is generated. The frequency of this oscillation output is lower than the frequency of the synchronization signal.

  Then, in the flip-flop FF1, since no synchronization signal is input to the set terminal S and the oscillation output of the free-running oscillation circuit 26 is input to the reset terminal R, the output of the flip-flop FF1 becomes L level. For this reason, the L level signal turns off the FET Q3 of the intermittent cycle generation circuit 23 via the OR circuit U2, and turns on the FET Q2. Then, a current flows from the control power supply 24 to the capacitor Ct via the constant current source and the FET Q2, and the capacitor Ct is charged.

The comparator CP1 is, until the voltage of the capacitor Ct is charged to a voltage V _t2 the output is at the L level. For this reason, since the flip-flop FF2 holds the reset state, the output of the flip-flop FF2 is L level, and one of the inputs of the NOR circuit U3 is H level. Therefore, the NOR circuit U3 output becomes L level, but this L level does not act on the free-running oscillation circuit 26 via the OR circuit U1.

  For this reason, in the period T2 and the period T4, the switching element Q1 continues to be switched at the switching period determined by the free-running oscillation circuit 26. That is, a free-running oscillator operation is performed.

Further, when the synchronization signal is restored before the voltage of the capacitor Ct rises to the voltage V _t2 determined by the comparator CP1 (in the example shown in FIG. 2, when switching from the period T2 to the period T3), the free-running oscillation circuit through the OR circuit U1. The synchronization signal is input to 26, and the oscillation output of the free-running oscillation circuit 26 is stopped. At the same time, the flip-flop FF1 is set, the FET Q3 is turned on via the OR circuit U2, the FET Q2 is turned off, and the capacitor Ct is discharged. As a result, the state before the disappearance of the synchronization signal is entered, and the switching operation of the switching element Q1 is continued as it is.

(3) Next, the operation when the synchronization signal disappears continuously will be described.

In the period T5 shown in FIG. 2, the sync signal is continuously lost. In this case, the operation is substantially the same as the operation when the synchronization signal disappears instantaneously, but when the synchronization signal disappears continuously until the capacitor Ct is charged to the voltage V _t2 determined by the comparator CP1, the comparator CP1 The output becomes H level. Therefore, the flip-flop FF2 is set by the first H level of the rising time _{t 51} of the comparator CP1 output. After synchronization signal is no longer inputted to the time t ₅₁ (time T4) is waiting operation delay time.

  In this state, since the output of the comparator CP1 is at the H level, one of the NOR circuit U3 inputs is at the H level, the NOR circuit U3 output is at the L level, and the output acts on the free-running oscillation circuit 26 at this time. do not do. For this reason, the free-running oscillation circuit 26 continues to operate, and the switching element Q1 continues the switching operation.

When the comparator CP1 becomes H level, the FET Q3 is turned on via the OR circuit U2 due to this H level, the FET Q2 is turned off, and the discharge of the capacitor Ct is started. In order for the output of the comparator CP1 to become L level, the voltage of the capacitor Ct must be discharged by the hysteresis voltage of the comparator CP1. Therefore, the output of the comparator CP1 remains at H level until the hysteresis voltage of the comparator CP1 (V _t2 −V _t1 ) is discharged, and this circuit continues the switching operation by the free-running oscillation circuit 26.

Then, when the capacitor Ct is discharged and the output of the comparator CP1 becomes L level, for example, at time _t52 , since the flip-flop FF2 stores the set state, both the NOR circuit U3 inputs become L level, The output of the NOR circuit U3 becomes H level.

When the output of the NOR circuit U3 becomes H level, the synchronization signal input of the free-running oscillation circuit 26 continuously becomes H level via the OR circuit U1. Since the free-running oscillation circuit 26 performs an operation of resetting the time constant by the synchronization signal, when the synchronization signal input is continuously kept at the H level, the time constant remains reset and no oscillation output is generated. Therefore, the switching operation of the switching element Q1 is stopped while the output of the NOR circuit U3 is at the H level (for example, from time t ₅₂ to time t ₅₃ ).

Further, when the capacitor Ct is discharged and the output of the comparator CP1 becomes L level at time _t52 , for example, the FET Q3 is turned off and the FET Q2 is turned on via the OR circuit U2. Therefore, the capacitor Ct is charged, the capacitor Ct is the voltage _{V t2} hysteresis voltage component rises and for example, time _{t 53} of the comparator CP1, the comparator CP1 output becomes H level again.

  Then, the FET Q3 is turned on, the FET Q2 is turned off, and the capacitor Ct starts discharging. When the output of the comparator CP1 becomes H level, the output of the NOR circuit U3 becomes L level and there is no input to the free-running oscillation circuit 26. For this reason, switching is started again by the output of the free-running oscillation circuit 26.

The above operation is continued until time t ₅₄ which synchronizing signal is inputted again, the switching operation of the switching element Q1 is intermittently performed by the comparator CP1 outputs the intermittent period oscillation circuit 23 by charging and discharging the capacitor Ct. That is, an intermittent operation is performed to reduce switching loss at light load.

  As described above, according to the switching power supply device of the first embodiment, the power source used for the CRT display performs the switching operation in synchronization with the synchronization signal from the outside, and when the synchronization signal from the outside is not input, free-running oscillation Switching operation is performed by the circuit. At the same time, it is determined that the system is in the standby state, and the switching operation is intermittently performed to reduce standby power consumption. However, there is a case where an instantaneous synchronization signal may be lost when switching the screen resolution. However, it is not necessary to detect this and enter a standby mode operation. According to the switching power supply device of the first embodiment, the switching power supply control unit 21 for performing these operations is integrated in the integrated circuit for controlling the switching power supply device, and during the standby operation against the instantaneous loss of the synchronization signal. Since the time until the first pulse of the missing period is used as the operation delay time, it is not necessary to obtain a sufficient operation delay period to avoid the loss of the synchronization signal and to make a separate operation delay time. It is possible to prevent an increase in the number of parts and an increase in the number of terminals.

  Next, a switching power supply device according to the second embodiment will be described. In the switching power supply device according to the first embodiment shown in FIGS. 1 and 2, it is assumed that the standby operation mode is first entered when the power supply is started, and then the normal operation is entered by inputting the synchronization signal.

  However, in actual use, there may be a case where the normal operation is entered directly without going through the standby operation mode when the power is turned on. There is a problem that it takes a long time for normal startup when the mode is shifted from the standby mode to the normal mode after the power is turned on instead of the standby mode. For this reason, in the switching power supply device according to the second embodiment, a state in which no synchronization signal arrives after power activation is determined as power activation, and in this state, a self-running oscillation circuit is not performed without performing an intermittent oscillation operation in a standby mode. 26, the switching operation of the switching element Q1 is continued.

  FIG. 3 is a diagram showing a circuit configuration of a switching power supply apparatus according to Embodiment 2 of the present invention. The switching power supply device according to the second embodiment illustrated in FIG. 3 further includes a flip-flop FF3 including an initialization circuit 30, a history storage circuit 31, and an OR circuit U5 in addition to the switching power supply device according to the first embodiment illustrated in FIG. It is characterized by that.

  The initialization circuit 30 outputs an initialization signal to the flip-flop FF3 only once after the power is turned on. The flip-flop FF3 stores the fact that the initialization signal is input starting from the initialization circuit 30 after starting the power supply. The OR circuit U5 takes an OR of the output of the flip-flop FF1 and the output of the flip-flop FF3. When the flip-flop FF3 does not store the input of the synchronization signal, the on period control unit 28 continues the switching operation of the switching element Q1 by the output of the free-running oscillation circuit 26 regardless of the presence or absence of the synchronization signal.

  Next, the operation of the switching power supply device according to the second embodiment configured as described above will be described with reference to the operation waveform diagram shown in FIG.

  First, in the period T11, the flip-flop FF3 is set (H level) by a signal that is output only once from the initialization circuit 30 after the power is turned on. Thereafter, in a state where no synchronization signal is input, the flip-flop FF3 continues to be set, and the OR circuit U2 output is maintained at the H level via the OR circuit U5, so that the intermittent cycle generation circuit 23 does not operate. Therefore, in this state, the switching operation of the switching element Q1 is continued according to the output of the free-running oscillation circuit 26.

  Next, when a synchronization signal is input in the period T12 after the power is turned on, the flip-flop FF3 is reset by the synchronization signal, the free-running oscillation circuit 26 does not output an oscillation output, and the synchronization signal is turned on via the OR circuit U4. Input to the period control unit 28. For this reason, a synchronization operation synchronized with the synchronization signal is performed.

  Next, when the synchronization signal is not input in the period T13, the output of the flip-flop FF3 is at the L level, so that the intermittent period generation circuit 23 operates this time and the state where the synchronization signal is not input is continued, that is, In the period T14, the intermittent operation is started as in the period T5 of the first embodiment shown in FIG.

  As described above, according to the switching power supply device of the second embodiment, when the power is turned on, continuous oscillation (self-running oscillator operation) is performed by the free-running oscillation circuit 26, and once the synchronization signal is input, the synchronization signal disappears. By detecting this, a standby operation mode by intermittent oscillation is entered. That is, after the power supply is activated, a state in which no synchronization signal is input is determined to be when the power supply is activated. In this state, the intermittent operation in the standby operation mode is not performed, and the switching operation of the switching element by the free-running oscillation circuit 26 is performed. For this reason, it is possible to cope with the case where the normal operation is directly started without going through the standby operation mode when the power is turned on.

  Next, a switching power supply device according to Embodiment 3 will be described. Whether or not the switching power supply according to the third embodiment performs an intermittent operation by detecting whether the load signal is sufficiently light at that time as well as the synchronization signal disappears with respect to the switching power supply according to the second embodiment. A means for judging the above is provided.

  FIG. 5 is a diagram showing a circuit configuration of a switching power supply apparatus according to Embodiment 3 of the present invention. The switching power supply device according to the third embodiment shown in FIG. 5 is further different from the switching power supply device according to the second embodiment shown in FIG. 3 in that the switching current detection resistor Rs and the OR circuit U7 are connected in series to the source of the switching element Q1. And a comparator CP2 and an AND circuit U6.

  At both ends of the switching current detection resistor Rs, a voltage proportional to the switching current flowing through the switching element Q1 is generated. The comparator CP2 outputs an H level when the voltage across the switching current detection resistor Rs exceeds the reference voltage Vs, and outputs an L level when the voltage across the switching current detection resistor Rs is equal to or lower than the reference voltage Vs. Detect if the value is greater than or equal to. The switching current detection resistor Rs and the comparator CP2 constitute a current detection circuit of the present invention.

  The AND circuit U6 takes an AND of the comparator CP1 output and the comparator CP2 output. The OR circuit U7 takes an OR of the output of the initialization circuit 30 and the output of the AND circuit U6. That is, when the AND circuit U6 and the OR circuit U7 are performing the switching operation of the switching element Q1 based on the output of the intermittent period generation circuit 23, it is detected that a switching current greater than a predetermined current value flows. In some cases, the memory to which the synchronization signal of the flip-flop FF3 is input is released.

  Next, the operation of the switching power supply device according to the third embodiment configured as described above will be described with reference to the operation waveform diagram shown in FIG.

  First, the switching current flowing through the switching element Q1 is detected by the switching current detection resistor Rs, and the comparator CP2 determines that the voltage across the switching current detection resistor Rs corresponds to the reference voltage Vs (in FIG. 6, a predetermined current value CP2 detection level). The output of the comparator CP2 becomes H level.

  Since the output of the comparator CP2 is ANDed with the output of the comparator CP1 of the intermittent cycle generation circuit 23, only when an output for performing an intermittent operation is output from the intermittent cycle generation circuit 23 (FIG. 6). In the example shown, the output of the comparator CP2 is output from the AND circuit U6 to the OR circuit U7 during the period T24).

  If there is a rising output of the first pulse of the intermittent oscillation from the comparator CP1 in the period T24, and if there is an H level output indicating that the switching current has exceeded a predetermined value from the comparator CP2, the AND circuit U6 output Becomes H level and flip-flop FF3 is set.

  When the flip-flop FF3 is set, the OR circuit U5 output and the OR circuit U2 output become H level, the intermittent cycle generation circuit 23 is stopped, and the flip-flop FF2 is reset. Thereby, the intermittent operation is stopped, and the switching element Q1 is continuously oscillated by the free-running oscillation circuit 26 (period T25).

  As described above, when the synchronization signal disappears and the H level signal is output from the comparator CP1 of the intermittent cycle generation circuit 23, when the switching current flows more than a predetermined value and it is determined that the load is heavy, Continuous oscillation by the output of the free-running oscillation circuit 23 is continued. That is, not only the sync signal disappears but also the load state is detected at that time, and when the load is heavy, the operation can be switched to the free-running oscillator operation. Depending on the CRT display, when the resolution setting is changed significantly, it is necessary to switch the internal components with a relay. In such a case, the synchronization signal is lost for a relatively long time, which may be longer than the operation delay time. Yes. In this case, the intermittent operation is temporarily started but the load is heavy, so that the switching operation of the switching element by the free-running oscillation circuit is immediately switched, and thereafter, when the synchronization signal is inputted, the switching operation by the synchronization signal is started.

  The present invention is applicable to a power supply device for a CRT display device.

It is a figure which shows the circuit structure of the switching power supply device which concerns on Example 1 of this invention. It is an operation | movement waveform diagram for demonstrating operation | movement of the switching power supply which concerns on Example 1 of this invention. It is a figure which shows the circuit structure of the switching power supply which concerns on Example 2 of this invention. It is an operation | movement waveform diagram for demonstrating operation | movement of the switching power supply which concerns on Example 2 of this invention. It is a figure which shows the circuit structure of the switching power supply apparatus which concerns on Example 3 of this invention. It is an operation | movement waveform diagram for demonstrating operation | movement of the switching power supply which concerns on Example 3 of this invention. It is a figure which shows the circuit structure of the conventional switching power supply device.

Explanation of symbols

11 Error amplifier 12 Intermittent signal detection circuit 13, 23 Intermittent cycle generation circuit 16, 26 Self-running oscillation circuit 17 OR circuit
DESCRIPTION OF SYMBOLS 19 Switching element control part 21 Switching power supply control part 22 Synchronization signal memory | storage circuit 24 Control power supply 25 Intermittent signal memory | storage circuit 18, 28 ON period control part 29 Switching element drive circuit 30 Initialization circuit 31 History memory | storage circuit U1, U2, U4, U5 , U7 OR circuit U3 NOR circuit U6 AND circuit Q1 Switching element Q2-Q3 FET
R1 Resistor C1 Smoothing capacitor C2, C3 Capacitor D1, D2 Diode FF1-FF3 Flip-flop CP1-CP2 Comparator PC Photocoupler T Transformer NP Primary winding NS Secondary winding

Claims (3)

In the switching power supply device that converts the voltage of the input power supply into a DC output voltage by performing the switching operation of the switching element in synchronization with the synchronization signal,
A free-running oscillation circuit that generates a frequency lower than the synchronization frequency of the synchronization signal and does not output an oscillation output when the synchronization signal is input;
An on-period controller that determines an on-timing of the switching element based on an output of the free-running oscillation circuit or the synchronization signal, and controls an on-period of the switching element so that the output voltage becomes a target value;
The operation is stopped while the synchronization signal is input, and includes an intermittent cycle generation circuit that starts operation when the synchronization signal is not input.
The on period control unit performs the switching operation of the switching element at the on timing of the free-running oscillation circuit when the synchronization signal is not input, and performs switching based on the output of the intermittent period generation circuit after a predetermined time has elapsed. A switching power supply device characterized by intermittent operation. A history storage circuit for storing that the synchronization signal is input for the first time after starting the input power supply;
When the history storage circuit does not store that the synchronization signal is input, the on-period control unit is configured to switch the switching element based on the output of the free-running oscillation circuit regardless of the presence or absence of the synchronization signal. The switching power supply device according to claim 1, wherein the switching operation is continuous. A current detection circuit for detecting a switching current flowing through the switching element and detecting whether the switching current has exceeded a predetermined current value;
When the switching operation of the switching element is performed based on the output of the intermittent cycle generation circuit, when the current detection circuit detects that a switching current greater than or equal to the predetermined current value flows, the history storage 3. The switching power supply device according to claim 2, further comprising a memory canceling unit that cancels the memory to which the synchronization signal of the circuit is input.

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