JP2005333154A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the reliability, response speed, and write/read characteristics of a transistor. <P>SOLUTION: The semiconductor device of the invention comprises a silicon substrate 10 a surface of which has a step 11 and a terrace 12, a gate insulator film 15 which is formed on the silicon substrate 10 and includes a crystalline oxide film, and a gate electrode 16 which is formed on the gate insulator film 15. The silicon substrate 10 has a source region 20 and a drain region 21, between which there is a portion of the silicon substrate 10 that is in contact with the gate insulator film 15. The gate insulator film 15 and the portion of the silicon substrate 10 that is in contact with the gate insulator film 15 have a crystal-crystal structure. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a MOS heterostructure, a semiconductor device having the structure, and a method for manufacturing the same.

  Conventionally, MOS field effect transistors having a metal-insulator-semiconductor structure (MOS type heterostructure) have been used as field effect transistors. Hereinafter, a conventional method for manufacturing a MOS field effect transistor and its operation will be described with reference to FIGS.

First, after preparing a normal single crystal silicon semiconductor substrate 50 shown in FIG. 4A, a silicon oxide film 51 is formed on the surface of the silicon substrate 50 as shown in FIG. . The silicon oxide film 51 is mainly formed of amorphous SiO ₂ .

  Next, after depositing a conductive thin film such as a polycrystalline silicon film on the silicon oxide film 51, the conductive thin film and the silicon oxide film 51 are patterned using lithography and etching techniques to obtain the structure shown in FIG. As shown, a gate structure including a gate insulating film 52 and a gate electrode 53 is formed.

  As shown in FIG. 4D, after the sidewall oxide film 57 is formed on the side surface of the gate structure, the source region 55 and the drain region 56 are formed in the silicon substrate 51 by the impurity doping method. A channel 54 is formed below the gate electrode 53 between the source region 55 and the drain region 56.

  When the surface of the silicon substrate 50 is thermally oxidized, the interface (silicon-thermal oxide interface) between the silicon substrate 50 and the silicon oxide film 51 is accompanied by the volume expansion of the silicon oxide film 51 grown on the surface of the silicon substrate 50. Distortion occurs. This distortion induces structural defects in the silicon substrate 50 and causes the formation of interface states. The interface state acts as a carrier trap site, causing dielectric breakdown of the gate oxide film 52 and deterioration of carrier mobility in the channel. This has various adverse effects on the characteristics of the MOS field effect transistor, and greatly impedes the high-speed operation of the transistor.

Further, as shown in FIG. 5A, a structural transition layer (thickness: 0.2 to 0.3 nm) 51a composed of a thin suboxide layer due to incomplete oxidation is formed at the silicon-thermal oxide interface. The The structural transition layer 51a is made of SiO _x (x ≦ about 1.7). A normal amorphous SiO ₂ layer (thickness: several nm) 51b is grown on the structure transition layer 51a. The structural transition layer 51a is responsible for stress relaxation between Si and SiO ₂ , but the bonds in the structural transition layer 51a are easily broken by electrons traveling in the channel and easily broken by electron injection. Therefore, the structure transition layer 51a is electrically unstable. As the silicon dioxide film 51 functioning as the gate oxide film 52 becomes thinner, the proportion of the structure transition layer 51a in the silicon dioxide film 51 becomes larger. Therefore, the fluctuation and failure of transistor characteristics due to the interface structure are serious. Become.

  FIG. 5B shows the energy levels of the conduction band and the valence band measured along the depth direction from the surface of the silicon oxide film 51 toward the inside of the silicon substrate 50. As can be seen from FIG. 5B, the energy level 61 of the conduction band and the energy level 62 of the valence electrons in the silicon oxide film 51 are bent in a region wider than that including the structure transition layer 51a (bending phenomenon). . Due to the bending of the energy level, the band gap of the silicon oxide film 51 is greatly reduced at the silicon-thermal oxide interface. Such a reduction in the energy gap of the silicon oxide film 51 reduces the breakdown voltage and reliability of the silicon oxide film 51.

  As described above, the thickness of the structural transition layer 51a is about 0.2 to 0.3 nm, but the thickness of the portion of the silicon oxide film 51 where the band gap is reduced reaches about 1 nm. Further, even if the thickness of the silicon oxide film 51 is decreased, the thickness of the structural transition layer 51a does not decrease. Therefore, the decrease in the thickness of the silicon oxide film 51 represents the proportion of the structural transition layer 51a in the silicon dioxide film 51. Increase the ratio and increase the percentage of the band gap reduction. When the proportion of the structure transition layer 51a in the silicon dioxide film 51 increases, not only does the breakdown voltage of the silicon oxide film 51 deteriorate, but also problems due to non-uniform film thickness and increased interface roughness become significant. For example, when the unevenness (roughness) of the silicon-thermal oxide interface is large, or when the thickness of the silicon oxide film 51 (that is, the gate oxide film 52) is not uniform, the electrons in the channel 54 feel the unevenness of the interface. Traveling, the electron scattering probability increases. As the effective vertical electric field strength increases as the size of the field effect transistor is reduced, this scattering phenomenon becomes more prominent. This means that the electron mobility is lowered, that is, the mutual conductance is lowered. Due to these factors, improvement in the characteristics of a fine MOS field effect transistor having an extremely thin gate insulating film is hindered.

  The present invention has been made in view of the above problems, and its object is to provide a MOS type heterostructure that is structurally and electrically stable, a semiconductor device having such a MOS type heterostructure, and It is in providing the manufacturing method.

  In order to achieve the above object, a first semiconductor device according to the present invention includes a silicon substrate having a step and a terrace on its surface, a gate insulating film including a crystalline oxide film formed on the silicon substrate, and a gate. A silicon substrate having a source region and a drain region sandwiching a silicon substrate portion in contact with the gate insulating film, a silicon substrate portion in contact with the gate insulating film, and a gate insulating film Have a crystal-crystal structure.

  According to the first semiconductor device, since the gate insulating film formed on the silicon substrate includes the crystalline oxide film, generation of strain at the interface between the silicon substrate and the gate insulating film is suppressed. For this reason, the formation of the interface order is also suppressed, and from this the deterioration of the carrier moving speed is suppressed. Further, since there is no amorphous silicon dioxide film or sub-oxide layer at the interface between the silicon substrate and the insulating film, the withstand voltage is excellent.

  Here, it is preferable that the crystal-crystal structure is constituted by the silicon substrate being monocrystalline silicon and the gate insulating film being a crystal film that is two-dimensionally continuous along the surface of the silicon substrate.

  The thickness of the gate insulating film is preferably 2 nm or less.

  The gate insulating film preferably further includes a dielectric film formed on the crystalline oxide film.

  The dielectric constant of the dielectric film is preferably higher than that of silicon dioxide.

  The misorientation angle of the silicon substrate is preferably 0 ° or more and 20 ° or less.

  The crystalline oxide film preferably covers 50% or more of the region covered with the gate insulating film on the surface of the silicon substrate.

  In order to achieve the above object, a second semiconductor device of the present invention includes a silicon substrate having a step and a terrace on its surface, a gate insulating film including a crystalline oxide film formed on the surface of the silicon substrate, A floating gate formed on the gate insulating film and a control gate capacitively coupled to the floating gate are provided, and the crystalline oxide film is 90% or more of the region covered with the gate insulating film on the surface of the silicon substrate. It is preferable to cover.

  In order to achieve the above object, a first method for manufacturing a semiconductor device according to the present invention includes a step of forming a silicon substrate having a step and a terrace using a heat cleaning method while holding the silicon substrate in a vacuum. The step of forming a crystalline oxide film on the surface of the silicon substrate by heating the silicon substrate in an oxygen atmosphere, the step of forming a gate electrode on the crystal oxide film, and the impurity doping to the silicon substrate Forming a region and a drain region.

  The step of forming the crystalline oxide film is preferably performed by supplying dry oxygen that has been passed through liquid nitrogen onto the silicon substrate.

  In order to achieve the above object, a second method for manufacturing a semiconductor device of the present invention includes a step of forming a silicon substrate having a step and a terrace by using a heat cleaning method while holding the silicon substrate in a vacuum. The step of forming a crystalline oxide film by epitaxial growth on the terrace on the surface of the silicon substrate, the step of forming a gate electrode on the crystal oxide film, and the impurity doping of the silicon substrate to form a source region and a drain region A process.

  In the first and second semiconductor device manufacturing methods of the present invention, the crystalline oxide film is preferably formed to a thickness of 2 nm or less.

  In the first and second semiconductor device manufacturing methods of the present invention, the crystalline oxide film is formed on the crystalline oxide film after the step of forming the crystalline oxide film and before the step of forming the gate electrode. Preferably, the method further includes the step of depositing a dielectric film having a dielectric constant higher than the dielectric constant.

  In the first and second semiconductor device manufacturing methods of the present invention, the misorientation angle of the silicon substrate is preferably 0 ° or more and 20 ° or less.

  According to the semiconductor device of the present invention, the surface of the single crystal silicon substrate has a flat surface at the atomic level formed by rearrangement of silicon atoms, and the insulating film formed on the surface is a single crystal silicon substrate. Crystalline silicon dioxide epitaxially grown on the surface of the substrate. Therefore, a semiconductor device having a MOS type heterostructure with few crystal defects is realized without applying a strong stress to the silicon substrate when forming the insulating film. In addition, since there is no amorphous silicon dioxide film or suboxide layer at the interface between the single crystal silicon substrate and the insulating film, a semiconductor device with excellent breakdown voltage can be obtained.

  When the thickness of the insulating film is 2 nm or less, most of the region of the insulating film is composed of a crystalline silicon dioxide layer. Therefore, a MOS type heterostructure with improved reliability while using an ultra-thin gate insulating film. A structure is provided.

  If a dielectric film is added on crystalline silicon dioxide, the leakage current can be further reduced.

  In addition, since the semiconductor device of the present invention has the above-described MOS type heterostructure, it can operate at a high speed and exhibits performance with excellent breakdown voltage and reliability. In particular, when the present invention is applied to a nonvolatile memory, an oxide film that hardly deteriorates by hot electron injection can be obtained.

  According to the method for manufacturing a semiconductor device of the present invention, the semiconductor device as described above can be manufactured.

(Embodiment 1)
Hereinafter, embodiments of the present invention will be described for a semiconductor device having a MOS heterostructure. The semiconductor device according to the present embodiment has a MOS field effect transistor formed using a single crystal silicon substrate. This semiconductor device actually includes circuit elements other than transistors, a wiring structure, an element isolation structure, etc., as in the known semiconductor integrated circuit, but in the drawings, only the MOS type heterostructure portion of the transistor is shown for simplification. Indicates.

  Reference is made to FIGS. First, as shown in FIG. 1A, a (001) clean surface is formed on the (001) plane of the single crystal silicon substrate 10 by a vacuum heating cleaning method or a silicon homoepitaxial growth method. More specifically, in the present embodiment, a single crystal silicon substrate 10 having a misorientation angle 13 of 0 to 0.02 ° is used, and the above-described heating cleaning method in vacuum or homoepitaxial growth of silicon is performed on the substrate 10. When the surface treatment is performed by the method, the rearrangement phenomenon of silicon atoms proceeds on the outermost surface of the cleaned silicon substrate 10, and steps 11 and terraces 12 are formed on the surface of the silicon substrate 10.

  In addition, in order to obtain such a surface, other surface cleaning methods include hot water cleaning, buffered hydrofluoric acid treatment in which hydrogen peroxide solution is mixed, and improved SC in which the concentration of hydrogen peroxide solution is increased. -1 cleaning, diluted hydrofluoric acid treatment, or other wet treatment methods may be performed.

  The form of the surface of the silicon substrate 10 on which the step 11 and the terrace 12 are formed is expressed as (Si (001) -2 × 1). The density of step 10 in the unit area decreases as the misorientation angle 13 of the silicon substrate 10 decreases. For example, when the misorientation angle is 0.02 ° or less as in this embodiment, the interval of step 12 (corresponding to the terrace width) is about 3 nm by vacuum heating cleaning at about 1000 ° C. for about 10 to 20 seconds. It becomes the size below. Step 11 extends along the [11-0] direction.

  On these terraces 12, an atomic arrangement (hereinafter referred to as “dimer row”) composed of a dimer of silicon atoms on the outermost surface (hereinafter referred to as “dimer”) is formed. When the misorientation angle 13 of the substrate is small as in the present embodiment, a form is obtained in which dimer rows are alternately present at right angles for each atomic step on each terrace.

  Next, the silicon substrate 10 having the Si (001) -2 × 1 surface form is heated to 850 ° C. by a rapid heating oxidation method in a dry oxygen atmosphere. The heating time is about 40 to 50 seconds. As a result, an oxide film having a thickness of 1.5 nm grows on the surface of the silicon substrate 10. According to such thermal oxidation, a crystalline oxide film (crystalline silicon dioxide film) 15 is epitaxially grown on the terrace 12 as shown in FIG. The epitaxially grown crystalline oxide film 15 has a crystal structure reflecting the surface crystal structure of the terrace 12.

  When the misorientation angle 13 is small as in the present embodiment, since the step interval is wide, a film-like crystalline oxide film 15 that spreads two-dimensionally on the terrace 12 is formed. In step 12, the crystalline oxide film 15 epitaxially grown on the terraces 12 on both sides thereof grows laterally and is substantially connected. Each step 11 and terrace 12 of the silicon substrate 10 shows a form reflecting the structure of the step 11 and terrace 12 before the crystalline oxide film 15 is formed even after the crystalline oxide film 15 is formed.

  The thickness of the crystalline oxide film 15 depends on the substrate temperature and oxygen partial pressure during epitaxial growth, but when the thickness reaches about 2 nm, the growth rate of the crystalline oxide film 15 rapidly decreases. Therefore, the oxidation method used in this embodiment is suitable for forming a thin gate insulating film having a thickness of about 2 nm with good reproducibility.

According to normal thermal oxidation, a compressive stress is generated on the oxide film side of the silicon-oxide film interface due to the volume expansion of the silicon oxide film (the volume expansion of Si → SiO ₂ is 2.2 times), Tensile stress is generated on the silicon substrate side. On the other hand, when the crystalline oxide film 15 is formed, the epitaxial growth of the oxide proceeds based on the atomic structure of the silicon substrate 10, so that the stress of each part in the oxide balances, and the silicon substrate 10 and the crystalline oxide It is considered that no great stress is generated in the vicinity of the interface with the film 15. From the results of cross-sectional observation with a transmission electron microscope and electron diffraction, the crystalline oxide film 15 is considered to have a tridymite structure.

  When normal thermal oxidation is performed on a silicon substrate whose surface is not planarized at the atomic level, crystalline oxide may grow partially, but an amorphous oxide film grows in a large area. As a result, a single amorphous oxide film including a plurality of crystalline oxides is formed below. Therefore, a crystal-amorphous structure is substantially formed at the silicon / oxide film interface, and the influence of stress due to thermal expansion of the oxide reaches the substrate. When a large stress is generated in the vicinity of the silicon / oxide film interface, stacking faults and twins are generated to relieve the stress.

  On the other hand, in the case of this embodiment, the volume expansion of the crystalline oxide film 15 covering the surface of the silicon substrate 10 is extremely small and the crystal lattice continuity at the silicon / oxide film interface is maintained, so that stress is generated. Is significantly reduced. As a result, the occurrence of stacking faults and twins is suppressed. Further, if the oxidation process is continued even after the crystalline oxide film 15 is grown to a thickness of about 2 nm, an amorphous oxide film grows on the crystalline oxide film 15. Although there is a transition region between the amorphous oxide film and the crystalline oxide film 15, the surface of the silicon substrate remains covered with the crystalline oxide film 15.

  When such a crystalline oxide film 15 is used as a gate insulating film, there is no inconvenience that the bond at the silicon oxide film interface is easily broken by hot electrons, and the generation of interface states due to thermal expansion is eliminated. Therefore, the annealing process performed on the oxide film after the oxide film is formed becomes unnecessary. In addition, since the silicon / oxide film interface has a crystal-crystal structure instead of the conventional crystal-amorphous structure, carriers in the inversion layer may receive random potential scattering at the discontinuous interface as in the past. Disappear.

  FIG. 6 (a) shows a cross section of the silicon-thermal oxide interface according to the present invention. As can be seen from FIG. 6A, there is no structural transition layer made of a suboxide layer between the crystalline oxide film 15 and the silicon substrate 10. Further, as can be seen from FIG. 6B, the energy level 71 of the conduction band and the energy level 72 of the valence electrons of the crystalline oxide film 15 are flat, and there is no reduction in the band gap due to the bending of the energy level. In addition, according to the present invention, problems due to non-uniform film thickness and increased interface roughness are also eliminated.

  In general, even if a phase change occurs from amorphous to crystalline due to heat, no phase change occurs from crystalline to amorphous. Since the silicon / oxide film interface of this embodiment has a crystal-crystal structure, it can be said that it is thermally stable.

  Next, after depositing a polysilicon film by a CVD method, the polysilicon film is patterned using a lithography technique to form a gate electrode 16 shown in FIG. Next, the source 20 and the drain 21 are formed in the silicon substrate 10 using an impurity doping technique. Thereafter, the same process as that of a normal MOS transistor is performed to complete the semiconductor device.

  When a predetermined voltage is applied between the silicon substrate 10 and the gate electrode 16 in the MOS transistor thus obtained, an electric field perpendicular to the surface of the silicon substrate 10 is formed, and the crystalline oxide film 15 and the silicon substrate 10 A channel 17 shown in FIG. 1D is formed on the silicon side in the vicinity of the interface.

  In this embodiment, since the misorientation angle 13 is small and the step density is small, the interfacial scattering of carriers (electrons) in the channel 17 is extremely small regardless of the direction in which electrons travel with respect to the step, and the mobility is low. Improved. Therefore, it is not necessary to define the positions of the source region 20 and the drain region 21 so that the step 18 extends straight from the source region 20 to the drain region 21.

  The crystalline oxide film 15 can be observed by using reflection high-energy electron diffraction (RHEED). More specifically, the surface of the silicon 10 is irradiated with an electron beam at a minute angle during exposure to oxygen, and a pattern of a crystal surface structure that changes with the formation of an oxide film is obtained from a diffraction image of reflected electrons totally reflected. By in-situ observing the surface of the substrate during the oxidation treatment with RHEED, it is possible to grasp the structural change occurring on the surface of the substrate in real time.

  As described above, in this embodiment, an ultra-thin gate insulating film is formed from the crystalline oxide film 15 having a thickness of about 2 nm, thereby forming a MOS field effect type having a band structure as shown in FIG. A transistor is manufactured. According to the present embodiment, the problems of the prior art are solved, and highly reliable transistor characteristics are realized. Although this embodiment can be applied to a transistor having an ultra-thin gate insulating film having a thickness of 2 nm or less, a remarkable effect can be achieved. However, the present embodiment can also be applied to a transistor having a gate insulating film having a thickness exceeding 2 nm. Good. In that case, the above-described crystalline oxide film 15 exists below the gate insulating film, and an amorphous silicon dioxide layer exists on the crystalline oxide film 15. Even with such a structure, there is no suboxide layer at the silicon / oxide interface, and the band structure shown in FIG. 6B is realized, so that excellent transistor characteristics can be obtained.

  It is not necessary that 100% of the channel region of the silicon substrate is directly covered by the crystalline oxide film 15. Even when the plurality of crystalline oxide films 15 epitaxially grown on each terrace do not constitute one continuous insulating film, the effect of the present invention can be sufficiently obtained. If at least half of the channel region is directly covered by the crystalline oxide film 15, even if an amorphous oxide film is grown on the other region, the problem caused by the suboxide layer is reduced. It is possible to obtain sufficiently improved reliability as compared with the conventional MOS type heterostructure.

  An oxidation method other than the thermal oxidation method described in this embodiment may be used. The important point is that the surface of the silicon substrate is planarized at the atomic level. Even if the surface of the silicon substrate flattened at the atomic level comes into contact with the atmosphere and a thin natural oxide film is formed on the surface, a crystalline oxide film can be epitaxially grown on the surface of the silicon substrate by subsequent oxidation treatment. . This is true for other embodiments later.

(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (e).

  First, a (001) clean surface is formed on the (001) plane of the single crystal silicon substrate 30 by a vacuum heating cleaning method or a silicon homoepitaxial growth method. Also in this embodiment, a substrate having a misorientation angle 33 of 0 to 20 ° is used. In the present embodiment, a substrate having a larger misorientation angle than the substrate used in the first embodiment is used, but the misorientation angle 33 may be a small angle of 0 ° or higher.

  When surface treatment is performed on such a silicon substrate 30 by the above-described heat cleaning method in a vacuum or a homoepitaxial growth method of silicon, as described in the first embodiment, silicon is formed on the outermost surface of the silicon substrate 30. As the atomic rearrangement phenomenon proceeds, a step 31 and a terrace 32 are formed on the surface of the silicon substrate 30. The terrace 32 is flat at the atomic level.

  Next, the Si (001) -2 × 1 surface is oxidized using the method described in the first embodiment. In this embodiment, the silicon substrate 30 having a Si (001) -2 × 1 surface form obtained by heat cleaning treatment in vacuum is exposed to 800 ° C. dry oxygen gas in an electric furnace. At this time, the oxygen gas is highly purified by a refining machine, and the moisture is sufficiently removed by passing 100% high-purity dry oxygen gas through liquid nitrogen, and then supplied to the silicon substrate. In this way, as shown in FIG. 2B, a crystalline oxide film 34 (thickness: 1 to 2 nm) grows on each terrace 32 and is interconnected to obtain a two-dimensional film.

Next, in this embodiment, a tantalum oxide film 35 is deposited on the crystalline oxide film 34 as shown in FIG. Since the dielectric constant of the tantalum oxide film is about 6 times higher than that of the silicon oxide film (SiO ₂ ), even if a relatively thick tantalum oxide film 35 is used, the thickness is converted into an oxide film thickness. Is about 1/6 of the actual thickness of the tantalum oxide film. For this reason, the addition of the tantalum oxide film 35 contributes to the reduction of the leakage current while suppressing a substantial increase in the oxide film thickness. Since a very thin gate oxide film is used in this embodiment, the gate leakage current may increase unless such a tantalum oxide film 35 is provided.

The tantalum oxide film 35 is deposited as follows. That is, the silicon substrate 30 on which the crystalline oxide film 34 is formed is heated to 410 ° C. and kept in a steady state. Then, the tantalum oxide film 35 is grown until the film thickness becomes 15 nm by a CVD method using a mixed gas of Ta (OC ₂ H ₅ ) ₅ and O ₂ . Thereafter, annealing is performed in an inert gas at 800 ° C. for about 1 minute.

  Next, after depositing a polysilicon film using the LPCVD method, the polysilicon film is patterned to form the gate electrode 36 shown in FIG. Thereafter, the same process as that of a normal MOS transistor is performed to complete the semiconductor device.

  When a predetermined electric field is formed perpendicular to the silicon substrate surface, an inversion layer is formed on the silicon side of the silicon / oxide film interface, and a channel 37 is formed as shown in FIG.

  FIG. 2E shows a planar configuration of the MOS transistor according to the present invention. Each step 39 shows a form reflecting step 31 before the crystalline oxide film 34 is formed even after the crystalline oxide film 34 is formed.

  In this embodiment, as shown in FIG. 2E, the positions of the source region 40 and the drain region 41 are defined so that step 31 extends straight from the source region 40 to the drain region 41, and impurity doping is performed. . The electrons travel from the source region 40 toward the drain 41 along the arrow 39. In this case, carriers (electrons) in the channel travel in a smooth terrace at the atomic level without traversing step 38, so that the interface scattering of the carriers is extremely small.

(Embodiment 3)
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3A to 3F for a semiconductor device (flash memory) including a nonvolatile memory cell having a MOS type heterostructure of the present invention.

  First, a (001) clean surface is formed on the (001) plane of the single crystal silicon substrate 70 by a vacuum heating cleaning method or a silicon homoepitaxial growth method. In the present embodiment, a substrate having a misorientation angle 73 of 5 ° is used. When surface treatment is performed on such a silicon substrate 70 by the above-described heat cleaning method in vacuum or silicon homoepitaxial growth method, as described in the first and second embodiments, the outermost surface of the silicon substrate 70 As a result, the rearrangement phenomenon of silicon atoms proceeds, and a step 71 and a terrace 72 are formed on the surface of the silicon substrate 70.

  Next, the substrate 70 is heated at a temperature of about 750 ° C. in an electric furnace in a dry oxygen atmosphere to form a tunnel oxide film (first gate insulating film) having a thickness of 7 nm. Oxidation causes the crystalline oxide to epitaxially grow on the terrace 72 reflecting its crystal structure, and eventually a two-dimensionally continuous crystalline oxide film 75 is formed as shown in FIG. Although the thickness of the crystalline oxide film 75 depends on the substrate temperature and the introduced oxygen partial pressure, it grows only at most about 1 nm. In the present embodiment, the oxidation process is continued after the crystalline oxide film 75 is formed. By doing so, a tunnel oxide film 77 having a thickness of 7 nm is formed as shown in FIG. The tunnel oxide film 77 includes a crystalline oxide layer 75 having a thickness of about 0.7 nm at a portion in contact with the silicon substrate, and further includes an amorphous oxide layer 76 having a thickness of about 6.3 nm. . That is, the tunnel oxide film 77 has a two-layer structure.

  In this embodiment, even if the oxidation treatment conditions are kept constant, the phase of the tunnel oxide film 77 naturally changes from crystalline to amorphous due to stress relaxation. However, since the continuity of the crystal lattice is maintained at the silicon / oxide film interface, an energy band structure as shown in FIG. 6B is realized at the silicon / oxide film interface. This energy band structure is not significantly affected by the amorphous oxide layer 76 formed on the crystalline oxide layer 75. According to the method of the present embodiment, the influence of the volume expansion of the oxide film is reduced compared to the case where the oxide film is formed by normal thermal oxidation.

  Thus, since the silicon / oxide film interface has a crystal-crystal structure, even if the silicon oxide film includes an amorphous part, the vicinity of the silicon / oxide film boundary is caused by hot electrons injected into the floating gate. Therefore, there is no inconvenience that the bond is easily broken, and the generation of interface states due to thermal expansion is eliminated, so that the reliability of the tunnel oxide film can be improved and the life thereof can be extended.

  After the tunnel oxide film 77 is formed, an annealing process is performed in dry nitrogen in order to remove oxide film defects such as pinholes. Next, a floating gate 78 is formed on the tunnel oxide film 77 as shown in FIG. A control gate which is capacitively coupled by the oxide film 79 after forming an oxide film (second gate insulating film) 79 on the floating gate 78 using a normal thermal oxidation method, as shown in FIG. 80 is formed. When a predetermined electric field is formed in the vicinity of the MOS hetero interface thus obtained, an inversion layer is formed on the silicon side of the silicon / oxide film interface, and a channel 81 is formed.

  FIG. 3F shows a planar configuration of the nonvolatile memory. Although not shown in FIG. 3F, the floating gate 78 and the control gate 80 are arranged so as to overlap in the active region of the transistor. In the present embodiment, the positions of the source region 84 and the drain region 85 are defined so that a straight line connecting the source region 84 and the drain region 85 intersects the step 82 perpendicularly as shown in FIG. Impurity doping is performed. Therefore, the electrons travel from the source region 84 toward the drain 85 along the arrow 83. Therefore, the electrons in channel 81 will traverse step 82. This has the effect of increasing the efficiency with which hot electrons generated in the vicinity of step 82 are injected into the floating gate 78. This effect becomes more prominent because the step height increases as the misorientation angle 73 of the substrate increases.

  As described above, according to this embodiment, since the silicon / oxide interface has a crystal-crystal structure and does not have an unstable suboxide layer, a highly reliable nonvolatile memory can be obtained. Thus, the number of read / write operations of the nonvolatile memory can be improved. Since this effect does not depend on the magnitude of the misorientation angle of the substrate, the misorientation angle may be 0 °. Even when the amorphous oxide layer 76 is formed on the crystalline oxide layer 75, the silicon / oxide film interface maintains the crystal-crystal structure. The amorphous oxide layer 76 is more suitable for use as a gate insulating film of a nonvolatile memory.

  The effect when the present invention is applied to the nonvolatile memory is considered to be remarkable when the crystalline oxide film covers 90% or more of the region covered by the floating gate in the substrate surface. . This is because if the region where the surface of the silicon substrate is directly covered with the amorphous oxide film is widely present under the floating gate, the number of read / write operations is determined by the life of that portion. . Therefore, a configuration in which 90% or more of the region where the oxide film is covered with the floating gate is directly covered with the crystalline oxide film is preferable.

  On the other hand, from the viewpoint of improving carrier mobility and maintaining high reliability of the gate insulating film for a normal MOS transistor, 50% or more of the region covered by the gate electrode on the substrate surface Is preferably directly covered with a crystalline oxide film.

  The nonvolatile memory is a stack type in which the control gate is provided on the floating gate, but the present invention is also effective for a split type in which the control gate and the floating gate are arranged in the horizontal direction.

  In each of the above embodiments, a silicon substrate having a (001) plane orientation is used, but a substrate having another plane orientation may be used. In particular, when a Si (111) surface substrate is used, an atomic level smooth surface can be obtained relatively easily even by wet cleaning with an alkaline solution. / It is possible to form a terrace form.

  The semiconductor device of the present invention can operate at high speed and is excellent in pressure resistance and reliability, and is particularly useful as a nonvolatile memory or the like.

FIGS. 1A to 1D are process cross-sectional views illustrating a first embodiment of a method of manufacturing a semiconductor device according to the present invention. FIGS. 2A to 2D are process cross-sectional views showing a second embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2E shows a positional relationship between a source / drain region and a channel region. It is a top view. FIGS. 3A to 3E are process cross-sectional views showing a third embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 3F shows a positional relationship between a source / drain region and a channel region. It is a top view. 4 (a) to 4 (d) are process cross-sectional views for explaining a conventional method for manufacturing a MOS transistor. FIG. 5A shows a conventional MOS heterointerface, and FIG. 5B shows its energy band structure. FIG. 6A shows a MOS heterointerface according to the present invention, and FIG. 6B shows its energy band structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon substrate whose surface is (001) surface 11 Step on silicon (001) surface 12 Terrace on silicon (001) surface 13 Misorientation angle 15 Crystalline oxide film 16 Gate polysilicon electrode 17 Channel 18 Step position 19 Direction of carriers flow in inversion layer 20 Source 21 Drain 30 Silicon substrate whose surface is (001) plane 31 Step on silicon (001) surface 32 Terrace on silicon (001) surface 33 Misorientation angle 34 Crystalline oxide film 35 Tantalum oxide film 36 Gate polysilicon electrode 37 Channel 38 Step position 39 Flow direction of carriers in inversion layer 40 Source 41 Drain 51 Silicon semiconductor substrate 52 Gate oxide film 53 Gate electrode 54 Channel 55 Source 6 drain 57 side wall oxide film 70 silicon substrate whose surface is (001) surface 71 step on silicon (001) surface 72 terrace on silicon (001) surface 73 misorientation angle 75 crystalline oxide film 76 amorphous oxide film 77 Tunnel oxide film 78 Floating gate polysilicon 79 Gate oxide film 80 Control gate polysilicon electrode 81 Channel 82 Position of step before oxidation 83 Flow direction of carriers in inversion layer 84 Source 85 Drain

Claims (15)

A silicon substrate with steps and terraces on the surface;
A gate insulating film including a crystalline oxide film formed on the silicon substrate;
A gate electrode formed on the gate insulating film,
The silicon substrate has a source region and a drain region across the silicon substrate portion in contact with the gate insulating film,
The semiconductor device, wherein the silicon substrate portion in contact with the gate insulating film and the gate insulating film have a crystal-crystal structure. In claim 1,
The crystal-crystal structure is
The silicon substrate is single crystal silicon;
2. The semiconductor device according to claim 1, wherein the gate insulating film is a crystal film that is two-dimensionally continuous along the surface of the silicon substrate. In claim 1 or 2,
The semiconductor device according to claim 1, wherein the gate insulating film has a thickness of 2 nm or less. In any one of Claims 1-3,
The semiconductor device, wherein the gate insulating film further includes a dielectric film formed on the crystalline oxide film. In claim 4,
The semiconductor device according to claim 1, wherein a dielectric constant of the dielectric film is higher than a dielectric constant of silicon dioxide. In any one of Claims 1-5,
The semiconductor device characterized in that the misorientation angle of the silicon substrate is not less than 0 ° and not more than 20 °. In claim 1,
The semiconductor device, wherein the crystalline oxide film covers 50% or more of a region covered with the gate insulating film on the surface of the silicon substrate. In claim 1,
The semiconductor device according to claim 1, wherein the gate insulating film includes the crystalline oxide film and a tantalum oxide film formed on the crystalline oxide film. A silicon substrate with steps and terraces on the surface;
A gate insulating film including a crystalline oxide film formed on the surface of the silicon substrate;
A floating gate formed on the gate insulating film;
A control gate capacitively coupled to the floating gate;
The crystalline oxide film is a semiconductor device that covers 90% or more of a region covered with the gate insulating film in the surface of the silicon substrate. A process of forming a silicon substrate having a step and a terrace using a heat cleaning method while holding the silicon substrate in a vacuum,
Forming a crystalline oxide film on the surface of the silicon substrate by heating the silicon substrate in an oxygen atmosphere;
Forming a gate electrode on the crystalline oxide film;
Forming a source region and a drain region by doping impurities into the silicon substrate. In claim 10,
The method of manufacturing a semiconductor device, wherein the step of forming the crystalline oxide film is performed by supplying dry oxygen that has been passed through liquid nitrogen onto the silicon substrate. A process of forming a silicon substrate having a step and a terrace using a heat cleaning method while holding the silicon substrate in a vacuum,
Forming a crystalline oxide film by epitaxial growth on the terrace of the silicon substrate surface;
Forming a gate electrode on the crystalline oxide film;
And a step of forming a source region and a drain region by doping impurities into the silicon substrate. In claim 10 or 12,
The method for manufacturing a semiconductor device, wherein the crystalline oxide film is formed to a thickness of 2 nm or less. In claim 10 or 12,
After the step of forming the crystalline oxide film and before the step of forming the gate electrode, a dielectric film having a dielectric constant higher than that of the crystalline oxide film is formed on the crystalline oxide film. A method of manufacturing a semiconductor device, further comprising a step of depositing. In claim 10 or 12,
A method for manufacturing a semiconductor device, wherein a misorientation angle of the silicon substrate is not less than 0 ° and not more than 20 °.

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