JP2005332269A - Device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device capable of surely performing establishment of communication with a host while suppressing an increase in cost. <P>SOLUTION: In a USB device 100 performing communication by USB2.0 standard, in which High Speed mode is set via Full Speed mode, whereby communication is performed while recognizing the setting to the High Speed mode, the communication mode is set to High Speed mode by a mode setting means 30 until communication preparation with a host 200 is completed after inputting power supply. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a device that communicates with a host in a plurality of communication modes.

  As a device as described above, a USB device such as a printer or a storage device connected to a host such as a personal computer and performing communication with the host according to the USB (Universal Serial Bus) 2.0 standard (hereinafter referred to as USB2. (Referred to as 0 devices) is becoming widespread.

  The USB 2.0 standard is a high speed capable of high-speed data communication in the full speed mode (maximum transfer rate: 12 Mbps) and the low speed mode (maximum transfer rate: 1.5 Mbps) which are communication modes of the conventional USB 1.1 standard. There are three types of communication modes to which a mode (maximum transfer rate: 480 Mbps) is added. The USB 2.0 device that performs communication according to the USB 2.0 standard is ensured upward compatibility with a USB device that performs communication according to the USB 1.1 standard (hereinafter referred to as a USB 1.1 device). .1 devices can also be used as they are under a host that performs communication according to the USB 2.0 standard. In addition, the bidirectional communication performed between the USB 2.0 device and the host is performed via a pair of signal lines D + and D−, similarly to the bidirectional communication performed between the USB 1.1 device and the host. It is.

  Note that the High Speed mode compatible device, which is a USB 2.0 device, also supports the Full Speed mode in order to maintain compatibility with the USB 1.1 standard. When a device that supports High Speed mode is connected, the host operates in the Full Speed mode.

  In the host, the detection of the connection to the high speed mode compatible device is performed by pulling up the signal line D + on the high speed mode compatible device side in the same manner as the detection of the full speed mode compatible device connection. When recognizing that the signal line D + is pulled up, the host performs control (Chirp control) for detecting a device that supports High Speed mode after a predetermined time has elapsed (min 100 ms).

  The High Speed mode compatible device operates in the Full Speed mode at the initial time, and then shifts to the High Speed mode by the above-described control for detecting the High Speed mode compatible device.

  Therefore, when the high speed mode compatible device is physically connected to the host that has been previously powered on, when the power is turned on, the device needs to respond to the control from the host after a predetermined time has elapsed. However, depending on the device (high speed mode compatible device), there may be a case where a lot of initial setting time is required from when the power is turned on until communication with the host becomes possible. For example, there are cases where a lot of time is required for a power-on reset process for initializing the apparatus, and a case where a CPU mounted on the apparatus needs a lot of time for a process for reading firmware. In such a case, a case where it is not possible to respond to the control (communication request) from the host occurs. Then, although the apparatus is connected to the host and the power is turned on, there arises a problem that establishment of communication with the host fails.

  Thus, a technique has been proposed that includes a control circuit that controls the signal line D + to be connected to a power source when it can respond to a communication request from a host (see Patent Document 1 and Patent Document 2).

  Further, a latch circuit is set until it becomes possible to respond to a communication request from the host, the transistor is turned on by the latch circuit, the signal lines D + and D− are set to 0 V, and communication from the host is performed. A technique has been proposed in which a latch circuit is reset to turn off a transistor when it becomes possible to respond to a request (see Patent Document 3).

Further, a technique has been proposed that includes a circuit for turning off the power of the USB transceiver unit for driving the signal lines D + and D− until it becomes possible to respond to a communication request from the host (see Patent Document 4). ).
Japanese Patent Laid-Open No. 11-110097 JP-A-11-288338 Japanese Patent Laid-Open No. 11-245487 JP 2003-186484 A

  However, the techniques proposed in Patent Documents 1 and 2 described above require a control circuit that controls the signal line D + to be connected to the power source. The technique proposed in Patent Document 3 requires a latch circuit and a transistor for setting the signal lines D + and D− to 0V. Furthermore, the technique proposed in Patent Document 4 requires a circuit for turning off the power supply of the USB driver unit for driving the signal lines D + and D−. Therefore, there is a problem that the cost increases even when any technique is adopted.

  In view of the above circumstances, an object of the present invention is to provide a device capable of reliably establishing communication with a host while suppressing an increase in cost.

The device of the present invention that achieves the above object is connected to a host and has a predetermined first communication mode and a predetermined second communication mode with the host, and the second communication mode is In a device that performs communication in a plurality of communication modes that are recognized as being set in the second communication mode by being set after passing through the first communication mode,
Mode setting means for setting a desired communication mode from among the plurality of modes is provided, and the mode setting means changes the communication mode to the second communication mode until the communication preparation with the host is completed after the power is turned on. It is characterized by being set.

  The device of the present invention is a device that performs communication in which the host recognizes that the second communication mode is set by setting the second communication mode after passing through the first communication mode. The communication mode is set to the second communication mode until the communication preparation with the host is completed after the power is turned on. For this reason, even if a lot of initial setting time (period) is required from when the power is turned on until communication with the host becomes possible, the device is set to the second communication mode only during that period. It becomes. Therefore, during this period, no communication request is made from the host, and the device cannot respond to the communication request from the host as seen in the prior art, and the establishment of communication with the host fails. It will be resolved. Moreover, since the second communication mode is simply set to the existing second communication mode until the communication preparation with the host is completed after the power is turned on, a simple circuit configuration is sufficient, and the cost increase can be suppressed to a small level.

  Here, the device is a device that communicates with the host according to the USB 2.0 standard, and the mode setting means sets the communication mode to High until power-on and preparation for communication with the host are completed. It is preferable that the speed mode is set.

  A device that performs communication according to the USB 2.0 standard is set to the High Speed mode by setting the High Speed mode that is the second communication mode after passing through the Full Speed mode that is the first communication mode. Is a device that performs communication that is recognized by the host. For this reason, if the communication mode is set to High Speed mode until communication preparation with the host is completed after the power is turned on, no communication request is made from the host during that period, and therefore communication with the host is established. It can be done reliably. In addition, since only the existing High Speed mode is set, a simple circuit configuration is sufficient, and the cost increase can be reduced.

  According to the device of the present invention, it is possible to reliably establish communication with the host while suppressing an increase in cost.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a circuit configuration of a device according to an embodiment of the present invention.

  FIG. 1 shows a USB device 100 that performs communication using USB 2.0, a host 200 typified by a personal computer, and a USB cable 300 that connects the USB device 100 and the host 200.

  The USB device 100 includes an FS circuit 10 for a full speed mode (corresponding to an example of a predetermined first communication mode of the present invention) and a high speed mode (corresponding to an example of a predetermined second communication mode of the present invention). ) HS circuit 20, mode setting means 30, and power supply unit 40.

  The FS circuit 10 outputs voltage signals to the FS buffer 11 to which the power supply voltage 3.3V is input, the FS receiver 12 to which voltage signals from the signal lines D + and D− are input, and the signal lines D + and D−. The FS driver 13 is provided. Further, in the FS circuit 10, a resistance element 14 (pull-up resistance element Rpu) connected between the output side of the FS buffer 11 and the signal line D +, and one end thereof are connected to the signal lines D + and D−. In addition, resistance elements 15 and 16 (series resistance elements Rs) each having the other end connected to each connection point between the FS receiver 12 and the FS driver 13 are provided. Further, the FS circuit 10 includes an FS receiver 17 that receives a signal from the FS receiver 12 and an FS driver 18 that outputs a signal to the FS driver 13.

  On the other hand, the HS circuit 20 is provided with an HS receiver 22 to which voltage signals from the signal lines D + and D− are input, and an HS driver 23 that outputs voltage signals to the signal lines D + and D−. The HS circuit 20 includes an HS receiving unit 27 to which a signal from the HS receiver 22 is input and an HS driving unit 28 that outputs a signal to the HS driver 23.

  The mode setting unit 30 sets a desired communication mode from among the full speed mode and the high speed mode. The mode setting unit 30 performs communication until the communication preparation with the host 200 is completed after the power is turned on. The mode is set to the High Speed mode.

  The power supply unit 40 supplies power to the entire USB device 100.

  In addition, the host 200 is connected to the signal lines D + and D− and communicates with the USB device 100, and a resistor connected between the signal lines D + and D− and the ground GND. Elements 202 and 203 (pull-down resistance element Rpd) are provided.

  First, a connection sequence between the USB device 100 (hereinafter referred to as the USB device 101) that does not include the mode setting unit 30 and the host 200 will be described.

  FIG. 2 is a diagram showing a connection sequence between a USB device not equipped with mode setting means and a host.

  Here, it is assumed that the USB device 101 that does not include the mode setting unit 30 and the host 200 are connected by the USB cable 300 and only the power source of the host 200 is turned on. 2 represent the voltage levels of the signal lines D + and D− that are USB buses. At the first time point, the voltage levels of the signal lines D + and D− are both 0V.

  Here, the power supply of the USB device 101 is changed from the off state to the on state. Then, the USB device 101 sets the enable signal Rpu Enable of the FS buffer 11 to the “H” level, and applies a voltage of 3.3 V from the FS buffer 11 to the signal line D + via the resistance element 14 (Rpu). . As a result, the voltage level of the signal line D + is raised (pulled up) from 0V to 3.3V. Then, the USB host unit 201 provided in the host 200 recognizes that the USB device 101 is in the Full Speed mode. Next, the USB host unit 201 lowers (pulls down) the voltage level of the signal line D + to 0 V after 100 ms (min) has elapsed.

  Thereafter, the USB device 101 sets the enable signal HS Output Enable of the HS driver 23 to the “H” level, and raises the voltage level of the signal line D− from 0 V to 800 mV indicated by a broken line. As a result, the USB host unit 201 recognizes that the USB device 101 has shifted to the Chirp mode, which is a characteristic part of the USB 2.0 standard, and prepares to start access to the USB device 101. Next, after a predetermined time has elapsed, the USB device 101 sets the enable signal HS Output Enable of the HS driver 23 to the ‘L’ level, and lowers the voltage level of the signal line D− from 800 mV to 0V. Then, the USB host unit 201 continuously changes the signal lines D + and D− to 800 mV and 0 V.

  The USB device 101 inputs the voltage levels of the signal lines D + and D− changing in this way to the HS receiver 22 and confirms the Chirp mode. Next, the USB device 101 sets the enable signal FS Output Enable of the FS driver 13 to the “L” level. Then, the voltage level of 800 mV of the signal lines D + and D− is lowered to 400 mV. In this way, the mode shifts to the High Speed mode. In the High Speed mode, when the process of continuously changing the signal lines D + and D− from the USB host unit 201 to 400 mV and 0 V is completed, the voltage levels of the signal lines D + and D− both become 0 V.

  In the USB 1.1 standard, when the power is turned on and the signal line D + is pulled up to the “H” level, the full speed mode is set. On the other hand, when the power supply is turned on and the signal line D− is pulled up to the “H” level, the Low Speed mode is set. As a result, the host 200 distinguishes between the full speed mode and the low speed mode. Since the voltage levels of both the signal lines D + and D− are used in this way, the high speed mode added in the USB 2.0 standard is distinguished by the above-described sequence.

  As described above, when a certain USB device is connected to the host 200, the device lowers the 800 mV voltage level of the signal lines D + and D− to 400 mV, so that the device corresponding to the High Speed mode (according to the USB 2.0 standard). The host 200 recognizes that the device is a communication device).

  FIG. 3 is a diagram showing the state of the USB host unit in the connection sequence shown in FIG.

  In the USB host unit 201, as shown in FIG. 3, the resistance elements 202 and 203 (Rpd) are connected between the signal lines D + and D− and the ground GND in any of the full speed mode, the chirp mode, and the high speed mode. It is in a connected state (on state). Further, in the Full Speed mode, the Full Speed mode FS circuit 10 and the High Speed mode HS circuit 20 are in an active / inactive state. Further, in both the Chirp mode and the High Speed mode, the signal lines D + and D− are terminated to the ‘L’ level with respect to the FS circuit 10 and are in an active state with respect to the HS circuit 20.

  FIG. 4 is a diagram illustrating a state of the USB device in the connection sequence illustrated in FIG.

  In the USB device 101, in the full speed mode and the chirp mode, the resistance element 14 (Rpu) is pulled up with a voltage of 3.3 V (on state). On the other hand, in the high speed mode, the resistance element 14 (Rpu) is not pulled up with a voltage of 3.3 V (off state). In the full speed mode, the FS circuit 10 and the HS circuit 20 are in an active / inactive state. Further, in the Chirp mode, they are inactive and active. In the high speed mode, the FS circuit 10 terminates the signal lines D + and D− at the ‘L’ level, and the HS circuit 20 is in an active state.

  FIG. 5 is a diagram showing the states of the signal lines D + and D− in the connection sequence shown in FIG.

  The operating voltage levels of the signal lines D + and D− are 3.3 V, 800 mV, and 400 mV in the full speed mode, the chirp mode, and the high speed mode, respectively. In the idle state, the signal lines D + and D− are in the high and low states in the full speed mode. Moreover, in the Chirp mode and the High Speed mode, both are in the Low state.

  Here, in the USB device 101 that is not provided with the mode setting unit 30 described above, a power-on reset for initializing the USB device 101 or a CPU (not shown) mounted on the USB device 101 is used. An initial setting operation for reading the firmware is performed. Such an initial setting operation requires a relatively long time (for example, 1 second). For this reason, there is a case where it is not possible to respond to a communication request from the host 200. In this case, communication with the host 200 is established even though the USB device 101 is connected to the host 200 and the power is turned on. The case of failing occurs.

  Therefore, the USB device 100 according to the present embodiment includes the mode setting unit 30 that sets the communication mode to the high speed mode until the preparation for communication with the host 200 is completed after the power is turned on. . Hereinafter, a description will be given with reference to FIG.

  FIG. 6 is a flowchart of a processing routine for setting the communication mode to the high speed mode until the USB device shown in FIG. 1 is ready for communication with the host after the power is turned on.

  Here, as shown in FIG. 1, it is assumed that the USB device 100 and the host 200 are connected by a USB cable 300, and only the host 200 is powered on. In this state, the USB device 100 is powered on as shown in FIG. Then, in step S1, the mode setting means 30 sets the FS circuit 10 and the HS circuit 20 so as to operate in the high speed mode. Specifically, in the High Speed mode shown in FIG. 2, the voltage levels of the signal lines D + and D− are set to 0V. On the other hand, the USB host unit 201 constituting the host 200 is in the Full Speed mode. Here, as shown in FIG. 3, in the USB host unit 201, in the full speed mode, the HS circuit 20 for the high speed mode is in an inactive state, so that a problem such as signal collision does not occur.

  Next, in step S2, it is determined whether or not preparation is complete, that is, whether or not the initial setting operation has been completed. Note that a reset signal and other control signals can be used as the flag indicating the completion of preparation. If it is determined that the preparation has not been completed, step S2 is repeatedly executed. On the other hand, when it is determined that the preparation is completed, the procedure described with reference to FIG. 2 is executed.

  First, in step S3, the Full Speed mode is executed. Next, the Chirp mode is executed in step S4, and the high speed mode is executed in step S5. Then, it becomes an idle state.

  As described above, in the USB device 100 according to the present embodiment, when it is determined that the communication preparation is not completed, the mode setting unit 30 sets the high speed mode. With this setting, the host 200 recognizes that the power of the USB device 100 is not turned on. Therefore, the USB device 100 cannot respond to a communication request from the host 200, and the USB device It is possible to prevent the problem that the communication with the host 200 fails to be established although the 100 is connected and the power is turned on. Here, since the mode setting means 30 only sets the existing High Speed mode necessary for configuring the USB device 100 only during the period when the communication preparation is not completed, a simple circuit configuration is sufficient and the cost is increased. Can be kept small.

  In the present embodiment, the USB device 100 performs communication according to the USB 2.0 standard, and the mode setting unit 30 switches the communication mode to the High Speed mode until the communication preparation with the host 200 is completed after the power is turned on. However, the present invention is not limited to this, and the present invention is connected to a host and passes through the first communication mode with the host before entering the second communication mode. A device that performs communication in a plurality of communication modes that are recognized as being set to the second communication mode by being set, and sets the desired communication mode from the plurality of modes As long as the mode setting means to set the communication mode to the second communication mode until the communication preparation with the host is completed after the power is turned on.

It is a block diagram which shows the circuit structure of the device of one Embodiment of this invention. It is a figure which shows the connection sequence of the USB device which is not equipped with the mode setting means, and a host. It is a figure which shows the state of the USB host part in the connection sequence shown in FIG. It is a figure which shows the state of the USB device in the connection sequence shown in FIG. It is a figure which shows the state of the signal lines D + and D- in the connection sequence shown in FIG. 3 is a flowchart of a processing routine for setting a communication mode to a high speed mode until the USB device shown in FIG. 1 is ready for communication with a host after power-on.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 FS circuit 11 FS buffer 12 FS receiver 13 FS driver 14, 15, 16, 202, 203 Resistive element 17 FS receiver 18 FS driver 20 HS circuit 22 HS receiver 23 HS driver 27 HS receiver 28 HS driver 30 Mode Setting means 40 Power supply unit 100 USB device 200 Host 201 USB host unit 300 USB cable

Claims (2)

A predetermined first communication mode and a predetermined second communication mode are connected to and connected to the host, and the second communication mode is set after passing through the first communication mode. In a device that performs communication in a plurality of communication modes that are recognized as being set to the second communication mode,
Mode setting means for setting a desired communication mode from the plurality of modes is provided, and the mode setting means changes the communication mode to the second communication mode until the communication preparation with the host is completed after the power is turned on. A device characterized by being configured.   The device is a device that communicates with the host in accordance with the USB 2.0 standard, and the mode setting means sets the communication mode to the high speed mode until power-on and preparation for communication with the host are completed. The device according to claim 1, wherein the device is set.