JP2005323028A - Charge pump type phase comparator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump type phase comparator capable of canceling leak electric charges generated owing to parasitic capacity of a discharging/charging means constituting a main charge pump and nonlinearity of an element. <P>SOLUTION: The charge pump type phase comparator is constituted by providing a subordinate charge pump 982 with a discharging means having the same characteristics with discharging means 932 and 942 of a main charge pump 981, connecting current sources 973 and 974 having a common control terminal to both charge pump outputs, connecting the output of a differential amplifier to the common control terminal of the current sources, and connecting a subordinate charge pump output Vb to a positive-phase terminal and a main charge pump output Vo to a negative-phase terminal, the subordinate charge pump being driven with a reset signal 907 irrelevant to the phase difference of an input signal and its inverted signal. The current sources are so controlled to cancel variation in output Vb due to a leak of the subordinate charge pump through feedback control over the differential amplifier, and then the same current is supplied to the main charge pump as well to cancel a leak current of the main charge pump having the same characteristics. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a charge pump type phase comparator used in a PLL circuit of a wireless communication device.

  FIG. 4 shows a conventional charge pump type phase comparator. The conventional charge pump type phase comparator includes a phase difference detector 909 and a charge pump 910. The phase difference detector 909 includes D flip-flops 903 and 904 and an OR gate 908 including a NAND gate and an inverter. The charge pump 910 includes a charging unit 911 and a discharging unit 912 (see, for example, Non-Patent Document 1).

  The charging unit 911 includes a current source 913 and a switch 915, and the discharging unit 912 includes a current source 914 and a switch 916. The output current Io is a difference Io = I1−I2 between the current I1 of the charging unit 911 and the current I2 of the discharging unit 912, and drives an externally connected load. Normally, a loop filter, which is a component of the PLL circuit, is connected as a load, so that the load is capacitive. The currents Io, I1, and I2 are positive when flowing in the direction indicated by the arrow in FIG. 4 and negative when flowing in the direction opposite to the arrow. The same applies to FIGS. 1 and 7 described later.

  Here, the operation of the charge pump type phase comparator will be described with reference to FIG. The output of the phase difference detector 909 is determined in synchronization with the edges of the signals applied to the input terminals 901 and 902. In this configuration example, the operation is performed based on the falling edge. In FIG. 5, the horizontal axis t represents time.

  First, as indicated by A in FIG. 5, when an edge of a signal applied to the input terminal 901 (hereinafter simply referred to as “901 edge”) precedes, D is synchronized with this. The output of the flip-flop 903 is inverted, and then the output of the D flip-flop 904 is inverted in synchronization with the edge of the input terminal 902. When the outputs of both flip-flops 903 and 904 are inverted, the output signal 907 of the OR gate 908 is inverted and both flip-flops are reset (hereinafter, the output signal 907 of the OR gate 908 is referred to as a “reset signal”). Therefore, during a period Ta from when the output 905 of the D flip-flop 903 is inverted until reset is performed, the switch 915 is turned on, and the output current Io flows in the positive direction to charge the load.

  Next, as indicated by B in FIG. 5, when the signals are in phase with the input terminals 901 and 902 and the edges are aligned, the outputs of the D flip-flops 903 and 904 are simultaneously inverted and reset is performed instantaneously. Therefore, charging / discharging to the load is not performed.

  Finally, as indicated by C in FIG. 5, when the edge of the input terminal 902 precedes, the output of the D flip-flop 904 is inverted in synchronization with this, and then the D flip-flop is synchronized with the edge of the input terminal 901. The output of 903 is inverted. When the outputs of both flip-flops are inverted, the reset signal 907 of the OR gate 908 is inverted to reset both flip-flops. Therefore, during a period Tc from when the output 905 of the D flip-flop 904 is inverted until reset is performed, the switch 916 conducts, and the output current Io flows in the negative direction to discharge the load.

“RF Microelectronics”, written by Behzad Razavi, translated by Tadahiro Kuroda, Maruzen Publishing, 2002

  In the above-described conventional charge pump type phase comparator, when the charge / discharge means is configured by using an actual transistor, the current waveform may be blunted, overshoot, or undershoot due to parasitic capacitance or element nonlinearity. Actually, there is a problem that it does not become a beautiful square wave as shown in FIG. Further, such transient non-ideal characteristics usually differ between the rise and fall of the current waveform and between the charging means and the discharging means. In such a situation, even when the signals applied to the input terminals 901 and 902 are in phase, a problem is found that a small amount of charge or discharge is performed on the load and the charge leaks. .

  An example of such non-ideal characteristics is shown in FIG. For example, if the falling portion of the current I2 is dull as shown in the figure, it has been found that a certain amount of whisker 30 acts as a leak in the negative direction, that is, in the discharge direction, in the waveform of the output current Io. FIG. 6 is merely an example, and the same problem occurs with respect to the rising portion of the current I2 and the current I1.

  When a PLL circuit is configured using such a charge pump type phase comparator, feedback by the PLL is applied so as to cancel the leak, so that the lock is performed with the edges of the input terminals 901 and 902 of the phase difference detector 909 slightly shifted. To do. That is, there is a stationary phase error at the time of locking, and as a result, there is a problem that the comparison frequency component leaks as spurious and the frequency spectrum becomes undesired.

Some representative means of the present invention are as follows.
(1). The charge pump type phase comparator according to the present invention includes a phase difference detector for detecting a phase difference between the first and second input signals, and an amount of electric charge proportional to the detected phase difference to make the phase difference positive or negative. And a main charge pump comprising a first charging means and a first discharging means for charging or discharging a load according to the load, and a second charging means and a second discharging means having the same characteristics as the main charge pump. A sub charge pump; and first, second, third, and fourth current sources having control terminals connected in common to the output terminal of the main charge pump and the output terminal of the sub charge pump, respectively. The sub charge pump is driven by a constant signal and its inverted signal, and the control signal input to the control terminals of the first to fourth current sources is determined from the charge / discharge amounts of the charging means and the discharging means. Based on the difference between Characterized in that it is a feedback signal.

  (2). A PLL circuit according to the present invention includes a phase comparator, a loop filter that smoothes an output signal, a voltage-controlled oscillator that oscillates at a frequency corresponding to the loop filter output voltage, and a frequency-divided output of the voltage-controlled oscillator. A PLL circuit comprising a variable frequency divider that feeds back to the phase comparator, wherein the charge pump type phase comparator described in the above (1) is used as the phase comparator.

  (3). In addition, a wireless communication apparatus according to the present invention includes a PLL circuit, a mixer that up-converts an input signal, a bandpass filter that removes an image, a power amplifier that amplifies a transmission signal, and a component that separates a transmission signal and a reception signal. A wave filter, an antenna, a low-noise amplifier that amplifies a reception signal received by the antenna, a band filter, and a mixer that down-converts the output of the band filter. ) PLL circuit is used.

According to the present invention, since only the leakage charge, that is, the difference between the charge and discharge amounts of the charging means and the discharging means, is always output from the sub charge pump, feedback is performed to the control terminal of the current source so as to cancel this. The sub charge pump is in a steady state in a state where the amount of current flowing through the current source and the leakage charge are just balanced. Since an amount of current equal to that of the current source is also supplied to the main charge pump, the leakage charge generated in the main charge pump can be reduced as a result.
In the PLL circuit using the charge pump type phase comparator of the present invention, the stationary phase error is reduced, so that the frequency spectrum can be made good.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A first embodiment of the charge pump type phase comparator according to the present invention will be described with reference to FIG.
In this embodiment, the conventional charge pump type phase comparator shown in FIG. 4 is provided with a sub charge pump 920 comprising a charging means 921 and a discharging means 922, and the charging means 921 comprises a current source 923 and a switch 925. The discharge means 922 includes a current source 924 and a switch 926, respectively. The reset signal 907 is directly input to the control terminal of the switch 925 and input to the control terminal of the switch 926 via the inverter 971. Further, current sources 918, 919 and 928, 929 having a common control terminal are connected to the output terminal Vo of the main charge pump 910 and the output terminal Vb of the sub charge pump 920, respectively. This is a preferred embodiment when the impedance of the current sources 913, 914, 918, 919, 923, 924, 928, 929 can be set sufficiently high.

  Here, it is assumed that the main charge pumps 910 and 920 have the same characteristics. It is easy to realize such an identical characteristic on an integrated circuit. The propagation delay characteristics of the signal path from the phase difference detector 909 to the main charge pump 910 and the sub charge pump 920 are also the same.

  Next, the operation of FIG. 7 will be described with reference to FIG. The sub charge pump 920 is driven based on the reset signal 907 of the phase difference detector 909. Therefore, assuming that the current waveform has the non-ideal characteristics similar to those in FIG. 6, only the leakage charge is always supplied to the load capacitor 930 regardless of the phase difference of the input signals input to the input terminals 901 and 902. It will be supplied.

  Since this leakage charge (leakage due to the beard 30) acts to discharge the charge stored in the load capacitor 930, the output voltage Vb gradually decreases. At this time, since the gate-source voltage of the current source transistor 929 decreases, the current value I4 of the current source 929 decreases. As a result, the discharge amount decreases and the gate-source voltage of the current source transistor 928 increases, so that the current value I3 of the current source 928 increases and the charge amount also increases. Therefore, the sub charge pump 920 is stationary and steady in a state where the amount of charge by the current source 928, the amount of discharge by the current source 929, and the amount of discharge by leakage charge are balanced.

  At this time, the current source 918 and the current source 919 connected to the output of the main charge pump 910 are given the same gate-source voltage as the current source 928 and the current source 929, respectively. Leakage charges generated in the pump 910 can be canceled out.

  Next, a second embodiment of the charge pump type phase comparator according to the present invention will be described with reference to FIG. In this embodiment, the present invention is applied to a vertically asymmetric type charge pump. Since the phase difference detector connected to the main charge pump uses the same phase difference detector 909 as the conventional example of FIG. 4, it is omitted in FIG. Here, the capacitor 980 connected to the output terminal of the sub charge pump 982 is selected to have a sufficiently small value. Specifically, as shown in FIG. 10, when a PLL circuit is configured, about 1% to 0.1% of the total capacitance value of the loop filter (F) 12 is suitable.

  The main charge pump 981 includes a current source 973 and discharge means 932 and 942. The discharging unit 932 includes a current source 934 and a switch 936, and the discharging unit 942 includes a current source 944 and a switch 946. The sub charge pump 982 includes a current source 974 and discharge means 952 and 962. The discharging unit 952 includes a current source 954 and a switch 956, and the discharging unit 962 includes a current source 964 and a switch 966, respectively. The output signal 907 of the OR gate of the phase difference detector shown in FIG. 4, that is, the reset signal is input to the control terminal of the switch 956 of the discharging means 952, and the inverter 971 is connected to the control terminal of the switch 966 of the discharging means 962. An inverted signal of the reset signal 907 is input through the terminal.

  The output of the differential amplifier 972 is connected to the control terminals of the current sources 973, 974, the current source 973 of the main charge pump 981 is connected to the inverting input terminal of the differential amplifier 972, and the positive phase input terminal is connected to the positive phase input terminal. A current source 974 of the sub charge pump 982 is connected.

  Here, the discharge means 932, 942, 952, 962 and the current sources 973, 974 have the same characteristics. It is very easy to realize such an identical characteristic on an integrated circuit. The propagation delay characteristics of the path from the phase difference detector to the main charge pump 981 and the sub charge pump 982 are also the same.

  The discharging means 952 and 962 are driven by the reset signal 907 of the phase difference detector, and are repeatedly turned on and off alternately. For this reason, the discharging means 952 and 962 are energized with a certain amount of current in terms of DC. The current value Ib of the current source 974 is biased to a current value equal to that of the current sources 954 and 964 by feedback from the differential amplifier 972. Further, since the positive phase / inverted input terminals of the differential amplifier 972 are virtually short-circuited by a feedback action, the output terminal voltage Vb of the sub charge pump 982 becomes equal to the output terminal voltage Vo of the main charge pump 981. It will be set to such a voltage.

  Therefore, since the same gate-source voltage is applied to the current sources 973 and 974, the current sources 973 and 974 are biased with the same current value Ib. In addition, since the drain-source voltages are equal, even when the output impedances of the current sources 973 and 974 are not sufficiently high, the current value matching is very good.

  Since the output current Io of the main charge pump 981 is given by Ib-I1-I2, the waveform thereof is as shown in FIG. 2, which is similar in principle to the conventional example. Here, assuming the non-ideal characteristics of the current waveform of the main charge pump and assuming that the falling portions of the currents I1 and I2 are blunt as shown in FIG. 3, the output current waveform has a leakage in the discharge direction as shown in FIG. A certain amount of whiskers 30 acting as

  Since the sub charge pump 982 is driven by the reset signal 907, only the leak charge is always supplied to the capacitor 980 regardless of the phase difference of the input signals. Since the capacitor 980 is discharged by this leak charge, the voltage Vb equal to the output terminal voltage Vo of the main charge pump 981 drops for a moment, but returns to the voltage Vo again in a short time by feedback from the differential amplifier 972. . At this time, the capacitor 980 is charged through the current source 974, and the amount of charge is equal to the amount of leaked charge that has discharged the capacitor 980.

  Here, since the current source 973 is biased exactly the same as the current source 974, the charge that cancels the leakage charge supplied by the current source 974 is also supplied to the main charge pump 981 through the current source 973 as a result. It is possible to cancel the leak charge generated in the charge pump 981.

  Finally, simulation results of the circuit shown in FIG. 1 will be described with reference to FIGS. FIGS. 8 and 9 plot the voltage at the output terminal Vo when a capacitive load is connected to the output of the main charge pump 981 and the input of the phase difference detector is driven by an in-phase signal. That is, it is the result of evaluating the integrated value of the leak charge.

  FIG. 8 shows a case where the drive signals of the switches 956 and 966 of the sub charge pump 982 are fixed to the logic level and the leakage charge is not canceled, and corresponds to the case where the present invention is not applied. On the other hand, FIG. 9 shows the case where the reset signal 907 of the phase difference detector 909 is given to the switch drive signal to cancel the leakage charge, which corresponds to the case where the present invention is applied.

  The current source of the discharging means was set to 1600 microamperes, and the capacitive load connected to the output terminal Vo of the main charge pump was 7 nanofarads. The power supply voltage is 2.8V, and the initial voltage of the capacitive load is set to an intermediate potential of 1.4V. The phase difference detector is operated at two locations, 50 nanoseconds and 90 nanoseconds.

  In principle, charging / discharging is not performed for in-phase input, and the output voltage should not be constant, but in FIG. 8, discharge is performed each time the phase difference detector operates, and the output voltage is You can see how it descends stepwise. On the other hand, in FIG. 9, although the output voltage slightly increases, it can be confirmed that the voltage fluctuation is suppressed to be extremely small as compared with FIG. 8 because of the effect of canceling the leakage charge.

  In the embodiment shown in FIGS. 1 and 7, a MOS transistor is used as a current source. However, a bipolar transistor may be used. Further, the power supply and the ground, and the PMOS and NMOS transistors can be exchanged to realize a symmetric structure with respect to the power supply voltage. Instead of inserting the switch into the drain of the current source, it is also possible to insert it into the source.

  FIG. 10 is a circuit block diagram showing an example where the charge pump type phase comparator according to the present invention is applied to a PLL circuit. This PLL circuit divides the phase of the loop filter (F) 12 that smoothes the output signal, the voltage controlled oscillator (VCO) 13 that oscillates at a frequency corresponding to the loop filter output voltage, and the voltage controlled oscillator output fout. The variable frequency divider 11 is fed back to the comparator (PC) 10. The variable frequency divider 11 includes a prescaler (P) 14, a main counter (M) 16, and a swallow counter (S) 15, and the frequency division number can be switched by a frequency division number switching signal 17.

  Here, the charge pump type phase comparator according to the present invention shown in FIG. 1 or 7 is used as the phase comparator 10. In that case, the output of the frequency divider 11 is input to the input terminal 901 of the charge pump type phase comparator, and the reference signal (fref) is input to the input terminal 902. By using the charge pump type phase comparator according to the present invention for the phase comparator 10 of the PLL circuit, the leakage charge can be canceled, so that no stationary phase error occurs and leakage spurious of the comparison frequency component is prevented. In addition, a good frequency spectrum can be obtained.

  Further, in the fractional PLL operation in which the frequency division number switching signal 17 is switched at high speed in time series, not only the leakage spurious of the comparison frequency component but also the phase noise in the vicinity of the oscillation frequency can be reduced to obtain a good frequency spectrum. Can do.

  FIG. 11 is a circuit block diagram of a transmission / reception unit showing an example in which a PLL circuit using a charge pump type phase comparator according to the present invention is applied to a wireless communication device. The PLL circuit 105 having the configuration shown in FIG. 10, the mixer 106 for up-converting the transmission signal from the baseband processing unit (not shown) to the transmission frequency band, the band filter 107 for removing the image, and the band filter 107 are passed. A power amplifier 108 that amplifies a high-frequency transmission signal in the transmission frequency band, a duplexer 109 that separates the transmission signal and the reception signal, an antenna 101, and a high-frequency reception signal that is input from the antenna via the duplexer 109 The low-noise amplifier 102, the band filter 103, and the mixer 104 that down-converts the output of the band filter 103 into a frequency band processed by the baseband processing unit.

  In the wireless communication apparatus of the present embodiment, the leakage spurious included in the carrier frequency generated by the PLL circuit 105 is reduced by using the charge pump type phase comparator according to the present invention for the phase comparator constituting the PLL circuit. Therefore, the image component included in the output signal of the mixer 106 is very small. Therefore, it is possible to obtain an effect that the cutoff characteristic of the band filter 107 may be moderate or the band filter 107 itself becomes unnecessary.

  As described above, according to the present invention, the leakage charge generated due to the non-ideal characteristics of the main charge pump can be effectively canceled out. Therefore, when the charge pump type phase comparator according to the present invention is applied to the PLL circuit, it is possible to prevent leakage spurious of the comparison frequency component due to the occurrence of the stationary phase error and obtain a good frequency spectrum.

The circuit block diagram which shows one Example of the charge pump type | mold phase comparator which concerns on this invention. FIG. 2 is an operation waveform diagram of the charge pump type phase comparator of FIG. 1. FIG. 3 is an operation waveform diagram when assuming non-ideal characteristics of the charge pump type phase comparator of FIG. 1. The circuit block diagram of the conventional charge pump type | mold phase comparator. FIG. 5 is an operation waveform diagram of the charge pump type phase comparator of FIG. 4. FIG. 5 is an operation waveform diagram when assuming non-ideal characteristics of the charge pump type phase comparator of FIG. 4. The circuit block diagram which shows another Example of the charge pump type phase comparator which concerns on this invention. The simulation result when not canceling leak current with the charge pump type phase comparator of FIG. The simulation result in the case of canceling leak current with the charge pump type phase comparator of FIG. The circuit block diagram which shows an example at the time of applying the charge pump type | mold phase comparator which concerns on this invention to a PLL circuit. FIG. 11 is a circuit block diagram illustrating an example when the PLL circuit of FIG. 10 is applied to a wireless communication device. FIG. 8 is an operation waveform diagram of the charge pump type phase comparator of FIG. 7.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Phase comparator (PC), 11 ... Variable frequency divider, 12 ... Loop filter (F), 13 ... Voltage controlled oscillator (VCO), 14 ... Prescaler (P), 15 ... Swallow counter (S), 16 ... Main counter (M), 17 ... frequency division number switching signal, 30 ... beard, 101 ... antenna. DESCRIPTION OF SYMBOLS 102 ... Low noise amplifier, 103 ... Band filter, 104 ... Mixer, 105 ... PLL circuit, 106 ... Mixer, 107 ... Band filter, 108 ... Power amplifier, 109 ... Demultiplexer, 901, 902 ... Input terminal, 903 904 ... D flip-flop, 907 ... reset signal, 908 ... OR gate, 909 ... phase difference detector, 910, 981 ... main charge pump, 911, 921 ... charging means, 912, 932, 942 ... discharging means, 901, 902 ... Input terminal, 913, 914, 918, 919 ... Current source, 915,916,925,926 ... Switch, 920,982 ... Sub charge pump, 923,924,928,929 ... Current source, 934,944,954 964 ... Current source, 971 ... Inverter, 972 ... Differential amplifier, 973,974 ... Current source, 93 , 946,956,966 ... switch, 930,980 ... capacity, fref ... reference frequency, Io ... output current, electric I1, I2, Ib ... current, Vo, Vb ... output terminal.

Claims (12)

A phase difference detector for detecting a phase difference between the first and second input signals;
A main charge pump comprising a first charging means and a first discharging means for charging or discharging a load in an amount proportional to the detected phase difference depending on whether the phase difference is positive or negative;
A sub charge pump comprising a second charging means and a second discharging means having the same characteristics as the main charge pump;
A first, a second, a third, and a fourth current source, each having a control terminal connected in common to the output terminal of the main charge pump and the output terminal of the sub charge pump;
The sub charge pump is driven by a constant signal and its inverted signal,
The charge pump type phase comparison characterized in that the control signal input to the control terminals of the first to fourth current sources is a feedback signal based on the difference between the charge and discharge amounts of the charging means and the discharging means. vessel. The charge pump type phase comparator according to claim 1,
The charge pump type phase comparator characterized in that the constant signal is a signal unrelated to a phase difference between the first and second input signals. The charge pump type phase comparator according to claim 1,
The charge pump type phase comparator, wherein the first to fourth current sources, the first and second discharging means, and the first and second charging means are composed of MOS transistors. The charge pump type phase comparator according to claim 1,
The charge pump type phase comparator, wherein the first to fourth current sources, the first and second discharging means, and the first and second charging means are composed of bipolar transistors. The charge pump type phase comparator according to claim 1,
The phase difference detector includes a first D flip-flop connected to a first input terminal to which the first input signal is input and a second input terminal to which the second input signal is input. D flip-flop, an OR gate comprising a NAND gate and first and second inverters, the output of the first D flip-flop being the first charging means of the main charge pump and the OR gate The output of the second D flip-flop is connected to the first discharging means of the main charge pump and the second inverter of the OR gate, and the output of the OR gate is the first inverter. And a charge pump type phase comparator which is a reset signal of the second D flip-flop. The charge pump type phase comparator according to claim 5,
The charge pump phase comparator according to claim 1, wherein the reset signal is used as the constant signal for driving the sub charge pump. A phase difference detector for detecting a phase difference between the first and second input signals;
A first and a second discharging means for discharging a load of an amount proportional to the detected phase difference; and a first current source for always charging a constant amount of charge to the load. A charge pump,
A sub charge pump comprising third and fourth discharge means and a second current source having characteristics identical to those of the main charge pump;
A capacity connected to the output of the sub charge pump and charged and discharged by the second current source and the third and fourth discharging means;
A differential amplifier in which an output of the main charge pump is connected to a negative phase input terminal, and an output of the sub charge pump is connected to a positive phase input terminal;
The output of the differential amplifier is commonly connected to the control terminals of the first and second current sources, respectively, and the third and fourth discharging means of the sub charge pump are controlled by a constant signal and its inverted signal. Driven,
A charge pump type phase comparator, wherein an output difference between the main charge pump and the sub charge pump is fed back to the control terminals of the first and second current sources by the differential amplifier. The charge pump type phase comparator according to claim 7,
The charge pump type phase comparator characterized in that the constant signal is a signal unrelated to the phase difference of the input signal. The charge pump type phase comparator according to claim 7,
The phase difference detector has a first D flip-flop connected to a first input terminal to which the first input signal is input and a second input terminal to which the second input signal is input. 2 D flip-flops, an NAND gate and an OR gate having first and second inverters, the output of the first D flip-flop being the first charging means of the main charge pump and the OR Connected to the first inverter of the gate, the output of the second D flip-flop is connected to the first discharging means of the main charge pump and the second inverter of the OR gate, and the output of the OR gate is the first inverter. A charge pump type phase comparator characterized by being a reset signal for the first and second D lip flops. The charge pump type phase comparator according to claim 9,
The charge pump phase comparator according to claim 1, wherein the reset signal is used as the constant signal for driving the sub charge pump.   A phase comparator, a loop filter that smoothes the output signal, a voltage controlled oscillator that oscillates at a frequency corresponding to the loop filter output voltage, and a variable that divides the voltage controlled oscillator output and feeds back to the phase comparator. A PLL circuit comprising a frequency divider, wherein the charge pump type phase comparator according to claim 7 is used as the phase comparator. The PLL circuit according to claim 11, wherein
A PLL circuit characterized in that a value of a capacitor connected to an output of a sub charge pump constituting the charge pump type phase comparator is 0.1 to 1% of a total capacitance value of the loop filter.

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