JP2005323009A - Image processing apparatus and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus and an image processing method capable of repeated outputting, without requiring extra line memories. <P>SOLUTION: The image processor 100 comprises a line buffer 102 for storing input line data (input image signal) or intermediate data, and an operating section 103 for calculating the intermediate data or output line data of next line by reading out the input line data or intermediate data stored in the line buffer 102 and performing predetermined operation process, wherein output line data, obtained through operation process at the operating section 103, are stored in the line buffer 102 and the output line data stored in the line buffer 102 is repeatedly outputted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus and an image processing method, and more particularly to an image processing apparatus and an image processing method for repeatedly reading an input image signal that has been subjected to pixel density conversion at an arbitrary magnification.

  Conventionally, there is a projection method, for example, as a conversion method used in an image processing apparatus for converting a pixel density at an arbitrary magnification. An example of the algorithm will be described with reference to the conceptual diagram shown in FIG. FIG. 1 shows an example in which an image is reduced at a magnification of 71%.

  In FIG. 1, the width of the pixels in the array of the input pixels d0, d1, d2,... Is 1, and the density is d0, d1, d2,. On the other hand, the width of each pixel in the array of output pixels o0, 01, o2,... Is a reciprocal of magnification 0.71, that is, 1.41, and the density is o0, o1, o2,.

When the input pixel and the output pixel are arranged like a one-dimensional coordinate as shown in FIG. 1, the density of the output pixel is the average of the input pixels in the portion corresponding to the output pixel. For example, since the input pixel corresponding to the output pixel o0 is 41% of the entire pixel d0 and the pixel d1, the density o0 of the output pixel o0 can be obtained by the following Expression 1.

  Next, FIG. 2 shows a block configuration of a pixel density converter 900 according to a conventional projection method. In FIG. 2, processing in the sub-scanning direction is taken as an example, but processing in the main scanning direction can also be realized with the same configuration. FIG. 2 shows an example in which five line memories are used.

  As shown in FIG. 2, the pixel density converter 900 holds a plurality of lines of input image signals, and simultaneously supplies a signal in a corresponding column in the sub-scanning direction to the density calculation unit 906 as a reference image signal. To 905, a plurality of lines of input image signals, page synchronization signals, line synchronization signals, and magnifications are input, and based on these, a density calculation unit 906 that calculates a density after pixel density conversion, and a density calculation unit 906 And a page memory 907 for holding the result.

  Next, the operation of the pixel density converter 900 shown in FIG. 2 will be described. In this operation, the page synchronization signal is first activated, and then the input image signal is input to the density calculation unit 906 in synchronization with the line synchronization signal. At this time, the input image signal is directly input to the density calculation unit 906, the input image signal is delayed by one line through the line memory 901, and input to the density calculation unit 906, and the line memory 902 is input. Two lines delayed and input to the density calculator 906, three lines delayed by three lines via the line memory 903 and input to the density calculator 906, and four lines via the line memory 904 Some are delayed and input to the density calculator 906, and some are delayed by five lines via the line memory 905 and input to the density calculator 906. As described above, the continuous six pixels in the sub-scanning direction are input to the density calculation unit 906.

  The density calculation unit 906 calculates the density by the projection method by calculating the input image signal input directly or delayed based on the page synchronization signal, the line synchronization signal, and the magnification.

  Here, a detailed configuration of the density calculation unit 906 will be described with reference to the drawings. FIG. 3 is a block diagram illustrating a configuration of the density calculation unit 906. FIG. 4 is a timing chart when executing a reduction process with a magnification of 35.5% as an example.

  In the adder with enable 932 in FIG. 3, if the enable signal is active in synchronization with the rise of the line sync signal after the page sync signal becomes active, the reciprocal of the magnification is shown in the output of the adder with enable 932 in FIG. Add as follows. At the same time, the counter 933 counts the number of line synchronization signals after the page synchronization signal becomes active as indicated by the output of the counter 933 in FIG. The output of the adder 932 with enable is input to the integer / decimal separator and separated into an integer part and a decimal part (bn).

  The separated integer part is input to the exclusive or not 935. The exclusive or not 935 also receives a counter 933 output. The exclusive or not 935 compares the input positive number part and the count value, and if they match, activates the enable signal to the adder with enable 932 as shown in the signal waveform of FIG. If not, the enable signal is made inactive as shown in FIG.

  The separated decimal part (bn) is input to the an calculator 936. The magnification is also input to the an calculator 936. The an calculating unit 936 obtains the decimal part (an) of (magnification−b (n−1)) from the decimal part (bn) and the magnification.

  On the other hand, the coefficient selection unit 937 inputs a signal for selecting a coefficient to be given to one input to the multipliers 911 to 916 to the selectors 921 to 925 and outputs the outputs of the selectors 921 to 925 to an, 0, 1 Choose from. This coefficient selection is performed by the value of the output of the adder with enable 932 in FIG. If the increase in the integer part of the adder 932 with enable is 1, the number of input pixels necessary to obtain the output pixel density is two, and the integer part of the added value shown in the adder 932 with enable in FIG. If the increase is 4, the number of input pixels required to obtain the output pixel density is 5. If the required number of input pixels is 5, the multiplication coefficient for the input image signal is a fractional part (bn), the multiplication coefficient for the output of the line memories 901 to 903 is 1, and the output to the output of the line memory 904 is The multiplication coefficient is a fractional part (an), and the multiplication coefficients for the remaining line memories are zero. If the required number of input pixels is 6, the multiplication coefficient for the input image signal is a fractional part (bn), the multiplication coefficient for the output of the line memories 901 to 904 is 1, and the output to the output of the line memory 905 is The multiplication coefficient is a fractional part (an). The multiplier 911 multiplies the input image signal by the decimal part (bn), and the multipliers 912 to 916 multiply the outputs of the line memories 901 to 905 and the outputs of the selectors 921 to 925, respectively. The results of the multipliers 911 to 915 are added in the adder 917. Also, the addition result in the adder 917 is input to the multiplier 918 and multiplied by the magnification, whereby density calculation is performed by the projection method.

  However, when pixel density conversion is performed by the conventional projection method described above, as the conversion magnification becomes smaller, more clock-synchronized buffers and more arithmetic units for pixel density conversion are required. For example, the number of line memories in FIG. 2, the number of selectors and the number of multipliers in FIG. 3 increase, and the scale of the hardware configuration increases as the scale of the adder increases. Further, in the conventional pixel density conversion, the smaller the conversion magnification, the more problems are image quality degradation such as missing fine lines and blurred edges.

  As a prior art for solving such a problem, there is Patent Document 1 shown below. FIG. 5 shows a schematic configuration of a pixel density conversion apparatus 800 according to the conventional technique.

  As shown in FIG. 5, the pixel density conversion apparatus 800 controls the repetition processing of the density calculation unit 804 from an externally designated conversion magnification (hereinafter simply referred to as magnification), a page synchronization signal, and a line synchronization signal. A control unit 808, a selector 801 for switching and selecting the input image signal and the second and subsequent image signals of the repeated processing, and density conversion calculation by sequentially extracting three adjacent pixels from the image signal in the sub-scanning direction as reference pixels. A reference pixel extraction unit 802 that receives line memories 803 and 804 to be processed, and a projection method processing enable signal and a projection method that are supplied from the control unit 808 to the reference pixels sequentially extracted by the reference pixel extraction unit 802 A density calculation unit 805 that performs density calculation for pixel density conversion according to the set magnification, and a density calculation unit 805 A page memory 806 for storing the results, and a the edge enhancement unit 807 performs the filtering process of the edge enhancement for each iteration.

  In the above configuration, first, the magnification is input to the control unit 808. The control unit 808 obtains a combination of magnifications equivalent to the designated magnification by combining the magnifications within the range that can be converted by one processing of the density calculation unit 805, and the number of times corresponding to the number of magnifications in the obtained combination. The density calculation unit 805 is controlled to repeat the above process. For example, in a configuration in which density calculation is performed by referring to three pixels at a time, processing can be performed with one density calculation when the specified magnification is 50% or more, but once when the magnification is less than 50%. Processing cannot be performed with the density calculation. Therefore, in the conventional technology, when the magnification is less than 50%, a magnification equivalent to the designated magnification can be executed by combining a plurality of magnifications that can be processed by 50% or more. For example, when a magnification of 35.5% is designated, processing is enabled by subordinately combining 70% processing and 50% processing that can be processed by the density calculation unit 805.

For reference, for example, Patent Document 2 shown below discloses a technique for having a memory for holding basic data and performing repeated reading by address control.
Japanese Patent Laid-Open No. 11-17931 Japanese Patent Laid-Open No. 2-312357

  However, in order to carry out the reduction process in the sub-scanning direction by the projection method as described above, it is necessary to hold twice the amount of information as normal data in order to hold the intermediate data for calculation in line units. Therefore, in the prior art, in order to realize the repeated output processing in the main scanning direction, a line memory for holding the repeated output result is added for one line, which causes problems such as an increase in the size and cost of the apparatus. Was produced.

  Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide an image processing apparatus and an image processing method capable of repeatedly outputting without adding a line memory.

  In order to achieve such an object, according to the present invention, a line buffer for storing an input image signal or intermediate data, and an input image signal or intermediate data stored in the line buffer are read out and specified. An arithmetic processing unit that calculates intermediate data of the next line or an output image signal by executing the arithmetic processing of the output line, and outputs the output image signal obtained by the arithmetic processing by the arithmetic unit to the line buffer. The output image signal stored and stored in the line buffer is repeatedly output. By configuring so that the output image signal obtained as a calculation result is stored in the line buffer originally provided, it is not necessary to add a separate line memory for repeated output. Thereby, an increase in size and cost of the apparatus can be avoided.

  The invention according to claim 1 is configured such that, for example, the line buffer stores the output image signal in a memory area after the memory area in which the input image signal or intermediate data is stored. May be. By storing the output image signal for repeated output in the area after the input image signal or intermediate data to be calculated, the calculation means need only read in order when reading it, simplifying the processing. Can be

  The invention described in claim 1 may be configured such that, for example, the output image signal is accumulated in the line buffer by the number of repetitions. By accumulating the output image signal for the number of repetitions, it is possible to obtain repeated images simply by sequentially reading them at the time of output.

  According to a first aspect of the present invention, for example, as in the fourth aspect, the calculation means reduces the input image signal or intermediate data, and stores the output image signal obtained by the reduction process in the line buffer. It may be configured to. For example, in an application such as Print Club (registered trademark), the captured image is reduced, repeatedly processed, and output. The present invention is particularly effective when applied to such an application.

  According to a fifth aspect of the present invention, the intermediate data or output image signal of the next line is calculated by reading out the input image signal or intermediate data stored in the line buffer and executing a predetermined calculation process. An image processing method, the first step of storing the output image signal obtained by the arithmetic processing in the line buffer, and the second step of outputting the output image signal stored in the first step, And the first step stores the output image signal in the line buffer for a number of repetitions. By configuring so that the output image signal obtained as a calculation result is stored in the line buffer originally provided, it is not necessary to add a separate line memory for repeated output. Thereby, an increase in size and cost of the apparatus can be avoided.

  According to the present invention, it is possible to realize an image processing apparatus and an image processing method capable of repeated output without adding a line memory.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  First, Embodiment 1 according to the present invention will be described in detail with reference to the drawings. FIG. 6 is a schematic diagram illustrating a schematic configuration of the image processing apparatus 100 according to the present embodiment, particularly a configuration for executing the reduction process and the repetition process.

  First, as shown in FIG. 6A, an image processing apparatus 100 according to this embodiment includes multiplexers 101 and 104, a line memory (also referred to as a line buffer) 102, and a computing unit 103.

  For example, an 8-bit input image signal is input to the multiplexer 101 from the outside. The multiplexer 101 also receives the 8-bit output image signal output from the computing unit 103 and 16-bit intermediate data. The signal output from the multiplexer 101 is held in the temporary line memory 102. As shown in FIG. 6B, the line memory 102 has a configuration in which two 8-bit line memories 102a and 102b are combined. The computing unit 103 is computing means for performing at least image reduction processing. For this reduction processing, for example, reduction processing using density calculation by a projection method can be applied. Since this is the same as the prior art, a detailed description is omitted here.

  The computing unit 103 can repeatedly output the reduced image by processing the input data based on the following operation. The details will be described below with reference to the drawings. Note that the image signal output from the arithmetic unit 103 is output to the outside via the multiplexer 104.

  FIG. 7 shows an outline of the flow of repeated output processing by the arithmetic unit 103. FIG. 7 is a conceptual diagram for explaining a normal operation when repeated output is performed in the sub-scanning direction.

  FIG. 7A is a conceptual diagram showing the operation of the first line. As shown in FIG. 7A, in this operation, when an input image signal for the first line (hereinafter referred to as first-line input line data) is input, the line memory 102 receives the 8-bit input image signal. Dummy data is added to make a total of 16 bits, and then input to the arithmetic unit 103. Further, the second line input line data is also input to the computing unit 103. The computing unit 103 obtains an output image signal for the first line (hereinafter referred to as first-line output line data) by performing arithmetic processing on the input first-line input line data and second-line input line data. At the same time, intermediate data for calculating the second line (also referred to as line memory information; hereinafter referred to as second-line intermediate data) is generated. The output intermediate data is fed back to the line memory 102.

  FIG. 7B is a conceptual diagram showing the operation after the second line. In this description, the processing target line is the kth line (2 ≦ k ≦ n, k and n are positive integers). As shown in FIG. 7B, in this operation, the intermediate data generated immediately before, that is, the k-th line intermediate data or the k-th line input line data is input to the line memory 102. If the input data is input line data, dummy data is added to this as in the first line. When intermediate data or input line data is held in the line memory 102, this data is next input to the computing unit 103. Further, the next line (k + 1 line) input line data is also input to the arithmetic unit 103. The arithmetic unit 103 obtains k-th line output line data and generates k + 1-th line intermediate data by performing arithmetic processing on the k-th line intermediate data or the k-th line input line data and the k + 1-th line input line data. To do. The output k + 1-th line intermediate data is fed back to the line memory 102. However, when the k line is the last line (n line), the arithmetic unit 103 outputs only the output line data and does not output the intermediate data.

  Of the data generated as described above, output line data is output to the outside via the multiplexer 104.

  Here, as a reference, an example in which the reduction process in the sub-scanning direction is executed will be described with reference to the drawings.

  FIG. 8 is a conceptual diagram for explaining the operation when the reduction process is performed in the sub-scanning direction. As shown in FIG. 8, in this operation, when the first-line input line data is input, 8-bit dummy data is added to the line memory 102 to obtain a total of 16 bits. Entered. Further, the second line input line data is also input to the computing unit 103. The computing unit 103 generates second-line intermediate data by performing arithmetic processing on the input first-line input line data and second-line input line data. The output second line intermediate data is fed back to the line memory 102. At this time, the writing position of the intermediate data is the same as the reading position.

  Next, in this operation, the second line intermediate data held in the line memory 102 is input to the calculator 103 and the third line input line data is input to the calculator 103. The computing unit 103 obtains the third line output line data by computing the second line intermediate data and the third line input line data, and further generates intermediate data for computing the next line. The output intermediate data is fed back to the line memory 102. Thereafter, this operation is repeated until the last line. However, in the process of the last line, the arithmetic unit 103 outputs only output line data and does not output intermediate data. Therefore, the initial value for the next line process is input to the line memory 102.

  This operation will be described more specifically by taking as an example the case of performing a two-third reduction process in the sub-scanning direction. However, here, the description will be focused on the processing up to the fourth line. In this operation, first, as shown in FIG. 9A, when the first line input line data is input, 8-bit dummy data is added to the line memory 102. Note that this stage is only accumulation, and no output line data is generated.

  Next, as shown in FIG. 9B, the first line input line data held in the line memory 102 is input to the calculator 103 and the second line input line data is input to the calculator 103. . The computing unit 103 computes the first line input line data and the second line input line data, thereby obtaining the first line output line data and generating the second line intermediate data. The output second line intermediate data is fed back to the line memory 102.

  Next, as shown in FIG. 9C, the second-line intermediate data held in the line memory 102 is input to the calculator 103 and the third-line input line data is input to the calculator 103. The computing unit 103 computes the second line intermediate data and the third line input line data, thereby obtaining the second line output line data and generating the third line intermediate data. The output intermediate data of the third line is fed back to the line memory 102. However, since the reduction ratio is 2/3 in this example, the intermediate data for the third line is zero. Therefore, the line memory 102 holds 0 similar to the dummy data.

  Next, the operation of the fourth line is as follows. Since the reduction coefficient here is 2/3, the counter for managing the line becomes the initial value. Therefore, the fourth line is the same as the operation of the first line. That is, the fourth line input line data is stored in the line memory 102, but no output is generated. Thereafter, by repeating such an operation, an image reduced by 2/3 as a whole can be output.

  Next, an operation unique to the present embodiment when the sub-scanning direction reduction process and the sub-scanning direction repeated output process are executed will be described with reference to the drawings.

  FIG. 10 is a conceptual diagram for explaining an operation when performing reduction processing in the sub-scanning direction and repeatedly performing output processing in the sub-scanning direction. As shown in FIG. 10, in this operation, when the first line input line data is input, dummy data having the same number of bits is given to the line memory 102 and then input to the computing unit 103. Further, the second line input line data is also input to the computing unit 103. The computing unit 103 generates second-line intermediate data by performing arithmetic processing on the input first-line input line data and second-line input line data. The output second line intermediate data is fed back to the line memory 102. At this time, the writing position of the intermediate data is the same as the normal reading position.

  Next, in this operation, the intermediate data for the second line held in the line memory 102 is input to the calculator 103 and the input line data for the third line is input to the calculator 103. The arithmetic unit 103 performs arithmetic processing on the second line intermediate data and the third line input line data to obtain three lines of output line data, and generates intermediate data for calculating the next line. The output intermediate data and output line data are fed back to the line memory 102 as repetition intermediate data and repetition output line data. The feedback intermediate data that has been fed back is written into the line memory 102 from the same writing position as when there is no repeated output processing. On the other hand, the fed back repeat output line data is written immediately after the repeat intermediate data or repeat output line data write area. That is, in this embodiment, when the same image is output periodically and repeatedly, the output line data used for this repetition is held in an empty area of the line memory 102. Thus, in this embodiment, it is not necessary to provide an additional line memory for repeated output processing, and problems such as an increase in the size and cost of the apparatus can be solved. However, in the process of the last line, the arithmetic unit 103 outputs only output line data and does not output intermediate data. Therefore, the initial value for the next line process is input to the line memory 102.

  The above operation will be described more specifically by taking as an example a case where a reduction process of 2/3 in the sub-scanning direction and a quarter of the main-scanning direction is performed and an output process is repeatedly performed. In other words, the necessary number of pixels is secured by repeatedly using data with a small number of input pixels in the main scanning direction.

  In this operation, first, as shown in FIG. 11A, when the first line input line data is inputted, dummy data having the same number of bits is given to the line memory 102. Note that this stage is only accumulation, and no output line data is generated.

  Next, as shown in FIG. 11 (b), the first line input line data held in the line memory 102 is input to the calculator 103 and the second line input line data is input to the calculator 103. . The computing unit 103 computes the first line input line data and the second line input line data, thereby obtaining the first line output line data and generating the second line intermediate data. The output second line intermediate data and first line output line data are fed back to the line memory 102. As shown in FIG. 11C, the fed back second-line intermediate data is written into the line memory 102 from the same writing position as when there is no repeated output processing. On the other hand, the fed back first line output line data is written immediately after the second line intermediate data write area, as shown in FIG. 11C.

  Next, as shown in FIG. 11C, when the input of the second line input line data to the computing unit 103 is completed, two lines are stored in the area where the first line input line data is stored in the line memory 102. The eye intermediate data is overwritten, and the output line data of the first line is accumulated after that. Thereafter, as shown in FIGS. 11C to 11D, the first line output line data stored in the line memory 102 is read, and the operation of outputting the data without performing the operation is repeated. A plurality of output line data is accumulated in the line memory 102. Thereby, the repetitive output according to the present embodiment is realized.

  For example, the writing process of the output line data of the second line in FIG. 11C is not an essential configuration in this embodiment, and the same effect can be obtained even if it is deleted.

  With the configuration and operation as described above, according to the present embodiment, it is possible to output repeatedly without adding a line memory for holding a repeated output result. Further, the case where the reduced image is repeatedly output in the sub-scanning direction has been described as an example. However, the present invention is not limited to this, and the present invention is also applicable to the case where the reduced image is repeatedly output in the main scanning direction. can do.

  The first embodiment described above is merely one of the best modes for carrying out the present invention, and the present invention can be implemented with various modifications without departing from the spirit thereof.

It is a conceptual diagram which shows the example of an algorithm of the projection method in the case of reducing an image by 71% of magnification. It is a figure which shows the block configuration of the pixel density converter 900 by the projection method of a prior art. It is a block diagram which shows the structure of the density | concentration calculation part 906 by a prior art. As an example, it is a timing chart when executing a reduction process with a magnification of 35.5% using the density calculation unit 906. It is a block diagram which shows schematic structure of the pixel density conversion apparatus 800 by a prior art. 1 is a schematic diagram illustrating a schematic configuration of an image processing apparatus 100 according to a first embodiment of the present invention, in particular, a configuration for executing a reduction process and a repetition process. It is a figure which shows the outline | summary of the flow at the time of repeatedly performing an output process using the calculator 103 by Example 1 of this invention. It is a conceptual diagram for demonstrating the operation | movement at the time of performing a reduction process in the subscanning direction in Example 1 of this invention. FIG. 9 is a diagram for explaining the operation illustrated in FIG. 8 together with a specific example in the case of performing a two-third reduction process in the sub-scanning direction. It is a conceptual diagram for demonstrating the operation | movement at the time of performing a reduction process in the subscanning direction in Example 1 of this invention, and repeatedly performing an output process similarly in the subscanning direction. FIG. 11 is a diagram for explaining, together with a specific example, a case where the operation shown in FIG. 10 is reduced by two-thirds in the sub-scanning direction and by one-fourth in the main scanning direction, and further repeated output processing is performed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Image processing apparatus 103 Operation unit 102, 102a, l02b Line memory 101, 104 Multiplexer

Claims (5)

A line buffer for storing an input image signal or intermediate data, and an intermediate image or output image signal for the next line is calculated by reading the input image signal or intermediate data stored in the line buffer and executing a predetermined calculation process An image processing apparatus having a calculation means,
An image processing apparatus, wherein an output image signal obtained by an arithmetic processing by the arithmetic means is stored in the line buffer, and the output image signal stored in the line buffer is repeatedly output.   2. The image processing apparatus according to claim 1, wherein the line buffer stores the output image signal in a memory area after a memory area in which an input image signal or intermediate data is stored.   The image processing apparatus according to claim 1, wherein the output image signal is accumulated in the line buffer for the number of repetitions.   2. The image processing apparatus according to claim 1, wherein the arithmetic means reduces the input image signal or the intermediate data, and stores the output image signal obtained by the reduction process in the line buffer. An image processing method for calculating an intermediate data or an output image signal of the next line by reading an input image signal or intermediate data stored in a line buffer and executing a predetermined calculation process,
A first step of storing the output image signal obtained by the arithmetic processing in the line buffer;
A second step of outputting the output image signal accumulated in the first step,
In the first step, the output image signal is accumulated in the line buffer by the number of repetitions.

Images