JP2005317619A - Thin film transistor circuit structure and active multi-pixel indicating device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a thin type highly precise large screen indicating device by a thin film transistor circuit structure which can be formed by applying liquid polymer on a substrate, an active drive multi-pixel indicating device reduced in the number of component or a control signal for constituting a pixel, and the stepwise connection constitution of the indicating device. <P>SOLUTION: An organic thin film transistor circuit having a high integration degree is formed by employing a substrate with a conductive pattern formed on a cover lay having an opening wherein a conductive layer is exposed, and applying the liquid material on the opening section. In an active drive multi-pixel indicating device which retains a driving current by a capacitor between gate sources of a transistor connected in series to a light emitting element, the control signal or the components for each pixels are reduced by the employment of an MIM (Metal Insulator Metal) element or a transistor with a high threshold voltage or the constitution of a circuit. Further, a compound indicating device is constituted by connecting individual indicating devices stepwise and distributing indicating data based on a relative positional information. By combining the structures, the thin type highly precise large screen indicating device is realized. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a thin film transistor circuit structure, an active multi-pixel display device, and a connection of the display device.

  Current-driven light-emitting elements include LEDs and organic ELs. In recent years, blue and white light-emitting LEDs have been mass-produced, and LEDs are used in large outdoor screen display devices. In addition, organic EL is used for small display devices due to improvement in luminance and life. Unlike LCD, it is self-luminous and has excellent visibility. At present, it is used for large outdoor screens that are large but thick, thin and high-definition small-sized mobile phones, and organic EL displays that are about the size of a small TV. It is difficult to say that a thin, high-definition, large-screen display device using a drive type light emitting element has been realized.

There are three possible solutions. The first is the use of thin-film organic circuits that are thin and suitable for medium-sized areas. In particular, if organic EL and peripheral circuits can be formed by a method that does not use a vacuum device, such as an ink jet printer, it can be made thinner and more cost-effective than using discrete components. It can be suppressed. Of course, if there are a lot of control signals and circuit elements, the area of the light emitting part will be reduced, the number of pixels will be reduced, and the image quality will deteriorate. Second, the control signals for the pixels and circuit elements will be reduced by devising the control circuit. is necessary. In view of productivity and yield, the size of the display device is not too small, not too large, and an appropriate size is good. Therefore, as a third one, it is only necessary to connect a plurality of display devices having an appropriate size to make one large display device.
Although technologies related to these three issues have been proposed, it is difficult to say that each has been sufficiently solved.

Japanese Patent Application Laid-Open No. 2003-258265 proposes a circuit structure suitable for an organic semiconductor.
A thin film transistor having a source or drain, a semiconductor layer, a drain or source, an insulator layer, and a gate electrode over a substrate, wherein the source or drain is provided over part of the substrate, and the source or drain and substrate are Covering with a semiconductor layer, providing a drain or source over a part of the region corresponding to the source or drain on the semiconductor layer, covering the drain or source with an insulator layer, and the drain or source on the insulator layer A thin film transistor is proposed in which the gate electrode is provided in a region corresponding to the source where the drain or source overlaps the source or drain. By adapting the thickness of the thin film to the distance between the source and drain electrodes, an extremely narrow channel length can be manufactured without applying an advanced microfabrication technique.

  As a method of emitting light by gradation of a current-driven display element, there are a static method in which the lighting or on time is duty-controlled, and an active method in which a current value is latched for each pixel and light is emitted with a latched constant current. . In order to darken by static driving, it is necessary to control the lighting time with fine resolution, but since it cannot be controlled with finer resolution than the response delay of the circuit, fine gradation display is difficult. Furthermore, it is difficult to lengthen the lighting time because it is controlled in a time-sharing manner, and the light emission brightness is increased to make it brighter. However, if the current is increased to make it brighter, the lifetime is shortened accordingly. is there. A display device is used for a long time, and a light emitting time can be extended, and an active method with a long life is suitable. If the life is long enough, it can be used as lighting.

  Japanese Patent Laid-Open No. 2003-195810 proposes an active light emission control circuit. One pixel includes one organic EL element, three transistors, one capacitor, and four control lines (scanning line X, signal line Y, power source, and ground). A capacitor is connected between the gate and the source of the first transistor, and a second transistor for switching is connected between the gate and the drain, thereby forming a current latch circuit. This current latch circuit is connected in series with the organic EL element which is a light emitting element, and is connected to the signal line X via the third transistor for switching. The gates of the second and third transistors are controlled by the scanning line X. The second and third transistors are turned on by the signal line X, and a current is passed through the path of the current latch circuit, the third transistor, and the signal line Y to charge the capacitor. When the second and third transistors are turned off by the signal line X, the latched current flows through the path of the current latch circuit and the organic EL element to emit light.

Japanese Patent No. 3417326 proposes an LED display device having a plurality of LED units connected by a control bus for sequentially transferring data from the LED control device. Using a control bus having a data communication function provided between the LED units, a command for controlling the LED units is sent from the LED control device. Individual identification information different from that of other LED units is recognized and stored for each LED unit. By using the identification information, display data, brightness correction data, and various control data transferred to each LED unit are individually received and controlled for lighting.
JP 2003-258265 A JP 2003-195810 A Japanese Patent No. 3417326

  The thin film transistor disclosed in Japanese Patent Application Laid-Open No. 2003-258265 has a structure in which an insulator layer and a semiconductor layer are sandwiched between three electrodes of a gate, a source, and a drain. The transistor is actually formed in contact with the insulator layer covering the gate electrode, and the transistor is formed only at the boundary between the source electrode or the drain electrode and the semiconductor. Even in a region where a transistor is not formed, it is necessary to prevent a short circuit between the three electrodes with an insulator layer or a semiconductor layer. Therefore, when a gate electrode is provided on the substrate, the gate electrode and the substrate are covered with an insulator layer, and when a source or drain is provided on the substrate, the source or drain and the substrate are covered with a semiconductor layer. A region only for insulation spreads around the region where the transistor is formed, and the entire element is enlarged. When the region where the transistor is formed is viewed from above, the transistor is symmetric, and a plurality of symmetric transistors are formed at the same time. Space is used. It is difficult to form a high-density circuit.

  The display control circuit disclosed in Japanese Patent Laid-Open No. 2003-195810 has one organic EL element, three transistors, one capacitor, and four control lines (scanning line X, signal line Y and power supply, ground) per pixel. It consists of As the number of pixels increases, the effect of reducing parts and control lines per pixel is greater. In order to increase the definition of a display device using a plurality of light emitting elements, reduce the cost of materials, and increase the productivity, a circuit system with fewer peripheral components and fewer control signals is required.

  In the composite display device of Japanese Patent No. 3417326, individual identification information different from other LED units is recognized and stored for each LED unit, and various data are transferred to each LED unit by using the identification information to control lighting. ing. The identification signal is used for determining whether or not the transmitted data is addressed to the user. This is a method that can be performed only when the data to itself is received and the remaining data is sent to the LED unit at the subsequent stage, and the LED units are simply connected in a line and the transmission destination is one. When an individual display device is two-dimensionally combined to make an integrated display device, there are a plurality of destinations, so a method for determining the destination is necessary.

  Highly integrated thin film transistor circuit structure that can be formed by applying liquid polymer to the substrate, active drive multi-pixel display device with few component parts and control signals constituting the pixel, and hierarchical connection structure of display device Realize a thin, high-definition, large-screen display device.

A thin film transistor circuit with a high degree of integration can be formed by applying a liquid polymer to the substrate, which is useful not only for high integration of display devices but also for high integration of all organic transistor circuits. An active-driven multi-pixel display device with a small number of components and control signals constituting a pixel is effective not only for organic EL but also for high-definition and cost reduction of a display device using a current-driven light emitting element such as an LED. . The hierarchical connection structure of the display devices is effective not only for connecting current-driven elements but also for display devices using voltage-driven elements, and the entire display device can be easily enlarged.
These three types of technologies are sufficiently effective as individual technologies, but by combining them, it becomes easy to realize a thin, high-definition, large-screen display device.

Means for solving the problems of the present invention are as follows.
FIG. 1 shows a conceptual diagram of the first invention. 1 is a thin film transistor circuit formed on a substrate 1. The substrate 1 includes a light emitting element electrode layer 3, a light emitting layer 4, and a source electrode 5 formed on an insulating sheet 2 and covered with an insulating member 6. A first conductive pattern 7 is formed on the insulating member 6. The second conductive pattern 8 is formed, and the insulating member 6 has an opening 9 through which a part of the source electrode 5 is exposed. The opening 9 has a first substantially circular portion 10, a second substantially circular portion 12, and a constricted portion 11 that is a location where the first and second substantially circular portions are connected. Various thin films are formed on the opening 9 to constitute a circuit. The semiconductor layer 13 is formed on at least the constricted portion 11. The drain electrode 14 is formed over the first substantially circular portion and the constricted portion, and a part of the outer periphery thereof is positioned on the constricted portion. In order to prevent a short circuit between the source electrode 5 and the drain electrode, the semiconductor layer 13 may cover the first substantially circular portion 10, the source electrode under the first substantially circular portion may be eliminated, or insulation. The member 6 may cover the first substantially circular portion 10. The insulator layer 15 is formed on the second substantially circular portion 12 and the constricted portion 11, and the gate electrode 16 is formed on at least the constricted portion 11.

  On the constricted portion 11, the gate electrode 16 is in contact with the drain electrode 14 and the semiconductor layer 13 through the insulator layer 15. Below the semiconductor layer 13 is the source electrode 5. The semiconductor layer 13 conducts at a voltage applied to the gate electrode 16, and a current flows between the drain electrode 14 and the source electrode 5. An N-type transistor is formed when the semiconductor layer 13 is N-type, and a P-type transistor is formed when the semiconductor layer is P-type. If the upper and lower widths of the constricted portion are made parallel, the area of the transistor does not change as long as it is within the constricted portion even if the position of the drain electrode is slightly shifted to the left or right. When the position of the drain electrode is shifted up and down, the length of the outer periphery of the drain electrode on the constricted portion is slightly changed and the area of the transistor is also changed. However, since the width is the same, it does not change greatly.

  The threshold voltage of the transistor is adjusted by adjusting the thicknesses of the insulator layer 15 and the semiconductor layer 13. A transistor is formed over the opening 9, and the sidewall of the opening 9 prevents the semiconductor layer 13, the drain electrode 14, the insulator layer 15, and the gate electrode 16 from spreading, thereby reducing the size of the element. I can do it. The drain electrode is exposed on the first substantially circular portion 9 and connected to the first conductive pattern 7 on the insulating member 6. Similarly, the gate electrode 16 is exposed on the second substantially circular portion 12 and is connected to the second conductive pattern 8 on the insulating member 6. The drain electrode or the gate electrode itself may be enlarged and covered with a conductive pattern, or a conductive member may be applied and connected.

  There are no particular limitations on the materials of the semiconductor layer, drain layer, insulator layer, and gate layer, but a liquid organic material is directly ejected by inkjet or the like by using a polymer organic material dissolved in a solvent. be able to. The sprayed material spreads in a circular shape or an elliptical shape, and can be applied to a substantially circular opening. Development of high-molecular organic materials dissolved in solvents is currently underway, and xylene solutions of semiconductor polymers (F8T2), PSS aqueous dispersions of conductive polymers (PEDOT), and isopropyl alcohol solutions of insulator polymers (PVP). Etc. are known. In the future, including newly developed materials, select and use as appropriate. It may be formed by spin coating.

  For the formation of the light emitting element electrode layer 3, the source electrode 5, and the first and second conductive patterns 7 and 8 on the insulating sheet 2, a copper foil may be formed by photoetching as in the case of a normal electronic circuit board. Gold or the like may be vacuum deposited. The insulating member 6 is formed of polyimide or the like so that a plurality of openings are opened by photoetching or the like. If a photomask or the like is used, the entire substrate can be formed with high accuracy at a time. The light emitting layer 4 may be a single layer or a multilayer structure including a hole transport layer and the like. Since the source electrode 5 and the conductive patterns 7 and 8 are formed in advance on the substrate itself, the step of forming an electronic circuit on the substrate may be simply applying a liquid polymer. A vacuum device or the like is also unnecessary and can be manufactured with a simple device such as an ink jet printer. When forming a complicated circuit, the insulating member 6 and the conductive patterns 7 and 8 may be laminated.

FIG. 2 shows a conceptual diagram of the second invention. It is a thin film current mirror circuit.
In a thin film current mirror comprising a substrate, a second insulator layer 22, a semiconductor layer 23, a source electrode 24, a first insulator layer 26 and a gate electrode 25, the substrate comprises an insulating sheet 17 and a first drain electrode 18. And the second drain electrode 19 and the insulating member 20, and the first and second drain electrodes 27 and 28 are formed on the insulating sheet 17, and the insulating member 20 covers the insulating member 20. 1. There is an opening 21 through which the second drain electrodes 18, 19 are exposed.

  The first and second drain electrodes 18 and 19 face each other at the center of the opening portion 21, and the width of the opening portion 21 is parallel to the first and second drain electrodes 18 and 19 near the facing portion. In the vicinity of the facing portion, the first and second drain electrodes are exposed in a straight line having a parallel width. The first and second drain electrodes 18 and 19 are sufficiently spaced apart from each other, or the second insulator layer 22 is formed on the facing portion, so that the first and second drain electrodes 18 and 19 are securely connected. To separate. Further, the first and second drain electrodes are covered with the semiconductor layer, and a substantially circular source electrode larger than the first insulator layer and smaller than the semiconductor layer is formed thereon. A part of the outer periphery of the source electrode is on the first drain electrode, and the other part is on the second drain electrode. Since the first and second drain electrodes are parallel and the source electrode is substantially circular, regions on the first and second drain electrodes are symmetrical on the outer periphery of the source electrode.

  A first insulator layer larger than the source electrode and a gate electrode larger than the source electrode and smaller than the first insulator layer are formed on the source electrode. The gate electrode 25 and the first conductive pattern 27 are connected. The gate electrode 25 may be extended and connected to an ellipse, or a conductor layer may be added. Similarly, the source electrode 24 and the second conductive pattern 28 are connected. The source electrode 24 may be connected to extend in an ellipse in directions other than on the first and second drain electrodes, or a conductor layer may be added. Further, the first drain electrode and the gate electrode are connected. The gate electrode 25 may be enlarged and overlapped with the first drain electrode. Since the gate electrode 25 and the first conductive pattern 27 are connected, the first drain electrode 18 and the first conductive pattern 27 are connected. A conductor layer may be added between them for connection.

  In the region where the outer periphery of the source electrode 24 overlaps on the first drain electrode 18, the gate electrode 25 is in contact with the source electrode 24 and the semiconductor layer 23 through the first insulator layer 25, and below the semiconductor layer 23. Since there is a first drain electrode 18, the conduction of the semiconductor layer 23 can be controlled by the gate electrode 25, and a transistor is formed. Similarly, in the region where the outer periphery of the source electrode 24 overlaps on the second drain electrode 19, the gate electrode 25 is in contact with the source electrode 24 and the semiconductor 23 through the first insulator layer 25, and the semiconductor layer 23. Since there is the second drain electrode 19 below, the conduction of the semiconductor layer 23 can be controlled by the gate electrode 25, and a transistor is formed. The gate electrodes, insulator layers, source electrodes, and semiconductor layers of the two transistors are the same, the drain electrodes are the same, and the shapes are symmetric. Accordingly, transistors having substantially the same characteristics are formed. A current mirror circuit is formed by connecting the gate electrode and the drain electrode of one transistor. If the semiconductor layer 23 is N-type, it is an N-type current mirror, and if it is P-type, it is a P-type current mirror.

  The substrate can be easily formed by photoetching or the like. The circuit on the substrate can be formed by an irradiation type apparatus such as an ink jet printer by using a semiconductor polymer dissolved in a solvent, a conductive polymer, or an insulator polymer. Although it is necessary to form the source electrode in a circular shape, it can be easily formed in a circular shape if it is applied by inkjet. It may be formed by spin coating or offset printing.

FIG. 3a) shows a circuit diagram of the third invention, and b) shows a flow.
It consists of a plurality of row lines P4, P5, P6 from the row control means 29, a plurality of column lines P1, P2, P3 from the column control means 30, and a plurality of pixels 31, 32, 33 arranged in a matrix. It is a display device.
Each of the plurality of pixels 31, 32, and 33 includes a light emitting element LED1, 2, 3, a transistor Tr1, 2, 3, a capacitor C1, 2, 3, and a voltage generating element MIM1, 2, 3, and the light emitting element LED1, 2, 3 and the transistors Tr1, 2, 3 are connected in series, the capacitors C1, 2, 3 are connected between the gates and sources of the transistors Tr1, 2, 3 and the voltage generating elements MIM1, 2, 3 Is connected to the gates and drains of the transistors Tr1, 2, 3 and the voltage generating elements MIM1, 2, 3 are MIM elements or varistors. The MIM (Metal Insulator Metal) element is a diode with a metal / insulator layer / metal structure, similar to a varistor, with the characteristics of connecting the cathode of a Zener diode, and the applied voltage is threshold in both the forward and reverse directions. When the voltage is lower than the voltage, the flowing current is almost zero, and when the applied voltage is high, the current flows. An MIM element having a structure in which tantalum oxide is sandwiched between chromium and tantalum is used for switching of an active drive LCD circuit.

  One end of the plurality of pixels in the row direction is connected to the row line in parallel, the other end of the plurality of pixels in the column direction is connected to the column line in parallel, and the row control means is a constant current to the row line, or The column control means includes constant voltage output means to the column line. Control is performed by a first step of clearing the latch current, a second step of latching the set current, and a third step of holding the latch current and emitting light with the current.

  In the first step, a reverse bias is applied to the light emitting element of the pixel, and a constant voltage is output from the row line and the column line so that a voltage higher than the reverse threshold voltage is applied to the voltage generating element. In the second step, a constant current to be set for the pixel in the selected column is output from the row line, and a voltage that causes a voltage higher than the threshold voltage to be applied to the voltage generating element of the pixel in the selected column is applied to the selected column. Apply. In the third step, a forward bias is applied to the light emitting element of the pixel, but a voltage that only takes a voltage lower than the threshold voltage is output from the row line and the column line to the voltage generating element.

The control flow is shown in FIG.
1) 1st step (light extinction of pixel)
S1: The voltage of the column line is set higher than that of the row line, and a voltage higher than the reverse threshold voltage is applied to the voltage generating element.
A current flows in the reverse direction to the voltage generating element, the capacitor is discharged, the gate voltage of the transistor becomes negative, the current is turned off, and the light emitting element is turned off.
2) Second step (constant current latch to pixel)
S2: The voltages of all the column lines are set to voltages near the row line voltage.
-Since the applied voltage of all the pixels is small and only a voltage equal to or lower than the threshold voltage is applied to the light emitting element, all the pixels are turned off because no current flows.
S3: A constant current set for the pixel in the selected column is output to the row line.
S4: The voltage of the selected column line is made sufficiently lower than the voltage of the row line, and a voltage equal to or higher than the forward threshold voltage is applied to the voltage generating element.
The voltage generating element of the selected column is turned on, and a gate voltage necessary for flowing a constant current from the row line to the pixel transistor is charged in the pixel capacitor.
S5: S2 to S4 are repeated until all the columns are updated.
• Constant current is set for all pixels.
3) Third step (maintaining light emission)
S6: The voltage between the row line and the column line is set to a voltage in the vicinity of the voltage generated in the pixel during full light emission.
S7: Wait until the display content update time is reached. When the update time is reached, the process proceeds to S2.
-Lights up at the set current until the display update time is reached.
The above is the display procedure.

  In the first step, by sufficiently increasing the voltage of the voltage output means relative to the current voltage output means, the applied voltage of the voltage generating element MIM1 is increased, and the reverse leakage current of the light emitting element LED1 is reduced by the capacitor C1, The voltage flows through the voltage generating element MIM1, and the capacitor C1 is discharged. Since only the leakage current flows between the gate and the source, the capacitance of the capacitor C1 may be very small. By making the capacitance of the capacitor C1 very small, the time of step 1 which is a step for discharging the capacitor C1 can be made very short. The transistor Tr1 may be a MOS transistor having an insulated gate, and may be a silicon semiconductor transistor or an organic transistor.

In the second step, a constant current is input. Initially, since the gate capacitor C1 is discharged, the source and drain of the transistor Tr are turned off, and the drain voltage is high. Therefore, the voltage across the voltage generating element MIM1 is also high, and a current can flow. The drain voltage is determined by the sum of the voltage of the capacitor C1 and the voltage across the voltage generating element MIM1, and the transistor Tr1 is in the saturation region. Since the capacitor C1 is charged with the current from the voltage generating element MIM1 and the gate voltage rises, the transistor Tr1 is turned on. When the capacitor C1 is charged with a voltage necessary for flowing a source / drain current equal to the input current, no current flows through the voltage generating element MIM1, and the drain voltage of the transistor Tr1 is the gate voltage charged in the capacitor C1. The voltage drops to the determined voltage. Since the voltage across the voltage generating element MIM1 is reduced, the voltage generating element MIM1 is turned off.
When the voltage across the light emitting element LED1 at the maximum light emission is Vledmax, the gate voltage at that time is Vgmax, the source / drain voltage is Vsdmax, and the forward voltage at which the current of the MIM element starts flowing is Vthmim, , Vledmax + Vgmax + Vthmim are required, and the current-voltage output means must be able to maintain a constant current even at this voltage. It is sufficient that the voltage on which the constant current output is based is sufficiently high.

  In the third step, a constant voltage lower than that in the second step is output from the row line. Since the capacitor C1 is charged in the second step and the voltage is applied to the gate, a source current corresponding to the gate voltage flows and the light emitting element LED emits light. The transistor Tr1 is in the saturation region.

If the voltage at this time is Vcnt, Vcnt> Vledmax + Vsdmax and the MIM element must not be turned on in order to enable maximum light emission during use, and Vcnt <Vledmax + Vthmim. From the two equations,
(Formula 1)
Vledmax + Vthmim>Vcnt> Vledmax + Vsdmax
A voltage that satisfies
When charging in step 2 and when emitting light in step 3, the source-drain voltage is different, but the gate voltage is the same and is in the saturation region, so almost the same current flows.
Further, the parasitic capacitance of the voltage generating element itself such as the MIM element is made smaller than the capacitance of the capacitor between the gate and the source. The size is reduced, and the distance between electrodes and the material are used. Since it is sufficient that a current sufficient to charge and discharge the capacitor flows, the area of the MIM element may be small. Not only one light emitting element but also a plurality of LEDs may be connected in series.

Each pixel has a very simple configuration with one light emitting element, one transistor, one voltage generating element, one capacitor, and two control lines (row line, column line).
Conventionally known dynamic drive matrix also has two control lines, the row line and the column line, but current cannot be latched in the dynamic drive matrix, so the duty drive is performed, and high brightness is achieved. An excessive current was required, and an excessively short duty was required for low brightness.
In the present invention, an arbitrary current can be latched and the light emission time can be made long, so that an excessive current is not required, the deterioration is reduced correspondingly, and the life of the display device is extended.

4a) is a conceptual diagram of the second invention, and b) is a control flow. This is an active drive type display device that performs driving by latching a set current value for each light emitting element.
The display device includes a row control unit 34, a column control unit 35, and a plurality of pixels 36, 37 and 38. The row control unit 34 outputs a constant current or a constant voltage to the row lines P10, 11, and 12. The column control unit 35 outputs H and L signals to the column lines P7, 8, and 9.
Each pixel 36, 37, 38 is connected to the light emitting elements LED 4, 5, 6, the first transistors Tr 4, 6, 8 connected in series, and the gates and sources of the first transistors Tr 4, 6, 8. And capacitors C4, 5, 6 and second transistors Tr5, 7, 9 having a source connected to the gate of the first transistor Tr4, 6, 8 and a drain connected to the drain. The gates of the second transistors Tr5, 7, 9 are controlled by the column lines P7, 8, 9. A plurality of pixels are connected in the row direction and connected to the row lines P10, 11, and 12.

  In a voltage-driven transistor such as an enhancement type MOS transistor or an organic transistor, when the gate voltage is a predetermined voltage, a linear region in which the source / drain current increases approximately in proportion to an increase in the source / drain voltage, and beyond that, the source -Even if the drain voltage is increased, there is a saturation region where the source / drain current is constant. Furthermore, when the source / drain voltage can be taken freely, the source / drain current does not flow when the gate voltage is lower than the threshold voltage, and when the gate voltage is higher than the threshold voltage, the source / drain voltage increases, and the source / drain voltage exponentially increases. The drain current also increases.

  Considering the operation of the pixel 36, when the control signal P7 is H, the transistor Tr5 is turned on, the gate-drain between the transistor Tr4 is turned on, and the capacitor C4 can be charged / discharged. In this state, when a current is input from the outside, the capacitor C4 is charged, and the voltage becomes the gate voltage. When the gate voltage is low, the input current cannot flow between the source and the drain, but also flows into the capacitor C4, and the capacitor C4 is charged. When the gate voltage is high, a current larger than the input current can flow between the source and the drain, so that a current flows out from the capacitor C4, and the capacitor C4 is discharged. Therefore, the voltage at the boundary between the linear region and the saturation region is charged in the capacitor C4. Since the gate-drain is turned on, this voltage is the gate voltage and also the source-drain voltage.

When the control signal P7 is L, the transistor Tr5 is turned off, the gate-drain between the transistor Tr4 is turned off, and the capacitor C4 cannot be charged / discharged. If the voltage already charged in the capacitor C4 is the gate voltage, the source / drain voltage is sufficiently high and in the saturation region, the source / drain current becomes the source / drain current when the capacitor C4 is charged. If the source / drain voltage is low and is in the linear region, the source / drain current is reduced accordingly. If the source / drain voltage is zero, the source / drain current is also zero. The pixel has a function of latching the input current when the control signal P7 = H and holding the latched current when P7 = L.

  In the circuit of the fourth invention, a transistor having the following characteristics in the threshold voltage of the transistor with respect to the voltage across the light emitting element is further used. Consider a case where the pixel 37 holds a drive current and the current is latched in the pixel 36.

The voltage across the pixel 37 is the maximum when the light emitting element LED5 is driven at the maximum current value in use, the voltage across the pixel is Vpix, and the voltage across the light emitting element when emitting light at the maximum current value. When Vledmax and the source / drain voltage of the transistor are Vsdmax (Equation 2)
Vpix> = Vledmax + Vsdmax
The voltage across the pixel 36 is Vsd = Vgs, where Vsd is the source-drain voltage and Vgs is the gate-source voltage because the transistor Tr5 is turned on between the gate and drain of the transistor Tr4.

When the gate voltage Vgs at which the transistor starts to be turned on is Vth and the minimum light emission voltage at which the light emitting element starts to emit light is Vledth, the voltage is lowest when the light emitting element LED4 is driven at the minimum current value during use.
(Formula 3)
Vpix = Vledth + Vth

The two pixels are connected in parallel through the row line P10, and the voltage across the pixel 36 and the voltage across the pixel 37 are equal. If Equation 1 is established, the pixel 37 can hold light emission at the latched current, and if Equation 3 is established, the pixel 36 can be latched even at the minimum current value in use. Since each pixel is equivalent, if the expressions 2 and 3 can be satisfied at the same time, it is possible to latch the current in an arbitrary pixel while holding the latch current of the other pixels. From Equation 2 and Equation 3,
(Formula 4)
Vledth + Vth> = Vledmax + Vsdmax
That is, the voltage obtained by adding the light emitting element voltage at the minimum driving current in use and the threshold voltage of the transistor should be larger than the voltage adding the light emitting element voltage at the maximum driving current and the source-drain voltage of the transistor. For example, the current can be latched in an arbitrary pixel while holding the latch current of another pixel.

  In the light emitting element, the type and size of the light emitting element are determined from the necessary emission wavelength, necessary luminance, durability, and the like, and as a result, the minimum and maximum light emitting element voltages Vledth and Vledmax are also determined. Further, the source-drain voltage Vsdmax of the transistor when light is emitted at the maximum current value causes power loss and heat generation, and should be a small voltage. Therefore, it is relatively difficult to arbitrarily set the source-drain voltage Vsdmax of the transistor when the light-emitting element voltages Vledth and Vledmax and the maximum current value emit light.

  However, the gate voltage Vth at which the transistor starts to turn on can be set depending on the gate thickness and impurity concentration in both the silicon semiconductor transistor and the organic transistor. Even when the gate voltage Vth is increased, current flows only when charging / discharging the gate capacitor, so the increase in current consumption is slight. It is also suitable for an organic transistor manufactured by a printing method and having a thick gate and a high gate voltage Vth. The structure and characteristics of the light-emitting element change for each emission color, and the light-emitting element voltages Vledth and Vledmax may change. By increasing the gate voltage Vth accordingly, Formula 4 is satisfied for all emission colors. Can do.

  The current value set in the set current output means is the total current of a plurality of pixels, and the resolution required for each pixel is required. The set current output means has a resolution for each pixel and a resolution for the number of pixels. The resolution that combines

The control flow is shown in FIG.
1) Initial setting (all pixels off)
S8: Currents of all row lines are set to zero.
S9: Set all column lines to H and return to L.
Since the second transistors in all the pixels are turned on and no current is supplied from the row line, the current flowing through the first transistor is zero, the capacitors C1 and C2 are discharged, and the latch current becomes zero.
2) Pixel current latch S10: The current value of the pixel to be selected is updated, and the total current value of the pixels in the row direction is set to the row line.
S11: The selected column line is set to H and returned to L.
Since the control signal of the non-selected pixel is L, the current of the non-selected pixel is retained. The pixel in the selected column can latch the current value, and the total current value obtained by updating the current value of the pixel to be selected from the row line is output. Therefore, the current value updated in the pixel in the selected column is 1 flows through the transistor, and the capacitor is charged with a voltage corresponding to the current.
S12: S10 and S11 are repeated until the pixels in all the columns are updated.
S13: Wait until the update cycle is reached.
3) Clearing pixel current S14: The total current value of the pixels in the row direction in which the current value of the selected pixel is set to zero is set in the row line.
S15: The selected column line is set to H and returned to L.
Since the control signal of the non-selected pixel is L, the current of the non-selected pixel is retained. The pixels in the selected column can latch the current value, and since the total current value in which the current value of the pixel to be selected is set to zero is output from the row line, the current value of the pixel in the selected column is zero. No current flows through the first transistor and the capacitor is discharged.
S16: When S14 and S15 are repeated until the pixels in all the columns are updated, the process proceeds to S10.
The above is the display procedure.

  In the present invention, one pixel has one light emitting element, two transistors, one capacitor, and three control lines (signal line P and power supply, GND), and the number of components and signal lines is small. .

  FIG. 5 is a conceptual diagram of an active drive type display device connected to output signal shift means and driven by latching a set current value for each light emitting element in the fifth invention. The display device includes a display control unit 39, an output signal shift unit 41, and a plurality of pixels 43, 44. The display control unit 39 outputs a set current corresponding to the setting to the current transmission line 42. The output means 40 is included and the output signal shift means 41 is controlled.

  The output signal shift means 41 is a means having a plurality of output terminals and sequentially shifting the output values of the plurality of output terminals, and the output signal is equivalent to a shift register. In FIG. 5, serially connected flip-flop circuits D-FF1 and 2 are shown, but the output value of the output terminal may be sequentially shifted by a program of the CPU.

  Each pixel 43, 44 includes light emitting elements LED 7, 8 connected in series, a drive current latch circuit, and a voltage short circuit. The drive current latch circuit includes first transistors 10 and 13, capacitors 7 and 8 connected to the gates and sources of the first transistors 10 and 13, and sources and drains connected to the gates of the first transistors 10 and 13. Are connected to the drain of the flip-flop circuit, and the gate is controlled by the output of the flip-flop circuit. The voltage short circuit is a third transistor Tr12, 15 having a source and a drain connected to both ends of the light emitting elements LED7, 8, and the light emitting elements LED7, 8 according to the output of the flip-flop circuits D-FF1,2. The both-end voltage is limited to the emission start voltage or lower.

The plurality of pixels are connected in parallel, and one end connected in parallel is connected to the current transmission line 42.
In a state where the current of the set current output circuit is 0 and no light is emitted, the data output Do = L is set, the clock is output, and the outputs Q of all the D flip-flops are initialized to Q = L. Since the initialization can be performed without emitting light, the flip-flop circuit may not have a reset circuit. A period of one clock Do = H is set, a pulse is output from the clock CK, and Do = H is sequentially transmitted to the flop-flop. A pixel connected to the flip-flop of Do = H is a selected pixel, and a current for the pixel is output from the set current output circuit and transmitted to the selected pixel via a current transmission line.

  When the pixel 47 is selected, both ends of the light emitting element LED7 of the pixel 47 are short-circuited by the transistor 12, and further, the transistor Tr11 is also turned on between the gate and drain of the transistor Tr10. The voltage is almost as low as the gate voltage of the transistor Tr10. Since both the selected pixel and the non-selected pixel are connected in parallel, the voltage between both ends of the selected pixel is lowered by lowering the voltage across the selected pixel. Unlike the transistor of the fourth invention, the transistor used in the fifth invention is a general transistor, and the threshold voltage between the gate and the source is sufficiently lower than the light emission start voltage of the light emitting element.

For this reason, the voltage of the light emitting element of the non-selected pixel becomes equal to or lower than the light emission start voltage, and no current flows. A plurality of pixels are connected to the current transmission line, but since no current flows through the non-selected pixels, only the current desired to be latched by the selected pixels may be output from the set current output circuit. When the clock CK pulse is output and the selected pixel is changed to the pixel 48, the output Q of the D flip-flop D-FF1 of the previous pixel 47 becomes Q = L, the transistors Tr11 and Tr12 are turned off, and the current is latched. The set current of the set current output circuit is changed to a current value desired to be set in the newly selected pixel 48. When current is latched in all the pixels and all outputs of the flip-flops become L, all the transistors that short-circuit both ends of the light-emitting elements are also turned off, so that current can flow through all the light-emitting elements. The setting of the setting current driving circuit is set to be equal to or more than the total value of the currents of all the pixels. You may turn on the power directly.

The control flow is shown in FIG.
1) Initial setting S17: The output current of the set current output circuit is set to zero, the period of one clock is set to Do = L, and a clock for pixels is output.
・ The output of all D-FFs becomes L.
2) The current latch S18 for the pixel is set to Do = H for one clock period.
The first pixel 11 becomes the selected pixel.
S19: The current value to be set for the selected pixel is set to the set current output circuit and output for one clock.
The both ends of the light emitting element of the selected pixel are shunted, the voltage is lowered, the other pixels are turned off, and the current from the set current output circuit is latched by the selected pixel.
S20: 2) is sequentially repeated for each pixel. 3) Light emission retention S21: The total current of all the pixels is set in the set current output circuit.
・ All pixels emit light with latch current.
4) Display update S22: Wait until a predetermined cycle is reached.
S23: After setting the setting current output means to zero, the process proceeds to step S18.
The above is the display procedure.

  FIG. 6 is a conceptual diagram of a display device of an active matrix driving system according to the sixth aspect of the invention, wherein the pixels are composed of 4 parts and 3 lines. A plurality of row lines P19, 20, 21 from the row control means 45, a plurality of column lines 50, 51, 52, a plurality of pixel control lines P13, 15, 17 from the column control means 46, and arranged in a matrix. In the display device comprising the plurality of pixels 47, 48, 49 and the transistors Tr16, 17, 18 as a plurality of switch means, each pixel has a light emitting element LED 9, 10, 11 connected in series and a drive current latch circuit. The driving current latch circuit includes first transistors Tr19, 21, and 23, capacitors C9, 10, and 11 connected between the gates and sources of the first transistors Tr19, 21, and 23, and a first transistor Tr19. , 21, and 23, and second transistors Tr 20, 22, and 24 that switch between the gates and drains, and one end of the pixel is parallel in the row direction. Are connected to the row lines P19, 20, 21 and the other end of the pixel is connected to the column lines 50, 51, 52 in parallel in the column direction. The column lines 50, 51, 52 are connected to the switching circuit Tr16, The switching circuits Tr16, 17, and 18 are controlled by the control signals P14, 16, and 18 of the column control means, and are connected to the ground via 17 and 18, and are included in a plurality of pixels arranged in the column direction. The gates of the transistors are connected to the pixel control lines P13, 15, and 17.

There are three external terminals for each pixel: the source electrode of the first transistor, the cathode electrode of the light emitting element, and the gate electrode of the second transistor, but the source electrode is shared in the row direction as a row line, By sharing the cathode electrode in the column direction and the gate electrode in the column direction, the number of parts of the pixel is reduced.
Since the gate electrode controls whether the current is latched or held, and the cathode electrode controls whether or not the current flows, so that a plurality of columns of pixels are connected to the row line that outputs a constant current. In addition, the current can be latched only in the pixels of the selected column. Only in the selected column, it is sufficient that the gate is turned on to pass a current, and the non-selected pixel is not turned off to pass a current.

The control procedure is shown in FIG.
1) Initial setting (all pixels off)
S24: The switching circuit between the column line and GND is turned off, and all the pixels are turned off.
S25: All pixel control lines are set to L, and all pixels are made current latchable.
Since the current to the pixel is off, the capacitors C9, 10 and 11 are discharged.
2) Latch current to pixels S26: All pixel control lines are set to H, and all pixels are in a current holding state.
S27: The switching circuit between all the column lines and GND is turned off, and all the pixels are turned off.
S28: Set the current value to be set to the pixel of the column to be selected for all the row lines.
S29: The switching circuit between the selected column line and GND is turned on.
S30: The selected pixel control line is set to L, and the pixels in the selected column are made current latchable.
A current flows through the pixels in the selected column, and a voltage corresponding to the set current is charged in the capacitor of the current latch circuit.
S31: Repeat steps S26 to S30 to latch current in all columns.
3) Holding of lighting S32: All pixel control lines are set to H, and all pixels are set in a current holding state.
S33: The total current of the pixels connected to each row is set for all row lines.
S34: The switching circuits between all the column lines and GND are turned on, and all the pixels are turned on.
S35: Wait until a predetermined cycle is reached, and proceed to S26.
The above is the display procedure.

  The row line needs accuracy when latching current in each pixel. However, when all the pixels emit light, it is sufficient if a current equal to or more than the total current for one row can be passed, and accuracy is not necessary. You may short-circuit to the power supply. There are one light emitting element, two transistors, one capacitor, and three control lines (row line, column line, GND side line) per pixel, and the circuit is simple and control is easy.

FIG. 7 shows a conceptual diagram and communication data of a composite display device in which a plurality of individual display devices having a plurality of light emitting elements are connected. It is a composite display device in which a plurality of individual display devices 54, 60, 66 are connected, and each of the individual display devices 54, 60, 66 has an equivalent configuration. Receiving means 56, 62, 68, first transmitting means 59, 65, 71, second transmitting means 58, 64, 70, transmission data processing means 57, 63, 69, and a plurality of light emitting elements, respectively. 55, 61, 67. The first transmission means 59 in the first individual display device 54 is connected to the reception means 62 of the second individual display device 60, and the second transmission means 58 is received by the third individual display device 66. The composite display device 53 is configured by connecting to the receiving device 56 in the first individual display device 54 and the transmitting device 73 in the display control device 72.

74 shows the composite display data transmitted by the transmission means. The composite display data including the relative position information indicating the connection position of the individual display devices connected by the transmission means and the display data for the individual display devices for all the individual display devices sequentially connected by the transmission means is transmitted. The transmission data processing means of the individual display device that has received the transmission data receives its own display data from the received composite display data, and further replaces it with the relative position information viewed from each transmission means of the individual display device. Complex display data is generated and output from each transmission means.
Since there is no communication-dedicated bus that connects to all the display devices, and the individual display devices are directly connected to each other, the configuration is simple. Since a plurality of individual display devices can be connected, a composite display device can be configured not only in a straight line but also in a planar shape, and a large-screen display device can be easily realized.

Hereinafter, the present invention will be described with reference to the drawings. FIG. 8 shows an N-type thin film transistor, wherein a) is a top view and a cross-sectional view of the substrate, b) is a liquid polymer coating diagram, c) is a cross-sectional view, and d) is an equivalent circuit.

  As shown in FIGS. 8 a) and 8 c, a conductive layer 79, an insulating member 78, and a conductive pattern 86 are provided on the insulating sheet 80. The insulating member 78 has two substantially circular portions 75 and 77 connected to each other, has an opening with a constricted portion 76, and the conductor layer 79 is exposed. The insulating sheet is a polyimide resin sheet, a glass epoxy sheet, an insulating sheet such as paper phenol or a glass plate. The conductor layer 79 is a metal such as copper foil or gold, or an organic conductor layer.

  A copper foil may be formed by photoetching, a metal may be vacuum-deposited, or an organic conductor layer may be formed by chemical treatment. It is formed on the entire surface or in a shape corresponding to the circuit. If the display unit is connected to the control circuit or GND, the entire surface is solid, and if it is a row line or column line of the matrix display unit, it is formed in a plurality of lines. The conductive pattern 86 is similarly produced according to the circuit to be produced.

  A liquid polymer is applied on the substrate of FIG. 8a) to form an N-type thin film transistor. The N-type semiconductor layer 84 is formed from the substantially circular portion on the right side to the constricted portion at the center. On the N-type semiconductor layer 84, the drain electrode 85 is applied so that a part of the outer periphery is on the constricted portion from the substantially circular portion on the right side to the constricted portion. An insulating layer 81 is formed on the left substantially circular portion and the constricted portion. The gate electrode 82 is formed from the left substantially circular portion to the constricted portion. A source electrode (conductor layer) 79, an N-type semiconductor layer 84, a drain electrode 85, an insulator layer 81, and a gate electrode 82 are overlapped in the vicinity 83 of the boundary of the drain electrode of the constricted portion, and d) an NMOS transistor Tr25 is formed. . The width of the transistor Tr25 is secured by the width of the constricted portion 76, and even if the position of the drain electrode 85 is shifted left and right, it does not change as long as it is within the range of the constricted portion 76. When the position of the drain electrode 85 shifts up and down or changes in size, the width of the transistor Tr25 changes accordingly, but it is a portion close to a straight line and does not change so much.

  In addition to preventing the liquid polymer from spreading on the side wall of the opening, the conductive pattern is formed on the insulating member, so there is little wasted space. Furthermore, one transistor is formed in one constricted portion, and no extra transistor is formed. Therefore, the transistor is reduced in size accordingly.

A substrate electrode itself has a two-layer structure of a source electrode 79 and an electrode pattern 86, and wiring necessary for a circuit is provided in the conductor layer 79 and the electrode pattern 86 at the time of manufacturing the substrate. In FIG. 8, the source electrode is the electrode layer 79, and the transistor fabrication itself also serves as a connection between the source electrode and the peripheral circuit. Although the gate electrode 81 and the drain electrode 85 are not connected to the peripheral circuit at the time of transistor fabrication, they are exposed on the upper surface of the element and can be easily connected to the electrode pattern with a liquid conductor or the like. If it is the gate electrode 81, it can connect in arbitrary positions over the upper left lower side, and if it is the drain electrode 85, it can connect in arbitrary positions over the upper right lower side. By making the gate electrode 81 and the drain electrode 85 larger or making them elliptical, they can be directly connected to the conductive pattern.

  By using such a substrate and an element structure, not only the element itself is small, but also a circuit can be formed only by applying a liquid polymer. For the production of the substrate, it is easier to reduce the resistance value by using etching or vacuum deposition by increasing the thickness of the conductor layer or conductive pattern. Considering the function of the insulating member as the boundary of the liquid polymer, it is better to use the thicker than the liquid polymer, so it is better to use etching or vacuum deposition.

After the production of the substrate, etching and vacuum deposition are not necessary, and it can be produced by an ink jet printer. Of course, etching or vacuum deposition may be used.
Currently, a chip component is mounted on a generally wired printed circuit board to form a circuit. Although the wired board | substrate is used also in FIG. 8, application | coating of various liquid polymers respond | corresponds to mounting of the conventional component. Since there is no part to be soldered, it is in principle solder-free.

  FIG. 9 shows a P-type thin film transistor, wherein a) is a top view and a cross-sectional view of the substrate, b) is a coating diagram of the liquid polymer, c) is a cross-sectional view, and d) is an equivalent circuit.

  In contrast to the substrate of FIG. 8, in FIG. 9, the conductor layer 91 is only under this opening and is separated from the surrounding conductor layer 93. The rest is the same, and an opening made up of left and right substantially circular portions 87 and 89 and a constricted portion 88 is opened on the insulating member 90. The conductor layer 91 which is also the source electrode is connected to the electrode pattern 100 by the conductor layer 99 on the lower right side of the substantially circular portion. On the conductor layer 91, the P-type semiconductor layer 97 is applied to the right substantially circular portion and the constricted portion, the drain electrode 98 is applied to the right substantially circular portion and the constricted portion, and a part of the peripheral portion is constricted. It is above. The insulation increase 94 is applied to the left substantially circular portion, the constricted portion, and a part of the right constricted portion, and the gate electrode 95 is applied to the left substantially circular portion and the constricted portion.

  A source electrode (conductor layer) 91, a P-type semiconductor layer 97, a drain electrode 98, an insulator layer 94, and a gate electrode 95 are overlapped in the vicinity 96 of the boundary of the drain electrode of the constricted portion, and d) a PMOS transistor Tr26 is formed. . The width is restricted by the constricted portion 88, and a transistor having a stable size can be formed. Unlike FIG. 8, since the conductor layer 91 of the source electrode is separated from the periphery, a conductor layer 99 that is connected to the periphery is necessary. The conductor layer 99 can be arranged in any direction other than the constricted portion on the left side forming the transistor, and the degree of freedom of arrangement is great. The connection between the drain electrode and the surrounding conductive pattern is performed at a position other than the constricted portion and the conductor layer 99. If the P-type semiconductor layer 97 is an N-type semiconductor layer, an N-type thin film transistor is obtained.

  FIG. 10 shows a current mirror, in which a) is a top view of the substrate, b) a coating diagram of the liquid polymer, c) a cross-sectional view, and d) an equivalent circuit. On the insulating sheet 356, drain electrodes 117 and 118, an insulating member 355, and a conductive pattern 354 are formed, and the insulating member 355 has an opening. The opening 115 includes left and right substantially circular portions and a constricted portion therebetween. The left and right lengths of the constricted portion are longer than those in FIGS. 8 and 9, and the upper and lower boundaries 119 of the constricted portion are parallel. Under the opening 115, drain electrodes 117 and 118 are separated from the peripheral conductor layer 116. The drain electrode 117 extends from the substantially circular portion on the left to the center of the constricted portion, and the drain electrode 118 extends from the approximately circular portion on the right to the vicinity of the center of the constricted portion, and faces the center of the constricted portion.

  At the center of the constricted portion, the left and right drain electrodes 117 and 118 face each other, and the insulating layer 350 is applied to the portion where the insulating sheet 356 is exposed. A semiconductor layer 346 is applied thereon to cover the entire constricted portion. The source electrode 351 is applied so as to be larger than the insulator layer 350 and smaller than the semiconductor layer 346 so that the left and right boundary lines are on the constricted portion. An insulator layer 345 larger than the semiconductor layer 346 is applied thereon, and a gate electrode 348 larger than the source electrode 351 is applied.

  At the position of the left arc region 359 in the constricted portion, the boundary portion of the semiconductor layer 346 and the source electrode 351, the insulator layer 345, and the gate electrode 348 are overlapped on the drain electrode 117 to form the transistor Tr27. Even at the position of the arc region 360 on the right side in the constricted portion, the boundary between the semiconductor layer 346 and the source electrode 351, the insulator layer 345, and the gate electrode 348 overlap with each other on the drain electrode 118 to form the transistor Tr28.

  The layers forming the transistors Tr29 and 30 are common. Since the upper and lower boundary lines 119 of the opening in the constricted portion are parallel and the source electrode 351 is circular, the two arc regions 359 and 360 are mirror-symmetric even if the source electrode 351 is shifted left and right and up and down with respect to the constricted portion. It is. Since the shapes are mirror symmetric and the layers are common, the characteristics of the transistors Tr27 and 29 are equal.

  A conductor layer 353 is applied between the drain electrode 358 and the conductive pattern 354 to electrically connect them. Similarly, a conductor layer 349 is applied between the source electrode 351 and the conductive pattern 352 to electrically connect them. A conductor layer 347 is applied between the gate electrode 348 and the conductive pattern 343, and a conductor layer 120 is applied between the drain electrode 357 and the conductive pattern 343, and these three are electrically connected to each other, and the gate electrode of the transistor Tr27. And the drain electrode are connected. Since the source electrodes and gate electrodes of the transistors Tr27 and 28 are common and have the same characteristics, a current mirror is formed.

  Even without the insulator layer 350, the two drain electrodes 117 and 118 are separated, so that a current mirror is formed. However, the semiconductor layer 346 and the source electrode 351 come on the two drain electrodes 117 and 11, and the semiconductor layer 346 becomes an equivalent resistance depending on the voltage of the source electrode, and a high resistance is provided between the two drains. Could cause a short circuit. As shown in this figure, when the insulator layer 350 is disposed, the drain electrodes 117 and 118 are also completely insulated by the insulating sheet 356 and the insulator layer 350, and the interval between the drain electrodes 117 and 118 is reduced. Insulation can be ensured without fail. In the case where the insulator layer 350 is eliminated, the distance between the drain electrodes 117 and 118 is sufficiently wide to ensure insulation.

  FIG. 11 shows an inverter circuit, in which a) is a top view of the substrate, b) is a liquid polymer coating diagram, c) is a cross-sectional view, and d) is an equivalent circuit. Conductive layers 102 and 103, an insulating member 357, and a conductive pattern 344 are formed on the insulating sheet 358, and an opening is opened in the insulating member 357. The opening 101 is composed of three substantially circular portions and two constricted portions located between the substantially circular portions. The conductor layer 103 extends from the substantially circular portion on the right to the substantially circular portion at the center, and is separated from the other regions 102.

An N-type semiconductor layer 110 is applied to the left substantially circular portion and the left constricted portion on the conductor layer 102 which is also the source electrode, and the drain electrode 109 is applied from the left substantially circular portion to the left constricted portion. A part of the outer periphery of the drain electrode 109 is on the left constriction. A P-type semiconductor 361 is applied on the right substantially circular portion and the right constricted portion on the conductor layer 103 which is also the source electrode, and the drain electrode 362 is applied from the right substantially circular portion to the right constricted portion. A part of the outer periphery of the drain electrode 362 is on the right constricted portion. The insulator layer 111 is applied from the left substantially circular portion to the right substantially circular portion, and the gate electrode 112 is applied from the left constricted portion to the right constricted portion.

  In the left constricted portion, the N-type semiconductor layer 110, the drain electrode 109, the insulator layer 111, and the gate electrode 112 overlap on the source electrode 102, and the N-type transistor Tr 29 is formed in the arc region 106. In the right constricted portion, the P-type semiconductor layer 361, the drain electrode 362, the insulator layer 111, and the gate electrode 112 overlap on the source electrode 103, and the P-type transistor Tr 29 is formed in the arc region 107. The gate electrodes 112 are common to the transistors Tr29 and Tr30.

  A conductive layer 104 is applied between the drain electrode 109 and the conductive pattern 105 of the transistor Tr29, and a conductive layer 108 is applied between the drain electrode 362 and the conductive pattern 105 of the transistor Tr30, so that the drain electrodes of the two transistors are conductive. doing. Since the gate electrode and the drain electrode are conductive, the transistors Tr29 and 30 form an inverter circuit. The input gate electrode 112 is connected to the conductive pattern 113 by the conductive layer 114. The source electrode 103 of the transistor Tr30 is also connected to the electrode pattern 363 through the conductor layer 344.

  Since the insulator layer and the gate electrode are shared, the N-type transistor of FIG. 8 and the P-type transistor of FIG. 9 can be made smaller than simply connecting them with a conductive pattern. Since each electrode is in a substantially circular portion, the conductive patterns 104, 113, and 363 can be arranged and connected at arbitrary positions other than the constricted portion.

  FIG. 12 shows a NAND gate. a) is a top view of the substrate, b) is a coating diagram of the liquid polymer, c) is a sectional view, and d) is an equivalent circuit. The insulating member 144 is formed on an opening having five substantially circular portions 121 and four constricted portions 122 therebetween. The three substantially circular portions on the right side and the three constricted conductor layers 123 are separated from the conductor layers 124 in other regions.

  In the leftmost constricted portion, the N-type semiconductor layer 132, the conductor layer 133, the insulator layer 129, and the gate electrode 130 are overlapped on the conductor layer 124 that is also the source electrode, thereby forming an N-type transistor Tr31. In the second constricted portion from the left, the N-type semiconductor layer 132, the conductor layer 133, the insulator layer 134, and the gate electrode 135 overlap on the conductor layer 123 to form the N-type transistor Tr32. In the third constricted portion from the left, a P-type semiconductor layer 136, a source electrode 137 that is also a power source Vcc, an insulator layer 134, and a gate electrode 135 are overlapped on the conductor layer 123 to form a P-type transistor Tr33. In the fourth constricted portion from the left, the P-type semiconductor layer 136, the source electrode 137, which is also the power source Vcc, the insulator layer 138, and the gate electrode 141 are overlapped on the conductor layer 123 to form the P-type transistor Tr34.

  The NAND gate is formed by connecting the gate electrode 130 of the transistor Tr31 and the gate electrode 141 of the transistor Tr34 via the conductor layer 131, the conductive pattern 140, and the conductor layer 139. The first input of the NAND gate is the conductive pattern 140. The second input is a conductive pattern 126 connected from the gate electrode 135 via the conductor layer 126. The output is a conductive pattern 143 connected from the conductive layer 123 through the conductive layer 142. The source electrode (Vcc) 137 is connected to the power supply pattern 128 through the conductor layer 127. GND is the conductor layer 124. A plurality of substantially circular portions and a constricted portion are connected to serve as an electrode, a semiconductor layer, and an insulator layer, thereby reducing the overall size.

  As described above, a normal circuit can be freely designed by using the N-type transistor, the P-type transistor, the current mirror, the inverter, and the NAND gate which are the basic circuits of FIGS. In addition to simply connecting an N-type transistor and a P-type transistor, the size can be optimized by increasing the number of connected substantially circular portions as in an inverter or a NAND gate. Not only one-dimensional connection but also two-dimensional connection may be used. The size of the substantially circular portion may be changed according to the required output current value.

FIG. 13 shows an active matrix using voltage generating elements, where a) is a circuit diagram and B) is a flow chart.
Since each pixel has two terminals, the pixel portion has a passive matrix configuration. The display control means 146 for controlling the display device includes a high voltage power supply 149, a light emission power supply 150, a discharge power supply 151, and a set current output means 147. Further, the data Dx for controlling the D flip-flop in the column direction, the clock CKx, the data Dy for controlling the D flip-flop in the row direction, the clock CKy, and the control signals CTL1, 2, 3, 4 are output. The set current output means 147 includes a DA circuit 148, an operational amplifier OP1, a transistor Tr47, and a resistor R1. An analog voltage corresponding to the set digital value is output from the DA circuit 148, converted into a current value by an emitter follower circuit including an operational amplifier OP1, a transistor Tr47, and a resistor R1, and then output. The current value is a current obtained by dividing the analog voltage by the resistor R1.

  If such a circuit is made for the number of rows, the circuit scale becomes too large. In FIG. 13, the circuit is simplified by sequentially transmitting the output of one set current output circuit to each row. The row lines are connected to current / voltage output circuits 152 and 153, respectively. The current / voltage output circuit of each row includes D flip-flops 3 and 4, transistors Tr35 to Tr35, and capacitors C12 and C13. The voltages of the high voltage power supply 149 and the light emission power supply 150 are input and controlled by the row data Dy, the row clock CKy, and the control signals CTL2, 3,4. Since the other rows have the same configuration, a description will be given of the current-voltage output circuit 152.

The transistors Tr35, 36, and 37 are controlled by the negative output (Q-) of the flip-flop D-FF3. When the negative output (Q-) of the flip-flop D-FF3 = L, the transistors Tr35 and Tr36 are turned on. The transistors Tr36 and 37 and the capacitor C12 constitute a current latch circuit. A set current from the set current output circuit 147 is input via the transistor Tr35, and a voltage corresponding to the current is charged in the capacitor C12. When the output of the D flip-flop shifts and (Q −) = H, the transistors Tr 35 and 36 are turned off, and the latched current is held.

  When the control signals CTL2 = L, CTL3 = H, and CTL4 = L, the transistors Tr38 and 44 are turned on, and the set current is output to the row line. When the control signals CTL2 = H, CTL3 = L, and CTL4 = L, the transistors Tr39 and 45 are turned on, and the light emission power source 150 is connected to the row line. When the control signals CTL2 = H, CTL3 = H, and CTL4 = H, the transistors Tr40 and Tr46 are turned on, and GND is connected to the row line.

Each column line includes D flip-flops D-FF5 and 6, NAND circuits NAND1 and NAND2, and transistors Tr48, 49, 50, and 51, and is controlled by a column data output Dx, a column clock output CKx, and a control signal CTL1.
The source electrodes of the transistors Tr49 and 51 are connected to GND, the source electrodes of the transistors Tr48 and 50 are connected to the discharge power supply 151, the drain electrodes of the transistors Tr48 and 49, and the drain electrodes of the transistors Tr50 and 51 are connected to the column line. To do.

When CTL1 = H and D flip-flop input = H, the outputs of the NAND gates NAND1 and NAND2 become L, the transistors Tr48 and 50 are turned on, and the discharge power supply is output to the column line. At other times, the transistors Tr49 and 51 are turned on and connected to GND.

  The pixels 158 and 159 are connected to N-type enhancement type transistors Tr52 and 53, capacitors C14 and C15 connected between the gates and sources of the transistors Tr52 and 53, and gates and drains of the transistors Tr52 and 53, respectively. Voltage generating elements MIM4, 5 and light emitting elements LED13, 13 connected in series with the sources and drains of the transistors Tr52, 53. Each pixel is connected to a row line and a column line to form a matrix.

  The voltage generating element is an MIM element or a varistor, and the current that flows when the absolute value of the applied voltage is smaller than the threshold voltage in both the forward and reverse directions is substantially zero, and the current flows when the applied voltage is high. It is. It is an element that generates a voltage higher than the threshold voltage when a current flows.

  Pixel control consists of three steps. Since all the pixels have the same configuration, description will be made with the pixel 158. In the first step, a high voltage that is reverse biased is applied to the light emitting element LED12. As shown in FIG. 14B, the MIM element does not flow current when the applied voltage is lower than the threshold voltage, but current flows when the voltage becomes higher than the threshold voltage. When the reverse bias voltage is high, the reverse leakage current of the light emitting element LED12 flows through the path of the capacitor C14 and the MIM element MIM4, and discharges the capacitor C12. When the applied voltage of the MIM element becomes smaller than the threshold voltage, no current flows through this path. Since a voltage equal to or higher than the threshold voltage needs to be applied to both ends of the MIM element MIM3, the transistor Tr52 uses a transistor without a protection diode in which a current flows from the source to the drain.

  In the second step, a constant current is input, and the capacitor C14 is charged with a voltage corresponding to the input current. At the beginning of current flow, the voltage of the capacitor C14 is lower than the threshold voltage of the transistor Tr52, the transistor Tr52 is turned off, current flows through the path of the MIM element MIM4 and the capacitor C14, and the capacitor C14 is charged. The charging voltage of the capacitor C14 is the base voltage of the transistor Tr52, and the drain current increases exponentially as the base voltage increases. When the drain current becomes equal to the input constant current, all current flows between the drain and source, and the current in the path of the MIM element MIM4 and capacitor C14 stops. When a current flows through the MIM element MIM4, the sum of the voltage across the MIM element MIM4 and the charging voltage of the capacitor C14 is a drain-source voltage, but when the current to the MIM element MIM4 stops, the drain-source The voltage is determined by the balance between the characteristics of the current / voltage output means and the transistor Tr52. Since a constant current flows, the drain current is in a substantially constant saturation region with respect to the drain-source voltage.

  In the third step, the voltage applied to the pixel 158 is reduced, and the transistor 52 outputs a current corresponding to the voltage charged in the capacitor C14 to drive the light emitting element LED12. Although the drain-source voltage is lowered by lowering the voltage, as shown in FIG. 14a), as long as a voltage in a saturation region where the drain current is substantially constant with respect to the drain-source voltage is applied, the capacitor C12 is charged. A substantially constant current flows according to the gate voltage, which is a voltage.

Specifically, consider a case where the light emitting element is a blue LED and is driven at a maximum of 50 mA.
In step 1, as shown in FIG. 14b), the reverse threshold voltage of the MIM element is −4V, and the blue LED has a reverse bias and a leak current flows. Therefore, the reverse bias voltage to the pixel may be set to −4V or less. Since the capacitor is only discharged, the application time may be very short.

In Step 2, from FIG. 14b), the forward threshold of the MIM element is 4V, and from FIG. 14a), in order to pass a drain current of 50 mA, the gate voltage is 2V, and the forward voltage of the blue LED is 3.5V. Therefore, a constant current that can generate a voltage of 4 V + 2.3 V + 3.5 V = 9.5 V or more is output to the pixel.

  In the third step, the drain-source voltage need only be 2V. From FIG. 14b), the forward voltage of the blue LED is 3.5V, so the voltage between the current voltage output means 58 and the voltage output means 59 is 2V + 3.5V. Can be lowered to about 5.5V. As described above, by using the MIM element in which the current hardly flows below the threshold voltage, a two-terminal constant current latch light emitting circuit that accurately latches the input current value and drives the light emitting element with the current value can be realized.

  A varistor may be used for the voltage generating element. Since the leakage current when the reverse voltage is lower than the threshold voltage is larger than that of the MIM element, it leaks in the third step, the capacitor is easily discharged, the gate voltage is lowered, and the drain current of the transistor is easily reduced. . Increasing the capacitance of the capacitor or shortening the current value update cycle reduces the influence of the leakage current. A capacitor and a voltage generating element may be interchanged to form a P-type transistor instead of an N-type transistor.

The control flow is shown in FIG.
1) Initial setting (all pixels off)
S38: The control signals CTL2 = H, CTL3 = H, and CTL4 = H.
• GND connects to the row line.
S39: The control signal CTL1 = L and the column data Dx = H.
S40: Output pulses corresponding to the total number of stages in the column from the clock CKx.
The column line of the D flip-flop input D = H is connected to the discharge voltage 151, and the reverse bias of the discharge voltage is applied. As a result, a voltage equal to or higher than the reverse threshold voltage of the MIM element is applied, a current flows in the reverse direction, and the capacitor is discharged.
-By outputting pulses for all the stages of the columns, the latch currents of the pixels of all the columns are cleared, all the inputs D = L of the D flip-flops, the outputs of the NAND gates NAND1 and NAND2 become H, and the transistors Tr49, 51 turns on and all columns connect to GND.
2) Select pixels in the first column.
S41: Column data Dx = L and CTL1 = L for one clock.
The pixel in the first column is selected, but all columns are connected to GND because CTL1 = L.
3) Set current output means with current latch S42: Set control signals CTL2 = H, CTL3 = L, and CTL4 = L.
The transistors Tr38 and Tr44 between the set current output circuit and the row line are turned off.
The transistors Tr39 and 45 are turned on, and the voltage of the light emission power supply 150 is supplied to the row line.
・ All pixels emit light with the latched current. Pixels with zero latch current are turned off.
S43: The row data Dy is set to H for a period of one clock of the row clock CKy.
S44: The current to be latched in the pixels of the selected column is sequentially output in accordance with the output of the clock CKy.
-The current to be latched to the pixels in the selected column is set in the set current output circuit.
4) Latch current to the selected column of pixels.
S45: Set the control signal CTL3 = H.
・ The line is opened.
S46: The control signal CTL1 is set to H.
The output of the NAND gate of the column where the input of the D flip-flop = L becomes L, the NPN transistor is turned on, and only the selected column becomes GND. The non-selected column is a discharge voltage.
S47: Set the control signals CTL4 = L and CTL2 = L.
-The constant current set to the row line is output from the set current output circuit.
-A constant current having a voltage of (high voltage power supply-GND) is applied to the selected column. The MIM element is turned on, a constant current flows through the pixel, and the capacitor is charged with a voltage corresponding to the current.
-Only a voltage of (high voltage power source-discharge voltage) is applied to the non-selected column.
Since it is smaller than the threshold voltage of the MIM element, no current flows and the voltage of the capacitor is maintained.
S48: The control signals CTL2 = H, CTL1 = L, and CTL4 = H are set.
• All row lines are open and all column lines are connected to GND.
5) Latch current to all pixels.
S49: One pulse of the column clock is output.
・ The next column becomes the selected column.
S50: 3), 4), and 5) are repeated for the number of columns.
• Current is latched in all pixels.
6) Light emission until display update cycle S51: Control signal CTL3 = L.
Since all the row lines are connected to the light emission voltage and the column lines are GND, light is emitted with the set current.
8) Periodic update S52: 2) to 7) are periodically repeated.
The above is the display procedure.

  Each pixel has a very simple configuration with one light emitting element, one transistor, one MIM element, one capacitor, and two control lines (row line, column line). The conventionally known dynamic drive matrix also has two control lines, the row line and the column line. However, since the current cannot be latched in the dynamic drive matrix, duty drive is performed, and each pixel has a single line. The light emission time is short, and it has no choice but to emit light with high brightness, and a large current flows, which shortens the lifetime of the element. In the present invention, an arbitrary current can be latched, and the light emission time can be increased. Therefore, an excessive current is not required, and the life of the light emitting element can be extended correspondingly.

  FIG. 14C) shows a top view of the opening of the substrate and a cross section of the pixel portion formed by the thin film circuit. The opening 160 includes four substantially circular portions and three constricted portions. In the substrate, a conductive layer 172, an organic EL light emitting layer 171, a conductive layer 170, an insulating member 169 having an opening 161 thereon, and a conductive pattern 163 are formed on the insulating sheet 173. In the case of the matrix of FIG. 13, the conductor layer 170 has a shape of a line for each column. Although the organic EL light emitting layer is shown here as one layer, it may be a two layer composed of a light emitting layer and a hole transport layer, or may be a three layer composed of an electron transport layer, a light emitting layer and a hole transport layer. Further, there may be a buffer layer for lowering the emission voltage. In the case of emitting light upward, the conductive layer 170 is a transparent electrode ITO such as indium tin oxide having a high visible light transmittance, and the conductive layer 172 which is also a cathode of the light emitting element has a small work function such as gallium or indium. Use metals from Group 3 and magnesium alloys that are scientifically stable and inexpensive.

The conductor layer 170 may of course be a high molecular type or a low molecular type. In this figure, there is no filter and the light emitting layer itself has three colors. White light emission may be provided and a color filter layer may be provided on the upper surface, or blue light may be emitted and a color conversion layer may be formed on the upper surface.

  Various liquid polymers are applied to the opening 160 of the substrate to form a circuit. Since all the pixels have the same configuration, the pixel 158 is considered. In the leftmost substantially circular portion, the high dielectric constant layer 164 and the conductor layer 165 overlap with the conductor layer 170 to form the capacitor C14. Since the capacitance of the capacitor is proportional to the dielectric constant and inversely proportional to the film thickness, the high dielectric constant layer 164 may be formed by reducing the thickness of the insulator layer instead of the high dielectric constant layer.

  In the second constricted portion from the left, an N-type semiconductor layer 174, a source electrode 161, an insulator layer 166, and a conductor layer 165 are formed on the conductor layer 170. A part of the periphery of the source electrode 161 is on the constricted portion, and the conductor layer 165 is in contact with the N-type semiconductor layer 174 through the insulator layer 166, so that the transistor Tr52 is formed. In the substantially circular portion on the rightmost side, the insulator layer 175, the source electrode 161, the MIM layer 168, and the conductor layer 167 are overlapped on the conductor layer 170 to form the MIM element MIM4. A capacitor and an MIM element are formed in two of the four substantially circular portions, and a transistor is formed in one of the three constricted portions. By forming capacitors and MIM elements in close contact, the number of substantially circular portions may be reduced and the size may be reduced. Since the light is emitted as it is under the circuit forming portion, the ratio of the light emitting region does not decrease even if the circuit is enlarged.

  FIG. 15 shows a matrix display device using a transistor with a high threshold voltage. The configuration of the pixels 186, 187, and 188 is the same as that in FIG. 4, and includes a drive current latch circuit including two transistors and a capacitor and a light emitting element. The column line of each pixel is controlled by a shift register composed of a D flip-flop. The outputs 182 and 183 of the set current output means 180 and 181 become row lines. The output of one constant current output circuit 178 is sequentially transmitted to the set current output means of each row using a shift register or the like. The set current output means for each row is composed of D flip-flops D-FF7 and 8, transistors Tr54 to Tr63, and capacitors C16 and C17.

  Since the other rows have the same configuration, the setting current output means 180 will be described. The transistors Tr54 and 55 are controlled by the output of the flip-flop D-FF7. When the output Q of the flip-flop D-FF15 is Q = H, the transistors Tr54 and 55 are turned on. The transistors Tr55 and Tr56 and the capacitor C16 form a current latch circuit. A set current from the constant current output circuit 178 is input via the transistor Tr54, and a voltage corresponding to the current is charged in the capacitor C16. When the output of the D flip-flop shifts and Q = L, the transistors Tr54 and 55 are turned off, and the latched current is held. When CTL1 = L and the transistor Tr57 is turned on, the latch current is output to the row line. When CTL1 = H and CTL2 = L, the transistor Tr58 is turned on, and the voltage of the light emission power source 179 is output to the row line 182.

  In FIG. 15, pseudo pixels 184 and 185 without a light emitting element are provided on the pixel side only by a drive current latch circuit. These are for absorbing the offset error of the output current of the set current output means, and when all the pixels are turned off, the maximum current of the expected offset error is set in the set current output means. First, the pseudo pixel is latched. In these pseudo pixels, a current that is shifted from the set value by an offset error is latched. Thereby, when the current is latched in the pixel, a current having no offset error can be set.

The control flow is shown in FIG.
1) All pixels off S53: The control signals CTL1 = H and CTL2 = H, the data Dx = H on the column side for one column clock period, and pulses corresponding to the number of columns in the column clock CKx are output.
Since no current flows through the pixels and the latching is performed sequentially, the latch currents of the pseudo pixels and all the pixels become zero.
2) Canceling the offset S54: The control signals CTL1 = L and CTL2 = H, and the column side data Dx = H.
• Select a column of pseudo pixels.
S55: The current of the maximum offset error is set to the constant current output circuit, the row-side data Dy is set to H for a period of one clock, and pulses corresponding to the number of rows are output from the clock CKy.
• A current deviated from the set current by an offset error is output from the set current output means.
The current with the offset error is latched in the pseudo pixel.
3) Current latch to the pixel S56: One pulse of the column clock CKx is output, and the data Dy on the row side is set to H for the period of one clock of the row clock.
The pseudo pixel column becomes Q = L, the latch current is held, and the column controlled by the subsequent flip-flop becomes the selected column.
S57: The current obtained by adding the pixels of the already selected column and the newly selected column for each row is sequentially output from the constant current output circuit in accordance with the output of the clock CKy.
The current is latched on the pixel in the newly selected column.
S58: 3) is repeated for the number of columns.
• Current is latched in all pixels. Q = L in all columns, and the current of all pixels is held.
4) Hold until display update cycle S59: Set control signals CTL1 = H and CTL2 = L.
The transistors Tr57 and 62 are turned off, the transistors Tr58 and 63 are turned on, and the light emission power source 179 is connected to the row lines 182 and 183.
S60: Hold until the display update cycle.
・ All pixels emit light at the set current.
5) Clear the latch current for each column.
S61: Column-side data Dx = H, column clock CKx is output by one clock, the next column of pseudo pixels is selected, and row-side data Dy = H is set for a period of one clock.
S62: The control signals CTL1 = L and CTL2 = H are set.
S63: The current obtained by subtracting the current of the selected pixel sequentially from the total current for each row is sequentially output from the constant current output circuit in accordance with the output of the clock CKy.
-The latch current of the pixels in the selected column is cleared to zero.
• The pseudo pixel still retains the offset error current.
S64: One pulse is output from the clock CKx.
The pseudo pixel column becomes Q = L, the latch current is held, and the column controlled by the subsequent flip-flop becomes the selected column.
6) Update of all pixels and periodic update When S65: 6) is repeated several times in the column, the process proceeds to 1), and the display of the next period is started.
-All pixels in columns other than the column to which the pseudo pixel is connected are cleared. Since the lights are sequentially turned on and turned off sequentially, the light emission times of the pixels in each column are equal.
The above is the display procedure.

  Since the total current for each row is supplied from the row line, the current value output from the row line increases. If there is an offset error in the set current, a current including the offset error is set in the pixels in the first column. By arranging a pseudo pixel that does not include a light emitting element in the first column, light emission including an offset error can be prevented. Since some offset error is allowed, the setting current output means can be easily designed. Furthermore, since the offset error is canceled by the pseudo pixel every cycle, the accuracy is high. If the offset error of the current set in the set current output means is constant each time and the leakage of the pseudo pixel capacitor is small, the offset error does not need to be canceled by the pseudo pixel every cycle.

In this embodiment, a transistor having a large threshold voltage Vth as shown in FIG. Similar to FIG. 4, the threshold voltage of the transistor and the voltage across the light-emitting element must have the characteristics shown in Equation 4. Each pixel has one light emitting element, two transistors, one capacitor, and three control lines (signal line P, power supply, and ground), and there are few components and signal lines.

  FIG. 16c) shows a top view of the opening of the substrate and a cross section of the pixel portion formed by the thin film circuit. The opening 189 includes four substantially circular portions and three constricted portions. The substrate includes an insulating sheet 202, a conductive layer 201, an organic EL light emitting layer 200, a conductive layer 199, an insulating member 198 having an opening 189 thereon, and a conductive pattern 190 formed thereon. In the case of the matrix in FIG. 15, the conductive layer 210, the EL light emitting layer 200, and the conductive layer 199 are solid in the pixel portion, and the EL light emitting layer 200 and the conductive layer in the control circuit portion of the pseudo pixel or row or column. 199 is lost. As in FIG. 14, the organic EL light emitting layer does not have to be a single layer, and may be a plurality of layers. Of course, it may be a high molecular type or a low molecular type. In the case of color display, the three colors of RGB are separately applied according to the location of the pixel.

  Various liquid polymers are applied to the opening 189 of the substrate to form a circuit. Since all the pixels have the same configuration, the pixel 186 is considered. In the leftmost substantially circular portion, the high dielectric constant layer 193 and the conductor layer 192 overlap with the conductor layer 199 to form the capacitor C20. The N-type semiconductor layer 203, the conductor layer 205, the insulator layer 194, and the conductor layer 192 are applied on the conductor layer 199 in the second constricted portion from the left. A part of the peripheral portion of the conductor layer 205 is on the constricted portion, and the conductor layer 192 is in contact with the N-type semiconductor layer 203 through the insulator layer 194, so that the transistor Tr69 is formed. The rightmost constricted portion is coated with the insulator layer 204, the conductor layer 205, the N-type semiconductor layer 195, the conductor layer 192, the insulator layer 197, and the conductor layer 196 on the conductor layer 199. The A part of the peripheral portion of the conductor layer 192 is on the constricted portion, and the conductor layer 196 is in contact with the N-type semiconductor layer 195 through the insulator layer 197, thereby forming the transistor Tr68. The conductor layer 205 is a conductor layer 191 and is connected to the conductive pattern 190 which is a row line. The conductor layer 196 may be connected to the column line by applying the conductor layer on the upper side or the lower side of the rightmost substantially circular portion and connecting it to the conductive pattern.

  A capacitor is formed in one of the four substantially circular portions, and two transistors are formed in two of the three constricted portions. By forming them closely, the number of substantially circular portions may be reduced and the size may be reduced.

  FIG. 17 shows an embodiment of a serial display device using a shunt circuit of a light emitting element. This is a display device that short-circuits a display element connected in series with a current latch circuit at the output of a shift register. The display device includes a display control unit 206, flip-flop circuits D-FF 11 and 12 connected in series, and a plurality of pixels 211 and 212. The display control means 206 includes a set current output circuit 209 that outputs a set current corresponding to the setting, a current mirror including transistors Tr75 and 76 that transmits the output to the current transmission line 210, and an output of the current mirror to the power supply Vcc. It includes a transistor Tr74 that is short-circuited, voltage value detection means 207 that detects the voltage of the current transmission line, and a CPU 208 that controls them, a data signal, and a clock signal.

  Each of the pixels 211 and 212 includes light emitting elements LED 17 and 18 connected in series, a drive current latch circuit, and a voltage short circuit. The drive current latch circuit includes transistors Tr77 and 80, capacitors C23 and C24 connected to the gates and sources of the transistors 77 and 80, and sources and drains connected to the gates and drains of the transistors 77 and 80. It consists of transistors 78 and 101 whose outputs are connected to the gate. The voltage short-circuit transistors Tr79 and Tr82 are controlled by the outputs of the flip-flop circuits D-FF11 and 12, connected to both ends of the light-emitting elements LED17 and 18, and the light-emitting elements LED17 and 17 according to the outputs of the flip-flop circuits D-FF11 and 12, respectively. Both ends of 18 are short-circuited.

The plurality of pixels are connected in parallel, and one end connected in parallel is connected to the current transmission line 210.
Data L is sent to all the flop flops, and the output of the shift register is initialized to Q = L. A reset circuit (not shown) may be added to the flip-flop circuit. Do = H is set for one clock period, and Do = H is sequentially transmitted to the flop-flop. The pixel connected to the flip-flop of Do = H is the selected pixel, and the current for the pixel is output from the set current output circuit and transmitted to the selected pixel via the current transmission line.

  Since both ends of the light emitting element of the selected pixel are short-circuited by the transistor and the gate and drain of the transistor are also turned on, the voltage at the both ends of the selected pixel becomes a voltage that is almost as low as the gate-source voltage of the transistor. Since both the selected pixel and the non-selected pixel are connected in parallel, the voltage across the selected pixel is lowered, the voltage across the non-selected pixel is also lowered, the voltage of the light emitting element is lower than the emission start voltage, and the current is reduced. It stops flowing. A plurality of pixels are connected to the current transmission line, but since no current flows through the non-selected pixels, only the current desired to be latched by the selected pixels may be output from the set current output circuit. When current is latched in all the pixels and all outputs of the flip-flops become L, all the transistors that short-circuit both ends of the light-emitting elements are also turned off, so that current can flow through all the light-emitting elements. The setting current drive circuit may be set to the total value of the currents of all the pixels, or the power supply may be turned on completely.

The voltage across the selected pixel is the gate-drain voltage of the transistor and the current-driven light-emitting element voltage, and the voltage across the non-selected pixel is the source-drain voltage of the transistor and the current-driven light-emitting element voltage. The source-drain voltage is lower than the gate-drain voltage. After the current latch of all the pixels, since all the pixels are not selected, the voltage may be lowered as compared with the selection. By reducing the voltage, overall power consumption and heat generation can be reduced.

The control procedure is as follows.
1) Initial setting S66: Data output Do = H.
The pixel 211 controlled by the first-stage D-FF 3 becomes the selected pixel.
S67: Set the control signal CTL1 = H.
2) Current latch in selected pixel S68: A current value to be latched by the selected pixel in the set current output circuit is set.
・ The light emitting element of the selected pixel is short-circuited and the voltage drops. Since the voltage is low, the non-selected pixels are turned off.
The output current of the set current output circuit 209 is supplied to the selected pixel via the current mirror composed of the transistors Tr75 and 76 and the current transmission line 210.
S69: One clock CKx is output.
3) Sequentially set the current to the pixels S70: 2) is repeated for the pixels.
4) Display update S71: Set control signal CTL1 = L.
The transistor Tr74 is turned on, the power supply Vcc is connected to the current transmission line 210, and all the pixels emit light.
S71: The display is updated periodically.
・ Wait until the update time is reached, and proceed to the process 1).
The above is the display procedure.

  With 5 lines (Vcc, GND, current transmission line, Do, CK), a serial display device can be realized in which the luminance of an arbitrary pixel can be freely set. A Zener diode and a capacitor may be added for each D flip-flop to separate the power supply to the D flip-flop from the CK signal. Since the Vcc line is reduced, only four lines are required. In FIG. 17, the pixel is controlled by the output of the D flip-flop. However, the CPU 208 may be a multi-pin CPU and the pixel may be directly controlled by the CPU. Two gates are required per pixel for the gate and the cathode of the light emitting element, but if the output terminal is a 200-pin CPU, 100 pixels can be controlled.

  FIG. 17c) shows a top view of the opening of the substrate and a cross section of the pixel portion formed by a thin film circuit. The opening 215 includes five substantially circular portions and four constricted portions. The substrate includes an insulating sheet 216, a conductive layer 217, an organic EL light emitting layer 229, a conductive layer 228, an insulating member 219 having an opening 215 thereon, and a conductive pattern 218 formed thereon. From the first substantially circular portion to the second substantially circular portion, the EL light emitting layer 229 and the conductor layer 228 are not formed, and the conductor layer 217 is exposed. Light is emitted from the middle of the second substantially circular portion having the EL light emitting layer 229 to the right side. A light emitting portion may be provided at a place other than the opening 215 to widen the light emitting area. Various liquid polymers are applied to the opening 189 of the substrate to form a circuit. Since all the pixels have the same configuration, the pixel 211 is considered.

  In the first constricted portion from the left, an N-type semiconductor layer 221, a conductor layer 220, an insulator layer 222, and a gate electrode 223 are applied on the conductor layer 217. A part of the periphery of the conductor layer 220 is on the constricted portion, and the gate electrode 223 is in contact with the N-type semiconductor layer 221 through the insulator layer 222, thereby forming the transistor Tr79. In the second constricted portion from the left, an EL light emitting layer 229, a conductor layer 228, an N-type semiconductor layer 221, a conductor layer 224, an insulator layer 222, and a gate electrode 223 are applied on the conductor layer 217. The A part of the periphery of the conductor layer 224 is on the constricted portion, and the gate electrode 223 is in contact with the N-type semiconductor layer 221 through the insulator layer 222, thereby forming the transistor Tr78. A light emitting element LED 17 is formed of the conductor layer 228, the EL light emitting layer 229, and the conductor layer 217. In the third constricted portion from the left, an EL light emitting layer 229, a conductor layer 228, an N-type semiconductor layer 221, a conductor layer 231, an insulator layer 225, and a gate electrode 224 are applied on the conductor layer 217. The A part of the periphery of the conductor layer 231 is on the constricted portion, and the gate electrode 224 is in contact with the N-type semiconductor layer 221 through the insulator layer 225, thereby forming the transistor Tr77. In the substantially circular portion on the rightmost side, the EL light emitting layer 229, the conductor layer 228, the insulating member 230, the conductor layer 231, the high dielectric constant body layer 227, and the conductor layer 226 are overlaid on the conductor layer 217. Capacitor C23 is formed.

  In order to be the same as the pixel 211, the conductor layer 228 and the conductor layer 220 need to be connected. Apply a conductor layer on the top or bottom of the top, bottom, or third side of the third, fourth, and fifth circles from the left and connect them to a conductive pattern (not shown). A conductor layer is applied to the body layer 220 and connected to the conductive pattern. A capacitor is formed in one of the five substantially circular portions, and three transistors are formed in three of the four constricted portions.

  FIG. 18 shows an active matrix display device using a shunt circuit of a light emitting element, which is an extension of FIGS. 5 and 17 into a matrix. The pixels are the same as those shown in FIGS. Each of the pixels 242 and 242 includes a driving current latch circuit including two transistors Tr82 and 83, 86 and 87, capacitors C27 and 28, light emitting elements LED19 and 20, and shorting transistors Tr85 and 88, respectively.

  The output of the set current output circuits 235 and 236 is output to the row lines 237 and 238 for each row. The set current output circuit includes a current latch circuit and an output switching circuit. The set current output circuit includes D flip-flops D-FF 13 and 14, transistors Tr73 to Tr73, and capacitors C25 and 26. Transistors 74 and 75, 79 and 80, and capacitors C25 and 26 constitute a current latch circuit. The transistors Tr73 and 78 for switching between the current latch circuit and the constant current output circuit 234 are controlled by the outputs of the flip-flops D-FFs 13 and 14. The row data signal Dy and the clock signal CK are output from the display control means, and the output current of the constant current output circuit 234 is sequentially set in the current latch circuit. The switching circuit includes transistors Tr76, 77, 81, and 82. When the control signals CTL2 = L and CTL3 = HH, the set current output circuit is output. When CTL2 = H and CTL3 = L, the output of the power source 233 is output to the row line.

  The column of the output Q = H of the D flip-flop for column control is the selected column, and is input to the control signal CTL1 and the AND gates AND1 and AND2. When the control signal CTL1 = H, the pixels in the selected column can be current latched. When CTL1 = L, all the pixels emit light with the latched current.

The overall control procedure is as shown in FIG. 18b).
1) The first column is the selected column S73: The control signal CTL1 = L and the column data Dx = H for one clock.
The first column is the selected column, but since CTL1 = L, all column lines = L, and the pixel holds current.
2) Set current to set current output means S74: Set control signals CTL2 = H and CTL3 = L.
The transistors Tr76 and 81 are turned off, the transistors Tr77 and 82 are turned on, and the row lines 237 and 238 are connected to the power source 233.
• All pixels emit light with the current already latched.
S75: The row data Dy = H is set for a period of one clock of the row clock CKy.
S76: The current to be set in the set current output means is sequentially output from the constant current output circuit 234 in accordance with the output of the clock CKy.
The current for the selected column is latched in the set current output means.
3) Current latch in selected column S77: Set control signal CTL3 = H and CTL2 = L, set control signal CTL1 = H for the time required for latching, and return to L.
-The current from the set current output means is input to the selected column, and the current is latched.
S78: Output one column clock CKy.
・ The next column becomes the selected column.
4) Updating all pixels S79: 2) and 3) are repeated several times in the column.
・ All lights are on.
5) Lighting and periodic update S80: Hold all the pixels in a lit state until the cycle is reached.
・ When the cycle is reached, go to 1) and update the display to the next cycle.
The above is the display procedure.

  There are one light emitting element, three transistors, one capacitor, and three control lines (row line, column line, GND) per pixel. This can be realized with only the transistor.

  FIG. 19 shows an active matrix display device in which pixels are composed of four parts and three lines. The pixels are the same as in FIG. The set current output circuits 246 and 247 for the row lines include D flip-flops D-FFs 17 and 18 and transistors Tr89 to 98. Similar to the set current output circuits 235 and 236 in FIG. 18a), the current from the constant current output circuit 245 is latched in the current latch circuit for each row, and latched for each row when CTL2 = L and CTL3 = H. When the current is CTL2 = H and CTL3 = L, the output of the power supply 244 is output to the row lines 248 and 249.

  Each column is controlled by a shift register composed of a D flip-flop and a NAND gate, and the column of the output Q = H of the D flip-flop is a selected column. When the CTL1 = L, the NAND gates NAND3 and NAND5 keep the pixel current latch in the holding state regardless of the output Q of the D flip-flop. When the CTL1 = H and Q = H, the pixel of the column The current can be set. Due to the NAND gates NAND4 and NAND6, when CTL4 = L, the transistors Tr99 and 100 are turned on regardless of the output Q of the D flip-flop, connecting the pixel to GND, and when CTL4 = H and Q = L The pixels in that column are open.

  The pixel is controlled in three periods. The first period is a period in which a current is set in another pixel, and a set current is output from the row line to the other pixel, but the current between the light emitting element and GND is open and no current flows. Since gate = H, it is a period during which the voltage of the capacitor is also held. The second period is a period in which a current is set. A set current is output from the row line, the light emitting element and GND are turned on, a current flows, and gate = L. Therefore, a voltage corresponding to the set current is This is the period during which the capacitor is charged. The third period is a period in which light emission is performed, and a power supply voltage is output from the row line, the light emitting element and GND are turned on, and the gate = H, so that a current that has already been latched flows. During the third period, the set current is latched in the current latch circuit in the row line.

The overall control procedure is as shown in FIG. 19B).
1) First column is selected column S81: Column data Dx = H for 1 clock.
・ The first column becomes the selected column.
2) Set current to set current output means S82: Control signals CTL1 = L, CTL4 = L, CTL2 = H, CTL3 = L.
The outputs of the NAND gates NAND3 and NAND5 become H, all the pixels hold the latched current, the outputs of the NAND gates NAND4 and NAND6 become H, the transistors Tr99 and 100 between GND are turned on, and all the pixels are Emits light.
The transistors Tr92, 97 are turned off, the transistors Tr93, 98 are turned on, and the row line is connected to the power supply 244.
S83: The row data Dy = H is set for a period of one clock of the row clock CKy.
S84: The current to be set to the set current output means is sequentially output from the constant current output circuit in accordance with the output of the clock CKy.
・ The newly set current is latched in the set current output means.
3) Current latch in selected column S85: Set control signal CTL3 = H, CTL2 = L, CTL4 = H, set control signal CTL1 = H for latch time, and return to L.
-The current from the set current output means is input to the selected column, and the current is latched.
S86: One column clock CKx is output.
4) Updating all pixels S87: 2) and 3) are repeated several times in the column.
・ All lights are on.
5) Lighting and update S88: Wait until the update cycle comes. When the cycle is reached, the process proceeds to 1).
・ All pixels are lit until the update cycle arrives.
The above is the display procedure.

  There are one light emitting element, two transistors, one capacitor, and three control lines (row line, column line, GND side line) per pixel, and the circuit is simple and control is easy.

  FIG. 19c) shows a cross section of a pixel portion formed by a thin film circuit. It consists of four substantially circular parts and three constricted parts. In the substrate, a conductive layer 264, an organic EL light emitting layer 263, a conductive layer 261, an insulating member 262 having an opening thereon, and a conductive pattern 255 are formed on the insulating sheet 265. The conductor layer 261 is the anode of the light emitting element LED21 of this pixel and is separated from the periphery of the opening. The conductor layer 264 is a cathode of the light emitting element LED21 and is common to the pixels in the column direction. In the entire pixel portion, lines of conductor layers corresponding to the number of columns are arranged. The EL light emitting layer 263 may be arranged with lines for three colors of RGB, and for one color, the entire pixel portion may be solidly coated.

  Various liquid polymers are applied to the opening 189 of the substrate to form a circuit. Since all the pixels have the same configuration, the pixel 252 is considered. In the first constricted portion from the left, an EL light emitting layer 263, a conductor layer 261, an N-type semiconductor layer 266, a conductor layer 259, an insulator layer 56, and a gate electrode 257 are applied on the conductor layer 264. The A part of the peripheral portion of the conductor layer 259 is on the constricted portion, and the gate electrode 257 is in contact with the N-type semiconductor layer 266 through the insulator layer 256, so that the transistor Tr102 is formed. In the second constricted portion from the left, an EL light emitting layer 263, a conductor layer 261, an N-type semiconductor layer 266, a conductor layer 268, an insulator layer 258, and a gate electrode 259 are applied on the conductor layer 264. The A part of the peripheral portion of the conductor layer 268 is on the constricted portion, and the gate electrode 259 is in contact with the N-type semiconductor layer 266 through the insulator layer 258, whereby the transistor Tr101 is formed. The light emitting element LED21 is formed of the conductor layer 264, the EL light emitting layer 263, and the conductor layer 261. In the substantially circular portion on the rightmost side, the EL light emitting layer 263, the conductive layer 261, the insulating member 267, the conductive layer 268, the high dielectric constant layer 260, and the conductive layer 259 are superimposed on the conductive layer 264, Capacitor C23 is formed. A capacitor is formed in one of the four substantially circular portions, and two transistors are formed in two of the three constricted portions.

  20 to 23 show an embodiment of a composite display lighting device in which individual display devices (hereinafter referred to as panels) having a plurality of pixels are combined. FIG. 20a) is a composite display device in which 16 rectangular panels as individual display devices are connected. The whole display control means 269 to which power is supplied by the power cable 270 is connected to the panel H1 and sequentially connected to the panels up to H16. There are receivers on the left and lower sides of the rectangle, and transmitters on the right and upper sides. There is no dedicated communication bus connected to each panel, but a hierarchical connection in which each panel is directly connected to another panel. Although devices are connected mechanically between the devices that touch the top, bottom, left, and right, communication is not performed by all the connections, but communication is performed according to the flow indicated by the black arrows.

  FIGS. 20b), c), and d) show a hierarchy diagram 271 viewed from the relationship between the panel number and transmission. The panel of the transmission partner connected to the transmission unit on the right side is arranged on the right side, and the transmission partner connected to the transmission unit on the upper side is arranged on the lower right side. For each panel, write the panel name on the upper side and the number of the relative position of the panel on the lower side. In this embodiment, since up to six stages are connected in the subsequent stage, the relative position is represented by a six-digit number. If the right side transmitter is 1, and the upper side transmitter is 2, if the most significant digit is 1, it indicates a connection to the right side transmitter, and if it is 2, it indicates a connection to the upper side transmitter. If it is 0, it indicates that there is no connection. The number of the next digit indicates the next connection position. With this relative position information, the transmission path to the panel can be specified.

  FIG. 20b) shows the hierarchical structure of the panel as viewed from the panel H1. Since H1 itself is not connected to the transmission means, the relative position information is N000000. Since panel H2 is transmitted by the transmitting unit on the right side of H1, N100000, and panel H3 is transmitted by the transmitting unit on the right side of panel H2, so that N110000. In the case of the panel H16, the transmission unit includes the upper side (2), the upper side (2), the right side (1), the upper side (2), the right side (1), and the right side (1). Others are the same.

  FIG. 20 c) shows a panel hierarchical structure 273 as viewed from the panel H <b> 2, and is composed of a panel group 272 surrounded by a square b). Since H2 is the first panel, the relative position information is N000000. Since panel H3 is connected to the first output of panel H2, it becomes N100000. When viewed from the panel H1, the position information of the panel H2 is N100000, and when viewed from the panel H1, it is N000000. If the most significant digit of the received position information is omitted and 0 is added to the least significant position, the position information is viewed from the subsequent panel, so conversion is easy.

    FIG. 20d) shows the hierarchical structure of the panel as viewed from the panel H3. Since H3 is the first panel, the relative position information is N000000.

  FIG. 21a) shows the composite display data. The display data sent to the panel H1 by the composite display control means 269 requires all the information of the panel group 271 in FIG. 20b), which is represented by the composite display data 274 in FIG. 21a). . The composite display data starts from the start data, followed by the number of stages, the data for each panel, and the end data. The data of each panel is arranged in an order that follows the hierarchical structure from the top.

Since individual panels can be replaced and it is not necessary to fix the panels, the panel name is not necessary for the data for each panel of the composite display data 276. Considering replacement of a failed panel, if there is relative position information, the panel name is not necessary. The composite display data 278 from the panel H1 to the panel H2 includes the data of the panel group 273 in FIG. The composite display data 279 from the panel H2 to the panel H3 includes the data of the panel group 275 in FIG.

  Details of the panel display data 277 to the panel H1 of the composite display data 276 are shown at 280. Relative position information N000000, shape and transmission unit number information K4-2, pixel number information G20, and current value data of each pixel. If it is a triangle and 2 outputs, it is K3-2, and if it is a hexagon and 3 outputs, it is K6-3.

  The panel H1 receives the composite display data 276 and transmits the composite display data 278 to the panel H2. Since the data of each panel is arranged in the order that follows the hierarchical structure from the top, even if not all of the composite display data 276 is received, when the relative position information N200000 is received, the most significant digit is It becomes 2 and it turns out that it became the data to another transmission means.

  Even when the composite display data is being received, there is relative position information for each panel, so each time data for one panel is received, the data obtained by converting the relative position information is sent to the designated transmission device. be able to. The display data is transmitted to the panel H16 only (the number of stages × the display data transmission time for one panel) for the panel H1. At the same time, display data is transmitted between a plurality of panels. Since the panels can transmit between a plurality of panels, a dedicated bus for communication is unnecessary, and even when a panel breaks down, it is possible to bypass the failed panel and send composite display data.

FIG. 21b) shows the flow of data reception and transmission.
1) Wait for reception S89: Wait until start data is received.
2) Process for receiving composite display data S90: When the end data is received, the process proceeds to end process S115.
S91: Wait until panel display data for one panel is received.
3) Processing and transmission of panel display data S92: The highest number of relative position information is stored in variable Nh.
S93: The highest position of the relative position information is shifted to the left and the lowest position is set to 0.
S94: The transmission means corresponding to the variable Nh is selected. When the variable Nh = 0, its own display unit is selected.
S95: If start data is not sent to the selected transmission means, start data is transmitted.
S96: The panel display data whose relative position information has been changed is transmitted to the selected transmission means, and the process proceeds to S108.
4) Termination processing S97: Termination data is transmitted to all transmission units that have transmitted.
As described above, every time panel display data is received, the entire transmission time can be shortened by processing and transmitting the data.

  FIG. 22 is a circuit diagram in which an entire display control device is arranged on the left, two receiving units are arranged on the right, and two individual display units are arranged on the transmitting unit. The overall display control device 281 includes an infrared communication unit 285, a USB connector 284, a USB communication unit 286, a wireless communication unit 287, a volume 288, a switch 289, an IC card 294, a display data storage unit 293, and a mail address storage unit 292. The transmission means 291 and the CPU 290 for controlling them are included. Further, there is an AC power input 283, a power supply 282 for generating a DC voltage therefrom, and a connector 295 for outputting the input AC power and the output of the transmission means 291 to the individual display device. When connecting to the Internet via infrared, USB, or wireless, the mail address stored in the mail address storage means is used.

  The individual display device 296 includes receiving connectors 301 and 305, switch means 302 for switching input of AC power, power supply 310 for generating DC power based on AC power, and receiving means 303 and 305 for receiving composite display data. Then, based on the composite display data, the display data on its own pixel portion, the transmission data processing means 306 for reconstructing the composite display data on the subsequent panel, and the first and second transmissions of the composite display data to the subsequent stage Transmission means 307 and 308 and first and second transmission connectors 311 and 309 are included. Further, a failed pixel position storage unit 300 that stores the position information of the failed pixel, a current correction data storage unit 299 that stores correction data of the current value of the pixel, a pixel unit 297 including a plurality of pixels, and transmission data processing There is display control means 298 for displaying on the pixel portion 297 based on the display data for own use from the means 306.

The transmission means and the reception means are the difference between the sending side and the receiving side of the composite display data. Needless to say, if there is a contradiction in the received composite display data, a re-transmission request is sent from the receiving means to the transmitting means, and communication for checking the connection status of the panel is performed when the power is turned on.
The whole display control device and the individual display device may be integrated, and another individual display device may be connected thereto. If it is a triangle or hexagon, the number of receiving means and transmitting means may be changed according to the shape. In FIG. 22, each individual display device is provided with a power source 310 that generates a DC voltage from commercial AC 100 V. However, if the wiring resistance can be sufficiently reduced as compared with the current consumption of the individual display device 296, the entire display control is performed. The DC power generated by the device 281 may be sent to the individual display device 296.

  FIG. 23 shows a rear view of a wall-hanging type composite display device. It is a figure separated for explanation, and the whole display control device 314 and the individual display devices 317, 333, 335, and 337 are connected and hung on a hook pierced on a wall by a chain 336. The individual display devices 317, 333, 335, and 337 are all rectangular and have the same shape.

  The overall display control device 314 has a power cable 312, a string-like on / off switch 315, an IC card mounting portion 313, a connection portion 316 with an individual trading device, and a wireless circuit therein. By pulling the string switch 315 once, the power is turned on to emit white light and start functioning as illumination. The brightness is increased at the second and third times, and turned off at the fourth time. Display is started by wirelessly transmitting display data when lit in white. TV, DVD, and the Internet may be displayed, or a still image may be displayed like a poster.

  The individual display devices 317, 333, 335, and 337 include reception connection members 320 and 322, and transmission connection members 326 and 325, which are connected to other devices. The receiving connecting member has the same shape, and includes a receiving concave connector portion 330, a mechanical connecting recess 332, and a locking member 331. All of the transmission connecting members have the same shape, and there are a transmission connector 329 that can be rotated at a rotation center 328 and a mechanical connection member 327. There is a recess in the middle, and the transmission connection member is used as a reception connection member. When inserted, the recess of the mechanical connection member 327 is mechanically locked by the locking member 331. The transmission connector is electrically connected by being inserted into the reception concave connector. When not connected to another individual display device, the transmission connector 329 and the mechanical connection member 327 are hidden in the individual display device by rotating around the rotation center 328. It looks good and is safe because it prevents accidental touching of the connector.

  Reference numeral 334 denotes a ring-shaped metal fitting for hanging a chain, and there are 8 pieces in one panel, and the chain 336 can be hooked at any position in the vertical and horizontal directions. The switch 321 is the switch 302 of FIG. 22 and selects which of the receiving connection units 320 and 323 is supplied with power. Reference numeral 324 denotes a substrate on which a circuit constituting the display control means is arranged, and a CPU, a power supply circuit, and the like are arranged. Reference numeral 318 denotes a reinforcing member, which is a reinforcing member that reinforces the four corners of the panel 323. When a panel is manufactured using a thin film electronic circuit, the panel is thin and can be bent. Since it is weak in strength, the four corners are particularly likely to be chipped, and therefore, it is reinforced by a reinforcing member 318 made of a resin sheet having strength and elasticity.

  FIG. 24 is a perspective view paying attention to the row lines and column lines of the panel of the display device. In the panel 338, row lines 339 and column lines 341 are arranged in parallel. When an active matrix is normally configured, row control circuits and column control circuits are arranged on at least two sides outside the pixel portion, and an area that is not displayed is generated near the periphery of the panel. When such panels are connected as shown in FIG. 23, an area that is not displayed at the center of the composite display device is formed. Although it can be very thin, it is still unsightly. In FIG. 24, the row lines are conducted to the back side by through-falls 340 not inside the panel but inside. Similarly, the column line is also connected to the back side by a through fall 340. If it is drawn out in a straight line, there will be a crossing point. It is very difficult to form a through-fall on a glass substrate, but it is easy if it is a hard substrate, a flexible substrate, or a resin sheet. A conductive layer, a light emitting layer, an insulating layer, and a conductive pattern may be formed on such an insulating sheet, and a circuit may be formed using a liquid polymer. Since the row control circuit and the column control circuit are not outside the pixel portion, display can be performed every corner of the panel. The composite display device of FIG. 23 can be configured with high quality.

  As described above with reference to the drawings, the following configuration can be raised as a particularly characteristic configuration.

Additional notes on Fig. 1)
In the thin film transistor comprising a substrate, a semiconductor layer, an insulator layer, a gate electrode, and a drain electrode, the substrate comprises an insulating sheet, a source electrode, an insulating member, and first and second conductive patterns, and the source electrode is provided on the insulating sheet. The insulating member covers the insulating member, the insulating member has an opening through which the source electrode is exposed, and the first and second conductive patterns are formed on the insulating member. A first substantially circular portion, a second substantially circular portion, and a constricted portion connecting the first and second substantially circular portions, a semiconductor layer is formed on at least the constricted portion, and a drain electrode is formed. Formed between the first substantially circular portion and the constricted portion, a part of the outer periphery thereof is located on the constricted portion, the insulating layer is formed on the second substantially circular portion and the constricted portion, and the gate electrode is formed on at least the constricted portion Formed on the drain electrode and the first conductor. To conduct a pattern, a thin film transistor which is characterized in that to conduct the gate electrode and the second conductive pattern.

(Notes on Fig. 2)
In the thin film transistor including a substrate, a semiconductor layer, an insulator layer, a source electrode, and a gate electrode, the substrate includes an insulating sheet, a first drain electrode, a second drain electrode, and an insulating member, and the first is formed on the insulating sheet. A second drain electrode is formed, the insulating member covers, and the insulating member has openings through which the first and second drain electrodes are exposed,
In the center of the opening, the first and second drain electrodes face each other, and in the vicinity of the facing part, the first and second drain electrodes are formed in a straight line having a parallel width. Covering the second drain electrode, a source electrode having a substantially circular shape larger than the first insulator layer and smaller than the semiconductor layer is formed on the second drain electrode, and the first drain electrode is larger than the source electrode. A thin film current mirror circuit, wherein a gate electrode larger than the insulator layer and the source electrode and smaller than the first insulator layer is formed, and the first drain electrode and the gate electrode are electrically connected.

(Additional notes regarding Figure 3)
In a current latch circuit for driving a light emitting element with a constant current, a transistor, a capacitor connected between the gate and source of the transistor, a voltage generating element connected to the gate and drain of the transistor, and a source of the transistor A light emitting element connected in series with the drain, the voltage generating element is an MIM element or a varistor;
A current voltage output means for outputting a constant current or a voltage is connected to the current latch light emitting circuit. A voltage is applied from the current voltage output means in a direction in which the light emitting element does not emit light, and the capacitor is discharged. 1 step,
A second step of inputting a constant current in a direction in which the light emitting element emits light from the current / voltage output means, and charging the capacitor with a voltage corresponding to the input current;
The current is controlled by a third step of applying a voltage in the direction in which the light emitting element emits light from the current voltage output means and causing the light emitting element to emit light with a current corresponding to the voltage charged in the capacitor. Latch circuit.

Additional notes on FIG. 18)
In a matrix display device, a plurality of row lines that output a constant current or a constant voltage, a plurality of column lines that output a voltage, and a plurality of pixels, each pixel being connected in series A driving current latch circuit and a third transistor, the driving current latch circuit including a first transistor, a first capacitor connected to a gate and a source of the first transistor, and a gate of the first transistor; It consists of a second transistor having a drain connected to the source and drain, the source and drain of the third transistor are connected to both ends of the light emitting element, and one end of a plurality of pixels arranged in the row direction is connected to the row line. The other ends of the pixels are all connected to the reference voltage, and the gates of the second and third transistors of the plurality of pixels arranged in the column direction are connected to the column line. Display device, characterized in that connected.

By using the thin film transistor circuit structure of the present invention, high integration of all organic transistor circuits as well as display devices can be realized. By using an active-driven multi-pixel display device with a small number of parts constituting a pixel and a small number of control signals, a display device composed of an organic EL or an LED can have high definition and cost reduction. By using a hierarchical connection structure of display devices, both current-driven display devices and voltage-driven display devices can be easily increased in size. By combining these three, it is possible to realize a thin, high-definition and large-screen display device.

Conceptual diagram of the transistor of the first invention Conceptual diagram of thin film electronic circuit of second invention A display device of the third invention using a voltage generating element a) Circuit diagram b) Flow Display device of the fourth invention using a transistor with a high threshold voltage a) Circuit diagram b) Flow Display device of 5th invention using shunt circuit of light emitting element a) Circuit diagram b) Flow Display device of 6th invention with 4 parts and 3 lines of pixels a) Circuit diagram b) Flow Conceptual diagram and transmission data of composite display device of seventh invention N-type transistor a) Top view and cross-sectional view of substrate b) Application drawing of liquid polymer c) Cross-sectional view d) Equivalent circuit P-type transistor a) Top view and cross-sectional view of substrate b) Application drawing of liquid polymer c) Cross-sectional view d) Equivalent circuit Inverter a) Top view and sectional view of substrate b) Liquid polymer coating c) Cross section d) Equivalent circuit Current mirror a) Top view and cross section of substrate b) Liquid polymer coating c) Cross section d) Equivalent circuit NAND gate a) Top view of substrate b) Liquid polymer coating c) Cross section d) Equivalent circuit Active matrix display device using voltage generator a) Circuit diagram b) Flow Characteristics of voltage generating element and cross section of pixel part a) Characteristics of transistor drain / source voltage and drain current b) Voltage / current characteristics of voltage generating element, LED and transistor c) Cross section of pixel part and equivalent circuit Active matrix display device using transistors with high threshold voltage a) Circuit diagram b) Flow Characteristics of transistor and cross-sectional view of pixel portion a) Characteristic diagram of drain-source voltage and drain current of transistor b) Voltage-current characteristic of transistor and LED c) Cross-sectional view and equivalent circuit of pixel portion Serial display device using shunt circuit of light emitting element a) Circuit diagram b) Flow c) Cross-sectional view of pixel portion and equivalent circuit Active matrix display device using shunt circuit of light emitting element a) Circuit diagram b) Flow Active matrix display device consisting of 3 lines of 4 parts a) Circuit diagram b) Flow Composite display device of the eighth invention a) Connection diagram b) Hierarchy view from panel H1 c) Hierarchy view from panel H2 d) Hierarchy view from panel H3 Transmission data and processing flow a) Composite display data b) Processing flow of transmission data Circuit diagram of whole display control means and individual display device Rear view of composite display device Rear view of display panel

Explanation of symbols

Numbers only: Various functional blocks H: Display device panel LED: Current-driven light emitting element. LED and organic EL
MIM: Voltage generating element, MIM (Metal Insulator Metal) element and varistor Tr: Transistor C: Capacitor R: Resistor OP: Operational amplifier D-FF: D flip-flop AND: AND gate NAND: NAND gate P: For each row or for each column Control signal CTL: control signal for entire row or column Do: data output to serial display device CK: clock output to serial display device Dx: data output in column direction of matrix display device CKy: matrix display device Clock output in the column direction Dy: Data output in the row direction of the matrix display device CKy: Clock output in the row direction of the matrix display device Vcc: Power supply GND: Ground

Claims (8)

In a thin film transistor including a substrate, a semiconductor layer, an insulator layer, a gate electrode, and a drain electrode, the substrate includes an insulating sheet, a source electrode, and an insulating member, the source electrode is formed on the insulating sheet, and the insulating member covers The insulating member has an opening through which the source electrode is exposed. The opening includes a first substantially circular portion, a second substantially circular portion, and the first and second substantially circular portions. A constricted portion, a semiconductor layer is formed on at least the constricted portion, a drain electrode is formed over the first substantially circular portion and the constricted portion, and a part of the outer periphery of the drain electrode is located on the constricted portion. A thin film transistor circuit, wherein the insulating layer is formed on the second substantially circular portion and the constricted portion, and the gate electrode is formed on at least the constricted portion.
In the thin film transistor including a substrate, a semiconductor layer, an insulator layer, a source electrode, and a gate electrode, the substrate includes an insulating sheet, a first drain electrode, a second drain electrode, and an insulating member, and the first is formed on the insulating sheet. A second drain electrode is formed, and the insulating member covers the insulating member, and the insulating member has an opening through which the first and second drain electrodes are exposed. The first and second drain electrodes are exposed in a straight line with parallel widths, and the first and second drain electrodes are sufficiently spaced apart, or A second insulator layer is formed on the facing portion, the first and second drain electrodes are covered with the semiconductor layer, and are larger than the first insulator layer, and the semiconductor layer Forming a substantially circular source electrode smaller than the layer, and further forming a source electrode A larger first insulator layer, a gate electrode larger than the source electrode and smaller than the first insulator layer, and formed by conducting the first drain electrode and the gate electrode. A thin film current mirror circuit.
In a display device comprising a plurality of row lines from the row control means, a plurality of column lines from the column control means, and a plurality of pixels arranged in a matrix, the plurality of pixels are respectively a light emitting element, a transistor, and a capacitor. The light emitting element and the transistor are connected in series, the capacitor is connected between the gate and source of the transistor, the voltage generating element is connected to the gate and drain of the transistor, and the voltage The generation element is an MIM element or a varistor, and one end of a plurality of pixels is connected in parallel to the row line in the row direction, and the other end of the plurality of pixels is connected in parallel to the column line in the column direction. The control means includes a constant current or constant voltage output means to the row line, and the column control means includes a constant voltage output means to the column line. A first step of outputting a constant voltage from the row line and the column line so that the element is reverse-biased, and a constant current to be set to the pixel of the selected column are output from the row line, and the selected column and other columns are output. The display device is controlled by a second step of outputting different constant voltages and a third step of outputting constant voltages from the row lines and the column lines so that forward bias is applied to the light emitting elements of the pixels.
In a display device comprising a plurality of row lines from the row control means, a plurality of column lines from the column control means, and a plurality of pixels arranged in a matrix, the row control means has a current value corresponding to the setting. Are output from the row line, and a plurality of pixels in the row direction are connected to the row line. Each pixel of the plurality of pixels includes a light emitting element, a first transistor, a second transistor, and a capacitor. The first transistor is connected in series, the capacitor is connected between the gate and the source of the first transistor, and the second transistor has a source connected to the gate of the first transistor and a drain connected to the drain. The gates of the second transistors of the plurality of pixels are connected to the column line, and the voltage obtained by adding the light emitting element voltage at the minimum driving current in use and the threshold voltage of the transistor is Maximum drive current when the light emitting element voltage and a transistor source of the time of use - display and greater than the voltage obtained by adding the drain voltage.
In a display device comprising a display control means, an output signal shift means, and a plurality of pixels, the display control means includes a set current output means for outputting a set current corresponding to the setting to the current transmission line,
The output signal shift means has a plurality of output terminals, and sequentially shifts output values of the plurality of output terminals. Each pixel has a light emitting element connected in series, a drive current latch circuit, a third The drive current latch circuit switches between a first transistor, a first capacitor connected to a gate and a source of the first transistor, and a gate and a drain of the first transistor; The third transistor comprises a second transistor whose gate is connected at the output of the signal shift means, the third transistor has its gate controlled by the output of the output signal shift means, switches both ends of the light emitting element, and a plurality of pixels are arranged in parallel The display device is characterized in that one end connected in parallel is connected to the current transmission line.
In a display device comprising a plurality of row lines from the row control means, a plurality of column lines, a plurality of pixel control lines from the column control means, a plurality of pixels arranged in a matrix, and a plurality of switching circuits, Each pixel includes a light emitting element and a drive current latch circuit connected in series, and the drive current latch circuit includes a first transistor, a first capacitor connected between a gate and a source of the first transistor, and a first capacitor. A second transistor for switching between the gate and drain of the transistor, one end of the pixel connected to the row line in parallel in the row direction, and the other end of the pixel connected to the column line in parallel in the column direction. The column lines are respectively connected to a power source or a ground via the switching circuit, and the switching circuit is controlled by the column control means. The gate of the second transistor of the plurality of pixels of direction is a display device characterized in that it is connected to the pixel control line.
In the composite display device in which a plurality of individual display devices are connected, the individual display device includes at least one receiving unit, a plurality of transmitting units, a transmission data processing unit, a display control unit, and a plurality of light emitting elements, The transmission means can be connected to the reception means of another individual display device, and relative position information indicating the connection position of the individual display devices connected by the transmission means, and control data of a plurality of light emitting elements in the individual display device The composite display data including all the individual display devices connected by the transmission means is transmitted through the transmission means, and the individual display device that has received the transmission data receives the composite display data. Based on the above, the transmission data processing means creates new composite display data replacing the relative position information viewed from the transmission means of the individual display device, and from the transmission means The individual display device for forming a composite display apparatus and transmits the new combined display data.
The transistor circuit according to claim 1 or the current mirror circuit according to claim 2 is used, and at least one type of display device according to claims 3 to 6 is used. A composite display device according to claim 7, wherein the display device is an individual display device.

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