JP2005311886A - Video signal processing circuit and video display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video signal processing circuit capable of reducing a circuit scale in a scale conversion and reducing the deterioration of vertical resolution. <P>SOLUTION: A vertical scaler 11 includes a function of increasing the number of scanning lines of an input video signal. Its increasing rate is about 1.0. The rate satisfies a condition of 0<α<2, where the number of unit output lines is M, the number of unit input lines is N and the increasing rate is α. That means, α is set at about 1.0. A plurality multiplication circuit 12 reads an input video signal at a clock of three times. Also, the circuit 12 is configured so as not to select a video signal read by address passing. A horizontal scaler 13 interpolates the number of horizontal dots while causing the number to correspond to the number of horizontal pixels of a liquid crystal panel 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video signal processing circuit and a video display device which are used for scaling a video signal and driving a display.

  For example, standards such as VGA, XGA, and WXGA exist for the number of pixels of a liquid crystal panel. The resolution of the VGA panel is vertical 480 lines / horizontal 640 dots, and the XGA resolution is vertical 768 lines / horizontal 1024 dots. On the other hand, video signals include NTSC and PAL. In the case of NTSC, the resolution is 240 vertical lines / horizontal 720 dots. For this reason, when the liquid crystal panel is driven by the video signal, it is necessary to convert (scale conversion) the number of horizontal pixels and the number of vertical pixels into a resolution suitable for the liquid crystal panel.

As a scale conversion method, there is a method in which the number of scanning lines is increased up to the resolution of the panel using a vertical scaler after once up-converting 480 interlace signals to 480P (progressive) signals (see Patent Document 1). . In the horizontal direction, a general interpolation filter is used to increase the number of horizontal pixels up to a predetermined panel horizontal resolution.
JP-A-5-252486

  In the conventional scale conversion method, motion adaptive progressive scan conversion is used to up-convert a 480 interlace signal to a 480P signal. This conversion requires a large capacity memory and a complicated signal processing circuit. . In addition, in this conversion, sequential scanning is performed to average the upper scanning line information and the lower scanning line information in the moving portion, so that a good image quality can be obtained in the still image, but the vertical resolution is in the moving image portion. The image is reduced to half, and the image quality is greatly deteriorated.

  On the other hand, as a method of performing scale conversion with a small circuit scale, there is a method of increasing the number of scanning lines to the number of lines of a liquid crystal panel for 240 video signals per field using a vertical interpolation filter. However, this method has a large vertical increase rate, so that the vertical resolution is greatly degraded.

  In view of the above circumstances, an object of the present invention is to provide a video signal processing circuit and a video display device that can reduce the circuit scale and reduce the deterioration of vertical resolution.

  In order to solve the above-described problem, the video signal processing circuit of the present invention is a video signal processing circuit that performs scale conversion of a video signal, and the line number increase rate α in the vertical direction with respect to the video signal is set to 0 <α <2. And a readout circuit that reads the same line of the video signal obtained through the vertical scaler once or a plurality of times during one horizontal period.

  According to another aspect of the present invention, there is provided a video signal processing circuit for converting the scale of a video signal, a readout circuit for reading out the same line of the video signal once or a plurality of times during one horizontal period, and the readout circuit. A vertical scaler in which an increase rate α of the number of lines in the vertical direction with respect to the obtained video signal is set to 0 <α <2.

  The video signal processing circuit having such a configuration preferably includes a horizontal scaler that converts the number of dots in the horizontal direction with respect to the video signal. The vertical line number increase rate a of the vertical scaler may be selected from a range of about 0.66 to about 1.58.

  The video display device according to the present invention includes any of the video signal processing circuits described above, and is configured to supply an output video signal from the video signal processing circuit to a hold-type display panel such as a liquid crystal panel. It is characterized by.

  According to the present invention, it is possible to reduce the circuit scale and reduce the deterioration of the vertical resolution in the scale conversion.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing a video display device. This video display device includes a video signal processing circuit 1 and a liquid crystal panel (LCD) 2. The video signal processing circuit 1 includes a vertical scaler 11 (11A, 11B), a multiple multiplying circuit 12, and a horizontal scaler 13. The input video signal is a digitized video signal (luminance / color difference signal, RGB signal, etc.) and is input to the vertical scaler 11. The vertical scaler 11 has a function of increasing the number of scanning lines of the input video signal. However, the increase rate is around 1.0. For example, when the number of unit output lines from the vertical scaler 11 is M, the number of unit input lines to the vertical scaler 11 is N, and the increase rate is α,
0 <α <2 (a = M / N)
Satisfy the condition of That is, α is in the vicinity of 1.0. In this embodiment, α ≠ 1.

  As the vertical scaler 11, a vertical scaler 11A shown in FIG. 2 or a vertical scaler 11B shown in FIG. 4 is employed. Of course, it is not limited to these. The vertical scaler 11A includes a single line memory 11a. FIG. 3 shows an operation timing chart of the line memory 11a. Here, the horizontal axis is time, and the vertical axis is the address value of the line memory 11a. A solid line indicates a write address, and a dotted line indicates a read address. In the input and output, a, b, c,... Each indicate a one-line video signal. In this example, M = 6 and N = 5 are shown, and α = 1.2.

  In FIG. 3, when viewing the output of the line memory 11a, one line video (a) is read twice, and the other one line video (b to e) is read once. As a result, 5 scan lines are increased to 6.

  The vertical scaler 11B shown in FIG. 4 has a circuit configuration that can prevent the one-line video (a) from being output twice. The vertical scaler 11B includes a first line memory 11b, a second line memory 11c, a first multiplier 11d, a second multiplier 11e, and an adder 11f. The first line memory 11b operates in the same manner as the line memory 11a described above. The output of the first line memory 11b is input to the first multiplier 11d and the second line memory 11c. The second line memory 11c outputs the input data with a delay of one horizontal period in the read system. The first line memory 11b and the second line memory 11c constitute a vertical interpolation filter.

  The data delayed in the second line memory 11c is input to the second multiplier 11e. The first multiplier 11d multiplies the input data from the first line memory 11b and outputs it, and the second multiplier 11e multiplies the input data from the second line memory 11c and outputs it. The adder 11f inputs m-fold output data and n-fold output data and outputs a value obtained by adding them.

  FIG. 5 is an operation timing chart of the vertical scaler 11B. The horizontal axis is time, and the vertical axis is the address value of the line memory. A solid line indicates a write address, and a dotted line indicates a read address. As can be seen from FIG. 5, with the vertical scaler 11B, the same video signal is not output twice in succession. As the multiplication coefficients (m) and (n) of the multipliers 11d and 11e, for example, a constant for linearly interpolating two scanning line signals is selected. For example, m = 0.5 and n = 0.5 can be employed.

  In order to construct an interpolation filter with better characteristics, a line memory may be further cascade-connected to the subsequent stage of the second line memory 11c.

  The horizontal scaler 12 converts the number of horizontal dots of the video signal input from the vertical scaler 11 into the number of horizontal dots on the liquid crystal panel 15. For example, when the liquid crystal panel 15 is an XGA panel, the input signal (720 dots) is converted into the horizontal resolution (1024 dots) of the XGA panel. A one-dimensional interpolation filter may be used for this conversion.

  FIG. 6 is a block diagram showing the multiple multiplier circuit 12. The multiple multiplication circuit 12 includes a third line memory 12a, a fourth line memory 12b, and a selection circuit 12c. The third line memory 12a and the fourth line memory 12b are input system clocks (corresponding to the read clocks of the first line memory 11b and the second line memory 11c) and alternately output video signals from the vertical scaler 11 every other line. Write. Then, reading is performed with a clock (for example, 1 times, 2 times, 3 times, etc.) that is an integral multiple of this write clock.

  FIG. 7 is a timing chart showing processing of the multiple multiplier circuit 12. In this example, reading is performed with three times the clock. When reading is performed at a triple speed, the ratio is 3/1, 3-1 = 2, and address overtaking occurs. Therefore, the third line memory 12a and the fourth line memory 12b are arranged in parallel. The selection circuit 12c selects and outputs the same video signal read three times from the third line memory 12a. Thereafter, switching to the fourth line memory 12b side, the same video signal read out three times from the fourth line memory 12b is selected and output. And it switches to the 3rd line memory 12a side again, and the same switching process is repeated. That is, the multiple multiplying circuit 12 is configured to perform reading with a triple clock and not to select a video signal read by address overtaking.

  The horizontal scaler 13 receives the video signal from the multiple multiplier circuit 12 and converts the number of horizontal dots of the video signal into the number of horizontal dots of the liquid crystal panel 2. For example, when the liquid crystal panel 2 is an XGA panel, the input signal (720 dots) is converted to the horizontal resolution (1024 dots) of the XGA panel. A one-dimensional interpolation filter may be used for this conversion.

As described above, the total output video scanning line number M ′ at the final stage in the system is
M ′ = N ′ × α × K = N ′ × (M / N) × K
Can be expressed as Here, N ′ is the total number of input video scanning lines, K is the number of multiplications (enlargement ratio) in the multiple multiplication circuit 12, and has values (natural numbers) of K = 1, 2, 3,.

Assuming that 240 NTSC signals per field are displayed on the VGA panel,
α = 20/19 = 1.05263
And K = 2, the total output video scanning line number M ′ is
M ′ = 240 × α × K = 240 × 1.0526 × 2 = 505.

  Since the vertical resolution of the VGA panel is 480 lines, the remaining 25 lines (505-480 = 25) are not displayed on the panel, and 95% is displayed. In general, the same applies to CRT televisions. However, when 100% of the input video signal is displayed, noise is displayed when a signal that is unstable and does not comply with the NTSC (PAL) standard is displayed, such as during VTR playback. In some cases, it is necessary to display an area of 100% or less.

Also, assuming display on an XGA panel (vertical resolution = 768),
α = 9/8 = 1.125
K = 3
Total scanning line number M ′ = α × 3 × 240 = 1.125 × 3 × 240 = 810
Display rate = 768/810 = 0.948
It becomes.

  FIG. 8 shows the resolution of various video display panels, various video signal formats, the number of effective scanning lines of the input video, the display rate, the number of display lines of the panel, and the magnification K of the multiple multiplier circuit. It is explanatory drawing which showed the relationship with increase rate (alpha). The increase rate α may be selected from the range of about 0.66 to about 1.58. By the way, the number of scanning lines of NTSC is 525, and the number of scanning lines of PAL is 625. In the case of NTSC, it becomes an integer as (525/2) × (22/21) = 275 (M is the numerator and N is the denominator). In the case of PAL, if (625/2) × (even / 5 or 25 or 125 or 625), it becomes an integer. It becomes easy to create a circuit by becoming an integer. In FIG. 8, when the increase rate α is close to 0.87719, when denominator = 5 and numerator = 4, α = 0.8, and when denominator = 25 and numerator = 22, α = 0.88. Either is acceptable. If the denominator is 25 and the numerator is 24, α = 0.96 and the display rate may be 0.86. The display rate is not constant in each company's display panel, and is generally in the range of 0.9 to 0.95.

  As described above, since the vertical scaler 11 in which the increase rate α is 0 <α <2 (that is, α is in the vicinity of 1.0) is used, the image quality is hardly deteriorated and the circuit scale can be reduced. Furthermore, by using the multiple multiplier circuit 12 in combination with the vertical scaler 11, the finally required vertical scaling processing can be realized, and the circuit scale can be made very small.

  In the example described above, the multiple multiplier circuit 12 is provided at the subsequent stage of the vertical scaler 11. However, the present invention is not limited to this, and the arrangement relationship between the vertical scaler 11 and the multiple multiplier circuit 12 may be reversed. Is. In the above description, an example of driving a liquid crystal panel has been shown, but the present invention is not limited to this. The video display device of the present invention can improve image quality particularly when used for driving a so-called hold type display element such as a liquid crystal panel.

It is the block diagram which showed the video display apparatus and video signal processing circuit of embodiment of this invention. It is explanatory drawing which showed an example of the vertical scaler. It is explanatory drawing which showed the relationship between the input and output of the vertical scaler of FIG. It is explanatory drawing which showed the other example of the vertical scaler. FIG. 5 is an explanatory diagram showing a relationship between input and output of the vertical scaler of FIG. 4. It is a circuit diagram showing a multiple multiplication circuit. 5 is a timing chart showing the operation of the multiple multiplier circuit. The resolution of various video display panels, the format of various video signals, the number of effective scanning lines of the input video, the display rate, the number of display lines of the panel, the expansion rate K of the multiple multiplier circuit, and the increase rate α It is explanatory drawing which showed the relationship.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image display apparatus 2 Liquid crystal panel 11 Vertical scaler 12 Multiplexing circuit 13 Horizontal scaler

Claims (5)

In the video signal processing circuit for converting the scale of the video signal, a vertical scaler in which the vertical line number increase rate α with respect to the video signal is set to 0 <α <2, and the same line of the video signal obtained through the vertical scaler A video signal processing circuit comprising: a readout circuit that reads out one or more times during one horizontal period. In a video signal processing circuit for converting the scale of a video signal, a readout circuit for reading out the same line of the video signal once or a plurality of times in one horizontal period, and an increase in the number of lines in the vertical direction with respect to the video signal obtained through the readout circuit And a vertical scaler in which the rate α is set to 0 <α <2. 3. The video signal processing circuit according to claim 1, further comprising a horizontal scaler for converting the number of dots in the horizontal direction with respect to the video signal. 4. The video signal processing circuit according to claim 1, wherein the rate of increase in the number of lines in the vertical direction of the vertical scaler is selected from a range of about 0.66 to about 1.58. Video signal processing circuit. A video signal processing circuit according to any one of claims 1 to 4 is provided, and an output video signal from the video signal processing circuit is supplied to a hold type display panel such as a liquid crystal panel. A video display device.

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