JP2005311690A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit simultaneously realizing a wide oscillation frequency range and a satisfactory phase noise characteristic. <P>SOLUTION: In response to control signals from control terminals 51-54, the output voltage of a charge pump circuit 10 is regulated by a voltage regulation circuit 20, which is then applied to a variable capacity element 4020 via a filter circuit 30. With this, control sensitivity after the parallel synthesis of the variable capacity element 4020 and capacitors 4011, 4012, 4013 and 4014 is reduced, so as to obtain a predetermined frequency having low phase noise in the wide frequency range. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL (phase locked loop) circuit.

  A prior art configuration of a PLL circuit that generates a predetermined frequency is shown in FIG. In FIG. 9, reference numeral 10 indicates a charge pump circuit, reference numeral 30 indicates a filter circuit, reference numeral 40 indicates a voltage controlled oscillator, reference numerals 4010, 4011, 4012, 4013, and 4014 indicate capacitors, and reference numeral 4020 indicates a variable value. Reference numerals 4031, 4032, 4033, and 4034 indicate switches, reference numerals 4040 indicate inductors, reference numeral 4050 indicates an oscillation circuit, reference numerals 51, 52, 53, and 54 indicate control terminals, respectively. Reference numeral 60 denotes a frequency divider, reference numeral 70 denotes a phase comparator, and reference numeral 71 denotes a reference frequency input terminal.

  The operation of the PLL circuit configured as described above will be described with reference to FIGS. In FIG. 9, the signal output from the charge pump circuit 10 is supplied as a DC voltage to the variable capacitance element 4020 built in the voltage controlled oscillator 40 after the AC component is removed by the filter circuit 30. The variable capacitance element 4020 has a capacitance value corresponding to the supplied DC voltage. The capacitor 4010 separates the DC voltage applied to the variable capacitance element 4020 from the bias voltage of the oscillation circuit 4050.

  Capacitors 4011, 4012, 4013, and 4014 can be connected in parallel to the variable capacitance element 4020 in any combination by ON / OFF combinations of the switches 4031, 4032, 4033, and 4034. The switches 4031, 4032, 4033, and 4034 can be turned on / off by the control terminals 51, 52, 53, and 54. In FIG. 9, four sets of switches and capacitors connected in series to the switches are used, but they are configured by combining an appropriate capacitance value and number to oscillate at a predetermined frequency.

  The inductor 4040 is connected to a capacitor network including a variable capacitance element 4020 and capacitors 4010, 4011, 4012, 4013, and 4014. The oscillation circuit 4050 oscillates at a resonance frequency determined by the capacitor network and the inductor 4040. That is, the oscillation frequency of the oscillation circuit 4050 is determined by the resonance frequency of the resonance circuit configured by the capacitor network and the inductor 4040.

  The output signal from the voltage controlled oscillator 40 is divided by the frequency divider 60 and then compared with the reference frequency signal input from the reference frequency input terminal 71 by the phase comparator 70. Loop control in which the comparison result by the phase comparator 70 passes through the charge pump circuit 10 and the filter circuit 30 and is again applied as a DC voltage to the variable capacitance element 4020, whereby the capacitance value of the variable capacitance element 40 becomes a predetermined value. Is on.

  When the variable capacitance element 4020 does not reach a predetermined capacitance value, the switches 4031, 4032, 4033, and 4034 are controlled by the control terminals 51, 52, 53, and 54, and the capacitors 4011, 4012, 4013, and 4014 are arbitrarily set The combination can be connected in parallel to the variable capacitance element 4020 to expand the variable capacitance range.

  Such a configuration is used to obtain a wide oscillation frequency range, and is disclosed in Patent Document 1, for example.

  FIG. 10 is a diagram illustrating the relationship between the charge pump output voltage and the oscillation frequency in the configuration of FIG. 9, that is, the frequency control sensitivity. The symbols VCPL and VCPH on the horizontal axis represent the lower limit voltage and the upper limit voltage of the charge pump output voltage, respectively. It is assumed that the variable capacitance element 4020 uses a section having good linearity in the applied voltage vs. capacitance characteristic. The symbols fB1L and fB1H on the vertical axis represent the oscillation lower limit frequency and the oscillation upper limit frequency when the switches 4031, 4032, 4033, and 4034 are all turned on (hereinafter referred to as band B1), and the frequency control sensitivity at this time is βB1. . The symbols fB16L and fB16H on the vertical axis represent the oscillation lower limit frequency and oscillation upper limit frequency when all the switches 4031, 4032, 4033, and 4034 are turned OFF (hereinafter referred to as band B16). The frequency control sensitivity at this time is expressed as βB16. To do.

  Here, the band B1 and the band B16 are compared. The capacitance values when the DC voltages VCPL and VCPH are applied to the variable capacitance element 4020 are CDH and CDL, respectively, and the parallel combined capacitance of the capacitors 4011, 4012, 4013, and 4014 is CSW. Note that the capacitor 4010 is assumed to be sufficiently larger than the capacitance of the variable capacitance element 4020 so that it can be ignored in the calculation of the combined capacitance value of the capacitor network. In band B1 and band B16, assuming that the combined capacitance change ratios of the capacitor network when the charge pump output voltage is changed from VCPL to VCPH are CRB1 and CRB16, respectively, the following results.

(Equation 1)
CRB1 = (CDH + CSW) / (CDL + CSW)

(Equation 2)
CRB16 = (CDH / CDL)
A comparison of (Equation 1) and (Equation 2) is as follows.

(Equation 3)
CRB1 <CRB16
As shown in (Equation 3), in the band B16, compared with the band B1, the capacity CSW that is a fixed capacity is not added to the combined capacity, so that the combined capacity change ratio becomes large. The oscillation frequency f of the oscillation circuit is f = 1 / {2π√ (L * C)} where the inductance value of the resonance circuit is L and the capacitance value is C. Therefore, if the capacitance change ratio increases, the frequency change ratio Also grows. That is, the frequency control sensitivity is increased.

  More specifically, the frequency control sensitivity is obtained. When VCPL = 1V, VCPH = 2V, CDL = 2pF, CDH = 2.5pF, CSW = 1.875pF, and the inductance value of the inductor 4040 is L = 2.5nH, the frequency control sensitivities βB1 and βB16 are as follows. .

(Equation 4)
βB1 = (fB1H−fB1L) / (VCPH−VCPL)
= 1 / [2π√ {L (CDL + CSW)}] − 1 / [2π√ {L (CDH + CS W)}]
≒ 95.2MHz / V

(Equation 5)
βB16 = (fB16H−fB16L) / (VCPH−VCPL)
= 1 / {2π√ (L × CDL)} − 1 / {2π√ (L × CDH)}
≒ 237.6MHz / V
A comparison of (Equation 4) and (Equation 5) is as follows.

(Equation 6)
βB16 / βB1
≒ 237.6 / 95.2
As shown in (2.5) (Equation 6), the frequency control sensitivity differs depending on the band, and the frequency control sensitivity becomes high in a region where the oscillation frequency is high, such as band B16.
JP 2001-339301 A (page 8, FIG. 3).

  In the prior art PLL circuit configured as shown in FIG. 9, in order to expand the oscillation range to a low frequency, a capacitor having a switching means is connected in parallel with the variable capacitance element to obtain a predetermined variable capacitance range. As shown in (Equation 6), the frequency control sensitivity differs depending on the band, and the frequency control sensitivity is high in a region where the oscillation frequency is high.

  When voltage noise is superimposed on a PLL circuit having a high frequency control sensitivity, the capacitance fluctuation of the variable capacitance element due to the voltage noise increases, and as a result, the frequency fluctuation of the voltage controlled oscillator increases, resulting in deterioration of phase noise.

  Handling a multi-level phase-modulated signal with a tuner composed of a PLL circuit with degraded phase noise has the problem that the bit error rate is reduced, making it difficult to reproduce high-quality video and audio. It was.

  The present invention solves the above-described problems of the prior art, and an object thereof is to provide a PLL circuit that can simultaneously realize a wide oscillation frequency range and good phase noise characteristics.

  In order to solve the above problems, a PLL circuit according to a first aspect of the present invention includes a charge pump circuit, a voltage adjustment circuit that adjusts a voltage by performing voltage conversion on a linear function with respect to an output signal of the charge pump circuit, and a voltage A first filter circuit that removes noise components from the output signal of the adjustment circuit, a variable capacitance element that is supplied with voltage from the first filter circuit and is adjusted to a predetermined capacitance value, and is connected in parallel to the variable capacitance element A voltage-controlled oscillator comprising a capacitor with capacitance switching means, an inductor that constitutes a resonance circuit together with a variable capacitance element and a capacitor with capacitance switching means, and an oscillation circuit that oscillates at a frequency corresponding to the resonance frequency of the resonance circuit; A phase comparator that compares the output signal of the output signal or the divided signal with the reference frequency signal and outputs the comparison result to the charge pump circuit, and a voltage adjustment circuit. And a control terminal for switching control in conjunction with the capacitance value of the voltage conversion coefficient and capacitance switching means with capacitors. Then, according to the control signal from the control terminal, the operating voltage of the variable capacitance element is adjusted in conjunction with the switching of the capacitance value of the capacitor with capacitance switching means, so that the frequency control sensitivity by the variable capacitance element is provided with capacitance switching means. Regardless of the switching of the capacitance value of the capacitor, it is adjusted to be constant in a low state so that a predetermined frequency of low phase noise can be generated in a wide frequency range.

  According to this configuration, by adjusting the charge pump output voltage by the voltage adjustment circuit, it is possible to make the frequency control sensitivity uniform in a wide oscillation frequency range. As a result, a wide oscillation frequency range and good phase noise characteristics can be realized simultaneously.

  In the PLL circuit of the first invention, the voltage adjustment circuit includes a variable gain amplifier having a variable output voltage and a variable gain when a predetermined voltage is input, and a variable gain according to a control signal from a control terminal. The amplifier includes a gain / output voltage control circuit that controls an output voltage and a gain when a predetermined voltage is input to the amplifier.

  The gain / output voltage control circuit is preferably composed of a D / A converter.

  Other configurations of the voltage adjustment circuit include at least two amplifiers that output an arbitrary output voltage when a predetermined voltage is input and are set to an arbitrary gain, and at least 2 in accordance with a control signal from a control terminal. An amplifier selection circuit that selects one of the two amplifiers may be provided.

  In the PLL circuit of the first invention, the connection order of the voltage adjustment circuit and the first filter circuit may be reversed. Further, in the configuration in which the connection order of the voltage adjustment circuit and the first filter circuit is reversed, a second filter circuit that removes noise components from the output signal of the voltage adjustment circuit is provided between the voltage adjustment circuit and the variable capacitance element. It may be provided.

  In the PLL circuit according to the first aspect of the invention, a low-frequency pass type / voltage adjustment circuit may be used instead of the voltage adjustment circuit and the first filter circuit. The low-frequency pass-through / voltage adjustment circuit preferably has a function of varying the frequency characteristics.

  The tuner of the second invention is configured using the PLL circuit of the first invention.

  A communication system according to a third aspect of the invention is configured using the PLL circuit according to the first aspect of the invention.

  According to the present invention, the charge pump output voltage is adjusted by the voltage adjustment circuit and then applied to the variable capacitance element, so that the frequency control sensitivity can be made low over a wide oscillation frequency range, and a good phase can be achieved over a wide oscillation frequency range. A PLL circuit having noise characteristics can be realized.

  In addition, in the case of the configuration using the PLL circuit of the present invention as a tuner, broadcasts in a wide frequency range can be received, and high-quality video and audio can be reproduced with good phase noise characteristics.

  In addition, the configuration when the PLL circuit of the present invention is used in a communication system can support communication standards having different frequency bands, and can receive and transmit high-quality video, audio and data with good phase noise characteristics. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
1, 2 and 3 are circuit diagrams showing the configuration of the PLL circuit according to the first embodiment of the present invention. In FIG. 1, the same components as those in FIG.

  In FIG. 1, reference numeral 20 denotes a voltage adjustment circuit that can set an arbitrary gain by the control terminals 51, 52, 53, and 54. The frequency divider 60 can be omitted if not necessary.

  The signal output from the charge pump circuit 10 is input to the voltage adjustment circuit 20, and the capacitors 4011, 4012, Output after being attenuated or amplified to a gain set in association with capacitance values 4013 and 4014.

  After the AC component is removed by the filter circuit 30, the voltage-adjusted signal is supplied as a DC voltage to the variable capacitance element 4020 built in the voltage controlled oscillator 40. The variable capacitance element 4020 has a capacitance value corresponding to the supplied DC voltage. Subsequent operations are the same as those in FIG.

  FIG. 2 is a circuit diagram showing an example of a specific configuration of the voltage adjustment circuit 20 in the configuration of FIG. In FIG. 2, reference numerals 21 and 22 respectively indicate an input terminal and an output terminal of the voltage adjustment circuit, reference numeral 2010 indicates a variable gain amplifier, reference numeral 2020 indicates a gain / output voltage control circuit, and reference numeral 2030 indicates a variable gain amplifier. An output voltage adjustment part is shown.

  The signal output from the charge pump circuit 10 is input to the input terminal 21 of the voltage adjustment circuit 20, voltage-adjusted by the variable gain amplifier 2010, output from the output terminal 22, and input to the filter circuit 30. At this time, the variable gain amplifier 2010 adjusts the gain and the output voltage when a predetermined voltage is input according to the control signal input from the control terminals 51, 52, 53, and 54. The gain / output voltage control circuit 2020 converts the control signal from the control terminals 51, 52, 53, 54 into a signal for adjusting the gain of the variable gain amplifier 2010 and the output voltage adjustment unit 2030.

  FIG. 3 is a circuit diagram showing another example of a specific configuration of the voltage adjustment circuit 20 of FIG. In FIG. 3, the same components as those in FIG. Reference numerals 2011 and 2012 indicate amplifiers, reference numerals 2031 and 2032 indicate output voltage setting units, and reference numeral 2040 indicates an amplifier selection circuit.

  The signal output from the charge pump circuit 10 is input to the input terminal 21 of the voltage adjustment circuit 20, outputs an arbitrary output voltage when a predetermined voltage is input, and is set to have an arbitrary gain. The voltage is adjusted in 2012 and then output from the output terminal 22 and input to the filter circuit 30. At this time, the amplifier 2011 or 2012 is set to an arbitrary output voltage by the output voltage setting unit 2031 or 2032.

  One of the amplifiers 2011 and 2012 and the output voltage setting units 2031 and 2032 are selected by the amplifier selection circuit 2040 according to control signals input from the control terminals 51, 52, 53, and 54, respectively. In FIG. 3, for the sake of simplicity, an example of two amplifiers and an output voltage setting unit is shown, but an appropriate number of capacitors 4011, 4012, 4013, and 4014 are combined.

  FIG. 4 is a diagram showing the relationship between the charge pump output voltage and the oscillation frequency in the configuration of FIG. 1, that is, the frequency control sensitivity. The symbols VCPL and VCPH on the horizontal axis represent the lower limit voltage and the upper limit voltage of the charge pump output voltage, respectively. It is assumed that the variable capacitance element 4020 uses a section having good linearity in the applied voltage vs. capacitance characteristic. The symbols fA1L and fA1H on the vertical axis represent the oscillation lower limit frequency and the oscillation upper limit frequency when the switches 4031, 4032, 4033, and 4034 are all turned on (hereinafter referred to as band A1), and the frequency control sensitivity at this time is βA1. . Symbols fA16L and fA16H represent an oscillation lower limit frequency and an oscillation upper limit frequency when the switches 4031, 4032, 4033, and 4034 are all turned OFF (hereinafter referred to as band A16), and the frequency control sensitivity at this time is βA16.

  FIG. 4 also shows the characteristics of the band B1 and the band B16 in the relationship of the charge pump output voltage versus the oscillation frequency in the configuration of FIG.

  FIG. 5 is a diagram showing the relationship between the charge pump output voltage and the voltage applied to the variable capacitance element, that is, the input / output voltage characteristics of the voltage adjustment circuit 20. As shown in FIG. 5, the voltage adjustment circuit 20 has a function of adjusting the voltage by performing voltage conversion with a linear function on the output signal of the charge pump circuit 10. In this voltage adjustment circuit 20, the conversion coefficient, that is, the gradient, and the value of the output voltage when the lower limit voltage VCPL is input to the voltage adjustment circuit 20 are different for each band. This value is switched according to the control signal from the control terminal.

  When the band A1 is selected, the gain of the voltage adjustment circuit 20 is set to 1, and the input charge pump output voltage is applied to the variable capacitance element as it is. On the other hand, when the band A16 is selected, the gain of the voltage adjustment circuit 20 is set to 1 or less, and the input charge pump output voltage is adjusted and applied to the variable capacitance element. In the example of FIG. 5, when the band A16 is selected, the lower limit of the variable capacitor applied voltage is set to VT16L and the upper limit is set to VCPH.

  More specifically, the output voltage and gain of the voltage adjustment circuit 20 are obtained. For example, when βA16 = βA1 (= βB1), the voltage VT16L is obtained as follows using FIG.

(Equation 7)
(FA16H-fA16L) :( fB16H-fB16L) = βB1: βB16
VT16 = VCPL + (VCPH−VCPL) * {(βB16−βB1) / βB16}
≒ 1.6V
Further, the gain GA16 when the voltage adjustment circuit 20 sets the band A16 is as follows.

(Equation 8)
GA16 = 20 * log (βB1 / βB16)
≒ -7.9dB
According to (Equation 7) and (Equation 8), when the band A16 is selected, the voltage adjustment circuit 20 may set the input voltage 1 to 2V, the output voltage 1.6 to 2V, and the gain to about −7.9 dB.

  By designing the output voltage and gain of the band between the band A1 to the band A16 by the same method, the frequency control sensitivity from the oscillation frequency fA1L to fA16H, that is, the lower limit to the upper limit of the oscillation frequency can be always kept constant. A PLL circuit with low phase noise in the frequency range can be realized.

  In the first embodiment, the configuration of FIG. 2 or FIG. 3 is used for the voltage adjustment circuit 20, but any configuration that can adjust the voltage of the charge pump output voltage may be used.

  Although the non-inverting amplifier is used as the variable gain amplifier of the voltage control circuit 20 in the first embodiment, an inverting amplifier may be used by inverting the upper and lower limit voltages of the charge pump output voltage.

  In the first embodiment, an example in which four capacitors are connected in parallel with the variable capacitance element has been described. However, one or more capacitors may be used so as to obtain a desired oscillation frequency range and frequency control sensitivity. That's fine.

  In the first embodiment, an example using an unbalanced oscillation circuit has been described. However, a balanced oscillation circuit using a differential circuit can also be used.

  In the first embodiment, the varicap diode is used as the variable capacitance element, and the switch and the capacitor connected in series as the capacitor with switching means. However, the capacitance element using the gate capacitance of the MOS transistor may be used. Good.

  In the first embodiment, when the configuration of FIG. 2 is used for the voltage adjustment circuit 20, if a D / A converter is used for the gain / output voltage control circuit 2020, a signal for controlling the gain and the output voltage from the control signal. It is easy to generate.

(Embodiment 2)
FIG. 6 is a circuit diagram showing a configuration of a PLL circuit according to the second embodiment of the present invention. In FIG. 6, the components are the same as those in FIG. 1, so the same reference numerals as those in FIG.

  The signal output from the charge pump circuit 10 is input to the voltage adjustment circuit 20 built in the voltage controlled oscillator 40 after the AC component is removed by the filter circuit 30. The signal input to the voltage adjustment circuit 20 is related to the capacitance values of the capacitors 4011, 4012, 4013, and 4014 connected in series to the switches 4031, 4032, 4033, and 4034 by the control terminals 51, 52, 53, and 54, respectively. After being attenuated or amplified to a set gain and output after being amplified, it is supplied to the variable capacitance element 4020 as a DC voltage, and the variable capacitance element 4020 has a capacitance value corresponding to the supplied DC voltage. Subsequent operations are the same as those shown in FIG.

  That is, in the second embodiment, the connection between the voltage adjustment circuit 20 and the filter circuit 30 is reversed as compared with the first embodiment. The configuration of voltage adjustment circuit 20, the relationship between charge pump output voltage versus oscillation frequency, and the relationship between charge pump output voltage versus variable capacitance element applied voltage are the same as in the first embodiment.

  In the configuration of FIG. 6, the voltage adjustment circuit 20 and the switches 4031, 4032, 4033, and 4034, which are components controlled simultaneously by the control terminals 51, 52, 53, and 54, are arranged close to each other, and the control terminals 51, 52 are arranged. , 53 and 54 can be efficiently wired. In addition, since the wiring connecting the output of the voltage adjustment circuit 20 and one end of the variable capacitance element 4020 can be shortened, voltage noise is hardly superimposed on the wiring, and the capacitance variation of the variable capacitance element due to voltage noise is reduced. The fluctuation is reduced, and a PLL circuit with low phase noise can be realized.

(Embodiment 3)
FIG. 7 is a circuit diagram showing a configuration of a PLL circuit according to Embodiment 3 of the present invention. In FIG. 7, the same components as those in FIG.

  In FIG. 7, reference numeral 31 denotes a filter circuit that removes an AC component. This is a configuration combining the first embodiment and the second embodiment, and is effective when voltage noise is generated in the voltage adjustment circuit 20 in the second embodiment. Since the voltage noise generated in the voltage adjustment circuit 20 is removed, the capacitance fluctuation of the variable capacitance element due to the voltage noise is reduced, the frequency fluctuation of the voltage controlled oscillator is reduced, and a PLL circuit with low phase noise can be realized.

(Embodiment 4)
FIG. 8 is a configuration diagram of a PLL circuit according to the fourth embodiment of the present invention. In FIG. 8, the same components as those in FIG.

  In FIG. 8, reference numeral 80 denotes a low-frequency pass-through / voltage adjustment circuit that can set an arbitrary gain and output voltage by the control terminals 51, 52, 53, and can remove an AC component.

  The signal output from the charge pump circuit 10 is input to the low frequency pass type / voltage adjustment circuit 80 and connected in series to the switches 4031, 4032, 4033, and 4034 by the control terminals 51, 52, 53, and 54, respectively. Attenuated or amplified to a gain set in association with the capacitance values of capacitors 4011, 4012, 4013, and 4014, and further output after AC components are removed. The voltage-adjusted signal from which the AC component has been removed is supplied as a DC voltage to the variable capacitance element 4020 built in the voltage controlled oscillator 40, and the variable capacitance element 4020 has a capacitance value corresponding to the supplied DC voltage. Subsequent operations are the same as those shown in FIG.

  The configuration of FIG. 8 is characterized in that the voltage adjustment circuit 20 in FIG. 1 has the frequency characteristics of the filter circuit 30, and the filter circuit can be reduced to realize a small and low phase noise PLL circuit.

  It should be noted that if the frequency characteristics of the low-frequency passing type / voltage adjusting circuit 80 of the constituent elements in the fourth embodiment are varied by the control terminals 51, 52, 53, 54, the optimum frequency characteristics of the filter depending on the oscillation frequency. And a PLL circuit with low phase noise in a wide frequency band can be realized.

  If the PLL circuit described in Embodiments 1 to 4 is used for a tuner, broadcasting in a wide frequency range can be received, and high-quality video and audio can be reproduced with good phase noise characteristics.

  In addition, if the PLL circuit described in Embodiments 1 to 4 is used in a communication system, it can support communication standards having different frequency bands and can receive and transmit high-quality video, audio, and data with good phase noise characteristics. be able to.

  The PLL circuit of the present invention has good phase noise characteristics over a wide frequency range, and is useful for tuners that require broadcast reception over a wide frequency range and reproduction of high-quality video and audio. It is also useful for communication systems that require communication standards having different frequency bands and high-quality video, audio, and data transmission / reception.

It is a circuit diagram which shows the structure of the PLL circuit in Embodiment 1 of this invention. FIG. 3 is a circuit diagram illustrating an example of a specific configuration of a voltage adjustment circuit in the PLL circuit according to the first embodiment. FIG. 6 is a circuit diagram illustrating another example of a specific configuration of the voltage adjustment circuit in the PLL circuit according to the first embodiment. FIG. 3 is a diagram for explaining a relationship between a charge pump output voltage and an oscillation frequency in the PLL circuit according to the first embodiment. FIG. 4 is a diagram for explaining a relationship between a charge pump output voltage and a variable capacitance element applied voltage in the PLL circuit according to the first embodiment. It is a circuit diagram which shows the structure of the PLL circuit in Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the PLL circuit in Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the PLL circuit in Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the PLL circuit of a prior art. It is a figure explaining the relationship between the charge pump output voltage and oscillation frequency in a prior art PLL circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Charge pump circuit 20 Voltage adjustment circuit 21 Input terminal 22 Output terminal 2010 Variable gain amplifier 2011, 2012 Amplifier 2020 Gain / output voltage control circuit 2030 Output voltage adjustment part 2031, 2032 Output voltage setting part 2040 Amplifier selection circuit 30 Filter circuit 31 Filter Circuit 40 Voltage controlled oscillator 4010, 4011, 4012, 4013, 4014 Capacitor 4020 Variable capacitance element 4031, 4032, 4033, 4034 Switch 4040 Inductor 4050 Oscillator circuit 51, 52, 53, 54 Control terminal 60 Frequency divider 70 Phase comparator 71 Reference frequency input terminal 80 Low frequency pass type, voltage adjustment circuit

Claims (10)

A charge pump circuit;
A voltage adjusting circuit for adjusting a voltage by performing voltage conversion with a linear function on an output signal of the charge pump circuit;
A first filter circuit for removing a noise component from the output signal of the voltage adjustment circuit;
A variable capacitance element that is supplied with voltage from the first filter circuit and is adjusted to a predetermined capacitance value; a capacitor with capacitance switching means connected in parallel to the variable capacitance element; the variable capacitance element and the capacitance switching A voltage-controlled oscillator comprising an inductor that forms a resonance circuit together with a capacitor with means, and an oscillation circuit that oscillates at a frequency corresponding to the resonance frequency of the resonance circuit;
A phase comparator that compares the output signal of the voltage controlled oscillator or a frequency-divided signal thereof with a reference frequency signal, and outputs a comparison result to the charge pump circuit;
A control terminal that switches and controls the voltage conversion coefficient of the voltage adjustment circuit and the capacitance value of the capacitor with the capacitance switching means,
In response to a control signal from the control terminal, the operating voltage of the variable capacitance element is adjusted in conjunction with the switching of the capacitance value of the capacitor with the capacitance switching means, whereby the frequency control sensitivity of the variable capacitance element is set to the capacitance. A PLL circuit that is capable of generating a predetermined frequency of low phase noise in a wide frequency range by adjusting it to be constant in a low state regardless of switching of the capacitance value of the capacitor with switching means.   The voltage adjustment circuit includes a variable gain amplifier having a variable output voltage and a variable gain when a predetermined voltage is input, and an input of the predetermined voltage of the variable gain amplifier according to a control signal from the control terminal. 2. A PLL circuit according to claim 1, further comprising a gain / output voltage control circuit for controlling the output voltage and gain at the time.   The voltage regulator circuit outputs at least two output voltages when a predetermined voltage is input and has at least two amplifiers set so as to have an arbitrary gain, and at least according to a control signal from the control terminal, The PLL circuit according to claim 1, further comprising an amplifier selection circuit that selects one of the two amplifiers.   3. The PLL circuit according to claim 2, wherein the gain / output voltage control circuit comprises a D / A converter.   The PLL circuit according to claim 1, wherein the order of the voltage adjustment circuit and the first filter circuit is switched.   6. The PLL circuit according to claim 5, wherein a second filter circuit for removing a noise component from an output signal of the voltage adjustment circuit is provided between the voltage adjustment circuit and the variable capacitance element.   The PLL circuit according to claim 1, wherein a low-frequency passing type voltage adjusting circuit is used instead of the voltage adjusting circuit and the first filter circuit.   The PLL circuit according to claim 7, wherein the low-frequency pass-through voltage adjusting circuit has a function of changing a frequency characteristic.   A tuner using the PLL circuit according to claim 1 or claim 5.   A communication system using the PLL circuit according to claim 1 or claim 5.

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