JP2005310885A - Printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for making the characteristic impedance of a bus wiring pattern to be substantially identical, irrespective of the positions of the bus wiring pattern and a guard ground in the bus wiring pattern having the guard ground. <P>SOLUTION: The printed wiring board comprises one or more signal layers and solid grounds, wherein the signal layers are adjacent to the solid grounds via an insulating layer. In the printed circuit board, the bus wiring pattern comprises at least four or more signal wirings, solid grounds are disposed with four wiring patters therebetween, and slits are formed at positions on the solid ground, on which the wiring patterns adjacent to the guard grounds superimpose, in the same direction as the bus wiring pattern. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a printed wiring board, and more particularly to a printed wiring board that transmits a high-speed signal using a bus.

  FIG. 4 is a cross-sectional view of a conventional printed wiring board. 4, 1a and 1b are bus wiring patterns, 2 is a guard ground, 3 is a solid ground, 4 is a resist, 5 is an L1 layer, 6 is a first insulating layer, 7 is an L2 layer, and 8 is a second insulating layer. It is.

  2. Description of the Related Art Conventionally, in electronic devices, as disclosed in Japanese Patent Application Laid-Open No. 2001-284827 (Patent Document 1), as a digital signal transmission method between integrated circuits, a parallel transmission method using a bus has been widely performed. . At this time, the signal frequency and the bus width are adjusted according to the necessary information amount, and the optimum value for the electronic device is adjusted. The width of the bus is, for example, 16 or 32. Taking a signal between an integrated circuit and a memory (DRAM) for holding the data as an example, this bus has a data signal, and there are other control signals such as an address signal. Data transfer between the integrated circuit and the memory is performed using a clock signal (for example, a high frequency such as 100 MHz) as a reference signal. For example, if the bus width of the data signal is 32, the signals transmitted through these 32 bus wiring patterns 1a and 1b are the same kind of digital signals, so that crosstalk noise due to simultaneous switching is reduced. A method of arranging the guard ground 2 every four or eight is performed. Furthermore, this guard ground 2 is particularly effective when the number of substrate layers is small, and also acts as a return path for high-frequency current flowing in the data signal by high-speed operation, thus reducing radiation noise radiated from the printed wiring board. Has also contributed.

  In FIG. 4, guard grounds 2 are arranged every four lines on the L1 layer 5 with respect to the bus wiring patterns 1 a and 1 b for transmitting data signals, and the solid ground 3 is arranged as the L2 layer 7. A resist 4 is arranged on the surface, and the bus wiring patterns 1a, 1b and guard ground 2 arranged in the L1 layer 5 are solid ground 3 arranged in the L2 layer 7 through the first insulating layer 6. And constitutes a microstrip line. Further, although not shown, there are a power source layer and a second signal layer under the second insulating layer 8 as L3 layer and L4 layer, and a printed wiring board is formed by stacking these layers.

Here, the thickness of each layer is, for example, A = 20 μm, B = 35 μm, C = 200 μm, D = 35 μm, the width of the bus wiring patterns 1a and 1b of the L1 layer 5 is 125 μm, the distance between the bus wiring patterns is 125 μm, When the characteristic impedance of each of the bus wiring patterns 1a and 1b is calculated with the width of the guard ground 2 being 600 μm, the characteristic impedance of the bus wiring pattern 1a close to the guard ground 2 is 66.0Ω, and the characteristic impedance of the bus wiring pattern 1b is 73. 1Ω, and the difference in characteristic impedance between the bus wiring patterns 1a and 1b is about 7Ω. Here, the width of the guard ground 2 is set such that a through hole (not shown) can be disposed.
JP 2001-284827 A

  However, in the prior art, for example, the characteristic impedance of the bus wiring pattern 1a close to the guard ground 2 is different from that of the bus wiring pattern 1b by the guard ground 2 arranged for reducing crosstalk noise and radiation noise. In comparison, the characteristic impedance varies by about 10% in this example, and the characteristic impedance varies depending on the location where the bus wiring pattern is arranged even though the same kind of digital signal is transmitted. Therefore, there is a problem that the quality of the signal is different, and this is particularly problematic in the case of higher speeds that will continue to advance in the future.

  Furthermore, as a method of aligning the characteristic impedance, there is a method of changing the wiring width of the bus wiring pattern. In order to increase the characteristic impedance, it is generally necessary to form a narrow pattern width. Implementation is often difficult due to plate manufacturing problems and cost constraints.

  The present invention has been made in consideration of such problems of the prior art, and the object of the present invention is to locate the bus wiring pattern and the guard ground in the bus wiring pattern having the guard ground. Regardless, the object is to provide means for making the characteristic impedances of the bus wiring patterns substantially the same.

  In order to achieve the above object, in the present invention, in a printed wiring board comprising one or more signal layers and a solid ground, the signal layer and the solid ground are adjacent to each other via an insulating layer. A guard ground is arranged at least every four bus wiring patterns composed of the above signal wirings and the bus wiring pattern, and a solid ground overlapping with the bus wiring pattern adjacent to the guard ground is in the same direction as the bus wiring pattern. And slits are formed.

  The slit is characterized in that it is arranged on the solid ground of the overlapping portion between the guard ground and the bus wiring pattern further outside the bus wiring pattern adjacent to the guard ground.

  The solid ground is formed in a ground layer.

  Since the present invention is configured as described above, the following effects can be obtained. Regardless of the positional relationship between the bus wiring pattern and the guard ground, the difference in characteristic impedance can be minimized, so that the signal quality of the bus can be made the same regardless of the position of the bus wiring pattern. It becomes possible to improve the reliability.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view of the printed wiring board according to the first embodiment. 4 that are the same as or correspond to those in the conventional example in FIG. 4 are denoted by the same reference numerals, and the differences from the conventional example will be mainly described below.

  In FIG. 1, 9 is a slit. FIG. 2 is a perspective view of the printed wiring board according to the first embodiment. In FIG. 1 and FIG. 2, the guard ground 2 is arranged every four bus wiring patterns 1a and 1b and every four bus wiring patterns 1a and 1b. Furthermore, the guard ground 2 has a width that allows a through hole (not shown) to be disposed on the guard ground 2. Further, in FIG. 1, four bus wiring patterns 1a and 1b and guard grounds 2 are arranged on both sides of the bus wiring patterns 1a and 1b. The same applies to FIG.

  And the thickness of each layer is the same as the conditions described in the prior art, for example, A = 20 μm, B = 35 μm, C = 200 μm, D = 35 μm, the width of the bus wiring pattern 1a, 1b of the L1 layer 5 is 125 μm, The distance between the bus wiring patterns is 125 μm, and the width of the guard ground 2 is 600 μm.

  At this time, the width of the slit 9 arranged in the solid ground 3 is the sum of the distance between the bus wiring pattern 1a and the adjacent guard ground 2 and the distance to the bus wiring pattern 1b on the opposite side ( In this example, when the characteristic impedance is calculated assuming that the slit width is 375 μm, the characteristic impedance of the bus wiring pattern 1a is 76.8Ω, the characteristic impedance of the bus wiring pattern 1b is 78.9Ω, and the characteristic impedance of the bus wiring patterns 1a and 1b. The difference is about 2Ω. The characteristic impedances described in the prior art are 66.0Ω for the bus wiring pattern 1a and 73.1Ω for the bus wiring pattern 1b, and the difference thereof is about 7Ω. Variations in characteristic impedance in the entire pattern can be greatly reduced.

  Thus, by arranging the slit 9 in the solid ground 3 corresponding to the bus wiring pattern 1a, the difference in characteristic impedance generated by the positional relationship between the bus wiring patterns 1a, 1b and the guard ground 2 can be minimized. Therefore, the signal quality can be made the same regardless of the position of the bus wiring pattern, and the reliability of the electronic device can be improved.

  FIG. 3 is a cross-sectional view of the printed wiring board according to the second embodiment. FIG. 3 assumes a build-up substrate in which the first insulating layer 6 is formed thin. Therefore, the thickness of each layer is, for example, A ′ = 20 μm, B ′ = 32 μm, C ′ = 60 μm, D ′ = 32 μm, the width of the bus wiring patterns 1a and 1b of the L1 layer 5 is 100 μm, and the distance between the bus wiring patterns Is 100 μm and the width of the guard ground 2 is 300 μm. Here, the width of the guard ground 2 is set such that a photo via (not shown) in the build-up substrate can be arranged.

  In this case, in order to make the characteristic impedances of the bus wiring patterns 1a and 1b substantially the same, two slits 9 of a distance (= 100 μm width) from the surrounding pattern of the bus wiring pattern 1a are arranged on the solid ground 3. ing. Unlike the first embodiment, since the first insulating layer 6 is thin, the solid ground 3 of the bus wiring patterns 1a and 1b is strongly coupled, and the influence of the guard ground is small. The difference in impedance is originally small.

  For example, the characteristic impedance when the solid ground 3 has no slit, that is, the solid ground 3 corresponding to the bus wiring patterns 1a and 1b is free of defects such as slits, the characteristic impedance of the bus wiring pattern 1a is 44. 3Ω and the bus wiring pattern 1b are 45.6Ω, and the difference between the bus wiring patterns 1a and 1b is about 1.3Ω.

  However, according to the second embodiment of the present invention, the slits 9 are arranged in the solid ground 3 corresponding to the bus wiring pattern 1a. At this time, when the respective characteristic impedances are calculated, the characteristics of the bus wiring pattern 1a are calculated. The impedance is 48.9Ω, the characteristic impedance of the bus wiring pattern 1b is 47.9Ω, and the difference between the bus wiring patterns 1a and 1b is 1.0Ω. Therefore, it is possible to minimize the difference in characteristic impedance regardless of the positional relationship between the bus wiring pattern and the guard ground with higher accuracy. Therefore, the signal quality should be the same regardless of the position of the bus wiring pattern. It is possible to improve the reliability of the electronic device.

  In this embodiment, the L1 layer 5 of the printed wiring board is a signal layer in which the bus wiring patterns 1a and 1b and the guard ground 2 are arranged, and the L2 layer 7 is a layer in which the solid ground 3 is arranged. Although the case where the first insulating layer 6 is adjacent to each other has been described, the present invention is not limited to this, and the signal layer and the solid ground on which the bus wiring patterns 1a and 1b and the guard ground 2 are arranged are described. Since the same effect can be acquired because 3 adjoins through an insulating layer, it is not limited to each being comprised with the L1 layer 5 and the L2 layer 7. FIG. Further, even in the case where the signal layer having the bus wiring patterns 1a and 1b and the guard ground 2 constitutes a strip line in which the solid ground 3 is arranged in both the upper and lower directions through the insulating layer, it is adjacent to the upper and lower sides. The same effect can be obtained by arranging the slits 9 in the portions where the bus wiring pattern 1a adjacent to the guard ground 2 overlaps both of the solid grounds 3 to be performed. In the present embodiment, the width of the guard ground 2 is set so that a through hole or the like can be arranged. However, the width is defined if the wiring has a ground potential that can serve as a return path for a high-speed signal current. is not. In these embodiments, since a slit width different from that of the present embodiment is required, the width of the slit 9 can be adjusted by calculating the characteristic impedance for each of the bus wiring patterns 1a and 1b. Further, although the solid ground 3 is arranged on the L2 layer 7, there is no problem even if the L2 layer 7 is the ground layer.

  As described above, the present invention is not limited to the above-described embodiments, and various configurations can be taken without departing from the gist of the present invention.

Sectional drawing of the printed wiring board concerning Example 1. FIG. The perspective view of the printed wiring board concerning Example 1. FIG. Sectional drawing of the printed wiring board concerning Example 2. FIG. Sectional view of a conventional printed wiring board

Explanation of symbols

1a, 1b Bus wiring pattern 2 Guard ground 3 Solid ground 4 Resist 5 L1 layer 6 First insulating layer 7 L2 layer 8 Second insulating layer 9 Slit A, A 'Resist thickness B, B' L1 layer conductor thickness C, C ' First insulation layer thickness D, D 'L3 layer conductor thickness

Claims (3)

  A printed circuit board comprising at least one signal layer and a solid ground, the signal layer and the solid ground being adjacent to each other via an insulating layer; a bus wiring pattern comprising at least four signal wirings; Guard grounds are arranged at least every four bus wiring patterns, and slits are formed in the same direction as the bus wiring patterns on the solid ground that overlaps the bus wiring patterns adjacent to the guard ground. A printed wiring board characterized by comprising:   The said slit is arrange | positioned in the said solid ground of the part which overlaps between the bus wiring patterns further outside the bus wiring pattern adjacent to the said guard ground from the said guard ground. Printed wiring board.   The printed wiring board according to claim 1, wherein the solid ground is formed in a ground layer.

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