JP2005310250A - Semiconductor storage device and digital filter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor storage device which can achieve highly integrated circuit in a digital filter using the pre-adding technique. <P>SOLUTION: A memory cell array consists of a plurality of memory cells 20 arranged in the shape of a two-dimensional matrix in a row direction and a column direction. It is equipped with a wordline 34 group which selects a row address of the memory cell array, a bit line 35 group and a bit line 36 group which select the column address. An odd-numbered memory cell among memory cells arranged in the column direction is connected to the bit line 36 via a switch 21, and an even-numbered memory cell is connected to the bit line 35 via the switch 21. Two wordlines in the wordline 34 group are simultaneously selected on prescribed conditions by using column decoders 31 and 32, stored data of the selected memory cell 20 is read to the bit line 35 group and the bit line 36 group simultaneously. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device including a single-port memory cell and a digital filter using the same, and more particularly, a semiconductor memory suitable for constructing a digital filter or the like used as an interpolation filter for a ΔΣ DA converter. The present invention relates to a device and a digital filter using the device.

  Conventionally, as an interpolation digital filter of an oversampling type DA converter such as a ΔΣ type DA converter, a half band FIR filter that performs an operation represented by the following equation (1) (Finite Impulse Response Filter) is known.

The calculation shown in the above equation (1) is performed as shown in FIG. 8 during one cycle from when the latest time series data X is input to when the latest time series data is input next. In addition, time series data X (z ^−k ) (k indicates that how many cycles the data is stored in the storage device) stored in the storage device (memory) 7 in advance is stored from the storage device 7. This is possible by reading, multiplying the read time series data X (z ^−k ) by a predetermined coefficient h _2k−1 , and cumulatively adding the multiplication results. At this time _, the total number of data to be cumulatively added is an arbitrary even number n.

Here, when the digital filter is realized, the above equation (1) is modified as shown in the following equation (2) using the properties of the FIR filter having a time-symmetric coefficient, and the same coefficient is multiplied by 2 The number of multiplications can be halved by adding the data first and then multiplying the addition result by a coefficient.
The time target coefficient _{here, (1) h n + m} = h nm as in the condition of formula (where, n is an even number, m is 0 or a positive integer) and a like around the h _n Refers to a coefficient that is symmetric. Hereinafter, this method is referred to as pre-adding.
Since the following equation (2) uses the time-series symmetry of the coefficient, not only the half-band FIR filter but also all the digital filters having the characteristic that the coefficient is time-sequentially halved in the same way. Is possible.

As shown in FIG. 9, the calculation shown in the above equation (2) is performed by using time series data X (z ^−k ) and X (z ^{− (n−k +} ) stored in the storage device 12 in advance. ¹⁾ ) are read out simultaneously, and the read time series data X (z ^−k ) and X (z ^{− (n−k + 1)} ) are added, and a predetermined coefficient h is added to the addition result. _This is done by multiplying _2k-1 and cumulatively adding the multiplication results.
While there is a time limit of one cycle, halving the number of multiplications makes it possible to design a hard filter that makes use of any of the following advantages to construct an FIR filter.

(1) The number of operations can be increased to increase the number of FIR taps, which is advantageous for improving the performance of the FIR filter characteristics.
(2) When the same hardware is used in multiple channels in a time-sharing manner, the calculation time is shortened, so the remaining calculation time is allocated to the calculation time of other channels, so that the multi-channel hardware can be shared and integrated circuit integrated. Is advantageous.
(3) When the same hardware is used in a time-sharing manner with multiple channels, the calculation time is shortened, which is advantageous for increasing the speed of the FIR filter.

A semiconductor memory device used for the digital filter as described above will be described below. When the digital filter represented by the above equation (2) is realized for any even number n of time series data X stored in the semiconductor memory device, the timing chart of FIG. 10 is used.
That is, as shown in FIG. 10, time series data is output from the semiconductor memory device 12 in response to the clock signal CLK2 having ((n / 2) -1) times in one cycle indicated by the clock signal CLK1. A and B, two each, that is, X (z ^{− (n / 2)} ) and X (z ^{− (n / 2 + 1)} ), X (z ^{− (n / 2-1)} ) and X (z ^{− (n / 2 + 2)} ),... X (z ⁻¹ ) and X (z ⁻ⁿ ) and other data pairs that should be multiplied by the same coefficient must be output simultaneously to the adder.

As an example of such a semiconductor memory device, the one shown in FIG. 11 is known (for example, see Patent Document 1).
In this semiconductor memory device, as shown in FIGS. 11 and 12, a memory cell array is composed of memory cells 17 having two outputs called dual ports. In the dual port type memory cell 17, one memory cell has two extraction ports as shown in FIG. 12 with respect to the single port type memory cell 20 shown in FIG. Data can be taken from either of the two connected lines.

  The semiconductor memory device shown in FIG. 11 comprises a memory cell array using dual-port memory cells 17 capable of storing n pieces of time-series data, and has two systems of row decoders for selecting word lines of a word line group. is doing. The two-system row decoder includes a first row decoder 22 and a second row decoder 23, and supplies respective outputs to the first word line 24 group and the second word line 25. Yes.

Each memory cell 17 has switches 18 and 19, and the switch 18 is ON / OFF controlled by a signal on the word line 24, and the switch 19 is ON / OFF controlled by a signal on the word line 25.
That is, the switch 18 of the memory cell 17 arranged in each row direction is turned on only by a signal of a certain word line 24 in the word line 24 group, and the switch 19 of the memory cell 17 arranged in each row direction It is configured to be turned on only by a signal of a certain word line 25 in the line 25 group.

The switch 18 of the memory cell 17 is connected to the bit line 27, and the switch 19 of the memory cell 17 is connected to the bit line 26. Further, a sense amplifier 28 is connected to each bit line 26, and a sense amplifier 29 is connected to each bit line 27.
That is, the data of the memory cell 17 selected in the first word line group 24 is connected to the first bit line connected by turning on the switches 18 of all the memory cells 17 arranged in the row direction in the memory cell array. 27 through the first sense amplifier 29 as the first half (here, X (z ⁻¹ ) to X (z ^{− (n / 2)} )).

On the other hand, the data of the memory cell 17 selected in the second word line 25 group is connected to the second bit line connected by turning on the switches 19 of all the memory cells 17 arranged in the row direction in the memory cell array. 26 to the second half (here, X (z ^{− (n / 2 + 1)} ) to X (z ⁻ⁿ )) is output via the second sense amplifier 28.
Here, the data stored in the memory cell at a certain address becomes both the first half and the latter half of the time-series data added by pre-adding. In order to have separate output when calculated as the first half and output when calculated as the second half, dual port cells were used to enable simultaneous output of data pairs required for pre-adding .
JP 2002-133872 A

By the way, in a semiconductor memory device having a memory cell array composed of a large number of memory cells, the larger the size of the memory cell array, the smaller the area of each memory cell is advantageous for integration.
However, in the semiconductor memory device described in Patent Document 1, since the memory cell is a dual port type memory cell, there are two memory cell take-out ports, and the area is large, which makes it unsuitable for integrated circuit and area saving. It is.
In view of the above, an object of the present invention is to provide a semiconductor memory device capable of providing two outputs for pre-adding that can be highly integrated, and a small-area digital filter including the semiconductor memory device. There is.

  In order to solve the above problems, the present inventor has a configuration of a semiconductor memory device capable of obtaining two outputs for pre-adding a memory cell array using a single-port memory cell having a smaller area than a dual-port memory cell. As a result, the present inventors have found a small-scale configuration of the row decoder, and have completed the present invention having the following configuration.

  That is, the invention according to claim 1 is a memory cell array composed of a plurality of memory cells arranged in a two-dimensional matrix in the row direction and the column direction, a word line group for selecting a row address of the memory cell array, and the column direction. A first bit line group for selecting a column address of the memory cell array and an even-numbered memory cell arranged in the column direction. A second bit line group that is connectable to a memory cell and selects a column address of the memory cell array; and a sense amplifier group that outputs each output data on the first and second bit line groups; , Two word lines in the word line group are simultaneously selected under a predetermined condition, and data stored in a memory cell selected according to the selection is stored in the first Comprises a reading means for reading at the same time and the bit line group second bit line group, the.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the reading unit generates and outputs a signal for selecting a predetermined one word line in the word line group. A row decoder; a second row decoder for generating and outputting a signal for selecting one other predetermined word line of the word line group; and a logic of each corresponding output signal output from the both row decoders A plurality of OR circuits each performing a sum operation, and each output signal of the plurality of OR circuits is supplied to each word line of the word line group.
According to such a configuration, a semiconductor memory device capable of obtaining the necessary two outputs can be realized by a memory cell array composed of single-port memory cells, and a highly integrated circuit can be realized.

According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect, each of the first and second row decoders includes a first shift register and a second shift register. The output of the flip-flop is fed back to the flip-flop of the first stage so that the data of the shift register is circulated, and the direction in which the data of the first shift register and the second shift register circulates is as follows: The directions are opposite to each other.
Here, when the direction of circulation is opposite to each other, if one of the row decoders sequentially selects in the direction of the upper row, the other row decoder sequentially selects in the direction of the lower row. It means to go.
According to such a configuration, it is possible to sequentially read out the rows of the memory cell array without having a complicated row decoder.

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the memory cell array has a first row, a ((N / 2) +1) th row, a second row, and a ((N / 2) +2 ) Line, ... I line, ((N / 2) + I) line, ... ((N / 2) -1) line, (N-1) line, (N / 2) The first and second shift registers are each configured by connecting half the flip-flops of N rows in series, and the shift register Each of the flip-flops has a selection unit, and the first selection unit can select either the first row or the ((N / 2) +1) th row, and the second selection unit has two rows. Either the first or the ((N / 2) +2) th row can be selected, and the I-th selection section is the Ith row and the ((N / 2) + I) th row. One of out was set to be configured to be selected.
According to such a configuration, the selection destination of the row decoder can be moved to a row separated by N / 2 only by changing the selection of the selection unit, and the row decoder selection start row (shift start row of the shift register) at the start of the cycle The circuit scale can be reduced without the need for a circuit for storing the data.

According to a fifth aspect of the present invention, there is provided the semiconductor memory device according to any one of the first to fourth aspects, an adding means for adding the first output and the second output output from the semiconductor memory device, Multiplying means for multiplying the output signal added by the adding means by a coefficient, and cumulative addition means for cumulatively adding the multiplication results multiplied by the multiplication means. According to such a configuration, pre-adding is provided. The digital filter can be realized with a small area circuit.

In the present invention configured as described above, the memory cell array can be composed of single-port type memory cells, so that it can be integrated as compared with the conventional circuit. In the configuration of the row decoder, the row decoder selection start row can be selected. The circuit scale can be reduced without requiring a circuit to be stored.
Therefore, according to the present invention, it is possible to realize a semiconductor memory device that can be highly integrated in a digital filter using a pre-adding technique, and to realize a small-area digital filter.

Embodiments of the present invention will be specifically described below with reference to the drawings.
(First Embodiment of Semiconductor Memory Device)
A schematic configuration of the first embodiment of the semiconductor memory device of the present invention will be described with reference to FIG.
In the first embodiment of the semiconductor memory device, as shown in FIG. 1, a plurality of single-port memory cells 20 are two-dimensionally arranged in a row direction (horizontal direction in the figure) and a column direction (vertical direction in the figure). A memory cell array arranged in a matrix is provided.

Corresponding to the arrangement of the memory cells 20, groups of word lines 34 for selecting a row address of the memory cell array are arranged in the row direction. In the column direction, a group of bit lines 35 and a group of bit lines 36 for selecting a column address of the memory cell array are arranged.
Here, the bit line 35 and the bit line 36 together form a pair of bit lines, thereby selecting the column address of the memory cell array.

  As shown in FIGS. 1 and 2, each memory cell 20 arranged in each column direction is alternately connected to the bit line 35 and the bit line 36 via the switch 21. That is, as shown in FIG. 2, for each memory cell 20 arranged in the column direction, the bit line 35 and the bit line 36 are alternately arranged with respect to the data stored in order in time series. The memory cells 20 are alternately connected.

  At the tip of each bit line 35, a sense amplifier 37 for outputting the data read on each bit line 35 is provided. A sense amplifier 38 for outputting data read on each bit line 36 is provided at the tip of each bit line 36. A desired data pair 39 can be obtained from the sense amplifiers 37 and 38.

  In the first embodiment, in order to select (designate) two row addresses using two predetermined word lines 34 of the group of word lines 34, a row decoder 31, a row decoder 32, Each of the row decoders 31 and 32 includes a plurality of OR circuits 33 that perform a logical sum operation of the corresponding outputs, and the outputs of the OR circuits 33 are supplied to the corresponding word lines 34. Each switch 21 corresponding to each memory cell 20 is on / off controlled in accordance with a signal on each word line 34.

According to the first embodiment having such a configuration, a semiconductor memory device capable of obtaining two necessary outputs can be realized by a memory cell array of single-port type memory cells, and a highly integrated circuit can be realized. The reason will be described below.
Focusing on the time-series data X (z ^−k ) and X (z ^{− (n−k + 1)} ) that require simultaneous output from the above equation (2), n, which is the total number of data, is an even number. Therefore, when k is an even number (n−k + 1), it is an odd number, and when k is an odd number (n−k + 1) is an even number.

That is, if the first data to be output by the semiconductor memory device at a certain time is an odd number, the second data to be paired is an even number, and if the first data is an even number, the pair is The second data is an odd number. The data pairs required for pre-adding cannot both be odd or both even.
Therefore, in the memory cell array, the odd-numbered memory cell group and the even-numbered memory cell group have the bit lines, respectively, so that necessary two-series output data can be taken out as in the prior art.

That is, according to the first embodiment, two addresses are selected in order to obtain two outputs in the group of word lines 34. However, since the two data stored in the two addresses are always odd-numbered and even-numbered memory cells 20, they are output from different bit lines 35 and 36, respectively. Therefore, even if two addresses are selected for one bit line group, the output data does not collide.
When data is stored in time series in the row direction of the memory cell array (see FIG. 2), a set of bit lines are alternately connected. Furthermore, as long as the data stored in the memory cell array does not share the same bit line as the temporally continuous data, the data storage method can be arbitrarily set without being time-sequential in the row direction.

Next, a specific configuration of the memory cell 20 and the like illustrated in FIG. 1 will be described with reference to FIG.
FIG. 3 shows an example in which a MOS transistor is used as the memory cell 20 to form an integrated circuit, which is configured by a static random access memory (SRAM) circuit.
Normally, in an SRAM circuit, as shown in FIG. 3, each memory cell constituting a memory cell array is composed of an inverter 20a and an inverter 20b, and has one system output with one set of a positive logic output and a negative logic output. It has become.

  Therefore, the single port type memory cell has two switches composed of MOS transistors 21a and 21b as shown in the figure, and the gates of the MOS transistors 21a and 21b are connected to the corresponding word lines 34, respectively. Then, the level difference between the bit lines 35a and 35b and the level difference between the bit lines 36a and 36b are amplified by the connected sense amplifiers 37 and 38, respectively, and used as a digital signal output 39 of "H" level or "L" level. It is designed to output.

As described above, the single-port memory cell used in FIG. 3 has fewer one-system outlets than the dual-port memory cell. In a single-port type memory cell, normally, two MOS transistors are required for one extraction port. For this reason, in the case of a single port type memory cell in which two MOS transistors can be omitted, the memory cell array of the memory circuit has an area of about 2/3 as compared with the case of a dual port type memory cell. It became possible to realize.
Although FIG. 3 shows an example using an SRAM circuit, it may also be realized by a dynamic random access memory (DRAM) circuit.

Next, specific configurations of the row decoder 31 and the row decoder 32 shown in FIG. 1 will be described with reference to FIG.
The row decoder 31 includes a shift register as shown in FIG. That is, (N / 2) flip-flop circuits (FF circuits) 41 are connected in series, the output of the final stage FF circuit 41 is fed back to the input side of the first stage FF circuit 41, and each FF Each output from the circuit 41 is taken out. Each FF circuit 41 is supplied with a first direction reference clock signal (hereinafter referred to as a clock signal) CLKA, and the first stage FF circuit 41 is supplied with a reset signal RESET via an inverter 42. The reset signal RESET is supplied as it is to the other FF circuits 41.

  That is, each FF circuit 41 receives the output of the FF circuit 41 in the previous stage and the clock signal CLKA, sequentially shifts the output of the FF circuit 41 in synchronization with the clock signal CLKA, and the FF circuit 41 in the final stage. The output is input to the first stage FF circuit 41, and the output of the FF circuit 41 is circulated. Here, the clock signal CLKA is a signal in which a square wave having a predetermined period is repeated ((N / 2) −1) times in one cycle.

  In the row decoder 31 configured in this manner, in the initial state (when reset by the reset signal RESET), only the first-stage FF circuit 41 among the connected N FF circuits 41 is set to the “H” level. Other FF circuits 41 are set to the “L” level. Therefore, the “H” level is sequentially shifted in the FF circuit 41 in synchronization with the clock signal CLKA, and the word line one level lower than the currently selected word line is sequentially synchronized in synchronization with the clock signal CLKA. Will choose.

  The row decoder 32 includes a shift register as shown in FIG. That is, (N / 2) flip-flop circuits (FF circuits) 43 are connected in series, the output of the final stage FF circuit 43 is fed back to the input side of the first stage FF circuit 43, and Each output from the FF circuit 43 is taken out. Each FF circuit 43 is supplied with a second direction reference clock signal (hereinafter referred to as a clock signal) CLKB, and the first stage FF circuit 43 is supplied with a reset signal RESET via an inverter 44, except for the first stage. The reset signal RESET is supplied to the FF circuit 43 as it is.

  That is, each FF circuit 43 receives the output of the preceding FF circuit 43 and the clock signal CLKB, and sequentially shifts the output of the FF circuit 43 in synchronization with the clock signal CLKB. The output is input to the first stage FF circuit 43, and the output of the FF circuit 43 is circulated. Here, the clock signal CLKB is a signal in which a square wave having the same cycle as the clock signal CLKA is repeated ((N / 2) −1) times in one cycle.

In the row decoder 32 configured in this way, in the initial state, only the first stage FF circuit 43 among the N connected FF circuits 43 is set to the “H” level, and other FF circuits 43 are set to “L”. The level is set. Therefore, the “H” level sequentially shifts the FF circuit 43 in synchronization with the clock signal CLKB, and is one higher than the currently selected word line in synchronization with the clock signal CLKB (with the row decoder 31). The word lines in the opposite direction are sequentially selected.
Each output from the row decoder 31 and each corresponding output from the row decoder 32 are supplied to each corresponding OR circuit 33 among the plurality of OR circuits 33 shown in FIG.

(Second Embodiment of Semiconductor Memory Device)
The configuration of the second embodiment of the semiconductor memory device of the present invention will be described with reference to FIG.
The second embodiment of the semiconductor memory device is based on the first embodiment shown in FIG. 1, and as a row decoder for selecting (designating) a row of the memory cell array, as shown in FIG. The selection circuits 61 and 62 and the selection control circuits 63 and 64 are added to the row decoders 31 and 32 shown in FIG.
In the second embodiment, the word lines (row addresses) of the memory cell array are the first row, the ((N / 2) +1) th row, the second row, the ((N / 2) +2) row, ... I line, ((N / 2) + I) line, ... ((N / 2) -1) line, (N-1) line, (N / 2) line, N It is composed of N rows arranged in the order of rows.

Since the row decoders 31 and 32 have the same configuration as that of the row decoders 31 and 32 shown in FIG. 4, the same components are denoted by the same reference numerals, and the description thereof is omitted.
As shown in FIG. 5, the selection circuit 61 includes a switch 49 group and a switch 50 group, and each output of each FF circuit 41 constituting the row decoder 31 is selectively selected by each set of switches 49 and 50. It comes to take out. That is, the switches 49 and 50 which are selection units of the selection circuit 61 select one of two rows that are adjacent to each other on the memory cell array and are sequentially separated by (N / 2).

  Further, referring to FIG. 5 in detail, the switches 49 and 50 related to the first stage FF circuit 41 of the row decoder 31 can select the Nth row when the switch 49 is closed, and when the switch 50 is closed. The N / 2nd row can be selected. Further, the switches 49 and 50 related to the second stage FF circuit 41 of the row decoder 31 can select the (N−1) th row when the switch 49 is closed, and (N / N) when the switch 50 is closed. 2) -1) The row can be selected. The switches 49 and 50 related to the FF circuit 41 in the final stage of the row decoder 31 can select the ((N / 2) +1) row when the switch 49 is closed, and one row when the switch 50 is closed. The eyes can be selected.

The selection control circuit 63 selectively turns on and off the switch 49 group and the switch 50 group. For this purpose, the selection control circuit 63 performs an OR operation on the clock signal CLK1 and the output of the FF circuit 41 at the final stage of the row decoder 31, and the output of the OR circuit 53, as shown in FIG. There is provided a toggle flip-flop circuit (TFF circuit) 54 for inputting a signal and generating a signal for selectively turning on and off the switch 49 group and the switch 50 group.
As shown in FIG. 5, the selection circuit 62 includes a switch 51 group and a switch 52 group, and each output of each FF circuit 43 constituting the row decoder 32 is selectively selected by each set of switches 51 and 52. It comes to take out.

  Further, in detail with reference to FIG. 5, the switches 51 and 52 related to the first stage FF circuit 43 of the row decoder 32 can select the ((N / 2) +1) -th row when the switch 51 is closed, When the switch 52 is closed, the first line can be selected. Further, the switches 51 and 52 related to the FF circuit 43 immediately before the last stage of the row decoder 32 can select the (N−1) th row when the switch 51 is closed, and when the switch 52 is closed ( (N / 2) -1) The row can be selected. The switches 51 and 52 related to the FF circuit 43 in the final stage of the row decoder 32 can select the Nth row when the switch 51 is closed, and select the (N / 2) th row when the switch 52 is closed. It can be done.

The selection control circuit 64 selectively controls on / off of the switch 51 group and the switch 52 group. For this purpose, as shown in FIG. 5, the selection control circuit 64 performs an OR operation on the clock signal CLK1 and the output of the first stage FF circuit 43 of the row decoder 32, and the output signal of the OR circuit 55. And a TFF circuit 56 for generating a signal for selectively turning on and off the switch 51 group and the switch 52 group.
Each output of the FF circuit 41 of the row decoder 31 selected by the selection circuit 61 and each output of the FF circuit 41 of the row decoder 31 selected by the selection circuit 62 are logically ORed by an OR circuit. Is used as a word signal for selecting a row.

Next, an operation example of the row decoder according to the second embodiment configured as shown in FIG. 5 will be described with reference to FIG.
As shown in FIG. 6, when the clock signal CLK1 falls, the selection control circuit 63 thereby turns on the switch 50 group of the selection circuit 61. Therefore, the word line corresponding to the (N / 2) th row address is selected by the output of the first stage FF circuit 41 of the row decoder 31, and the memory cell in that row is selected. Data X (N / 2) stored in the memory cell is output.

Next, when one clock of the clock signal CLKA elapses, the “H” level signal, which is the output of the first stage FF circuit 41, is shifted to the next stage FF circuit 41 in synchronization with the clock signal CLKA and one lower level. ((N / 2) -1), which is the address line, is selected, and data X (N / 2-1) is read in the same manner as described above.
Then, as shown in FIG. 6, the above procedure is repeated until the clock of the clock signal CLKA runs out, and when the data X (1) stored in the memory cell corresponding to the lowest address row is read, the address row This completes the selection and reading of data.

  On the other hand, in parallel with these operations, as shown in FIG. 6, when the clock signal CLK1 falls, the selection control circuit 64 turns on the switch 51 group of the selection circuit 61. Therefore, the word line corresponding to the ((N / 2) +1) -th row address is selected and the memory cell in that row is selected by the output of the first stage FF circuit 43 of the row decoder 32, and the selection is made. Data X (N / 2 + 1) stored in each memory cell is output.

Next, when one clock of the clock signal CLKB elapses, the “H” level signal that is the output of the first stage FF circuit 43 is shifted to the next stage FF circuit 43 in synchronization with the clock signal CLKB, and is one higher level. The ((N / 2) +2) th row is selected, and data X (N / 2 + 2) is read in the same manner as described above.
Then, as shown in FIG. 6, the above procedure is repeated until the clock signal CLKB reaches the ((N / 2) -1) th clock, and the clock signal CLKB reaches the ((N / 2) -1) th clock. That is, in this cycle, X (N) which is the latest data is written and read out simultaneously on the Nth row when starting from the ((N / 2) +1) th row.

  Thereafter, as shown in FIG. 6, when two clock signals CLKB are input, the “H” level of the FF circuit 43 is shifted two more times. Among them, the first clock of the clock signal CLKB shifts further from the highest FF circuit 43 to the highest. Therefore, the output QA of the TFF circuit 56 of the selection control circuit 64 changes from the “H” level to the “L” level, the switch 52 group is turned on, and the selection circuit 62 selects the address of the first row. Further, in the second clock of the clock signal CLKB, the selection circuit 62 selects the second row address and ends the operation of this cycle.

  Then, if the next cycle starts, as shown in FIG. 6, the output QA of the TFF circuit 54 of the selection control circuit 63 changes from “L” level to “H” level by the falling of the clock signal CLK1, and the switch 49 The group is turned on, and the selection circuit 61 selects the ((N / 2) +1) th row. Then, the data X (N / 2 + 1) stored in the memory cell of the selected row is output.

  Next, if one clock of the clock signal CLKA has elapsed, the “H” level signal that is the output of the FF circuit 41 is shifted in synchronization with the clock signal CLKA, and the next lower address row is selected. , The FF circuit 41 corresponding to the ((N / 2) +1) th row is the lowest order. Therefore, when the output of the FF circuit 41 shifts, the selection control circuit 63 turns on the switch 50 group. As a result, the selection circuit 61 selects the (N / 2) th row, and data X (N / 2) is read from the memory cell of the selected row in the same procedure as described above.

Then, as shown in FIG. 6, the above procedure is repeated until the clock of the clock signal CLKA runs out, and when the data X (2) stored in the memory cell corresponding to the lowest address row is read, the address row This completes the selection and reading of data.
On the other hand, in parallel with these operations, as shown in FIG. 6, when the clock signal CLK1 falls, the output QB of the TFF circuit 56 of the selection control circuit 64 changes from “L” level to “H” level, and the switch The 51st group is turned on, and the selection circuit 62 selects the ((N / 2) +2) th row. Then, data X (N / 2 + 2) stored in the memory cell of the selected row is output.

Next, assuming that one clock of the clock signal CLKB has elapsed, the “H” level signal that is the output of the FF circuit 43 is shifted in synchronization with the clock signal CLKB and is the next higher address row ((N The / 2) +3) th row is selected, and data X (N / 2 + 3) is read in the same procedure as described above.
Then, as shown in FIG. 6, the above procedure is repeated until the clock signal CLKB reaches the ((N / 2) -1) th clock, and the clock signal CLKB reaches the ((N / 2) -1) th clock. In this cycle, since it started from the ((N / 2) +2) th row, X (N + 1) which is the latest data is written to the first row, and it is read at the same time.

Thereafter, as shown in FIG. 6, when two clock signals CLKB are input, the “H” level of the FF circuit 43 is shifted two more times. The selection circuit 62 selects the third row address by the second clock of the clock signal CLKB, and the operation of the second cycle is completed.
Thereafter, the operation of each cycle is started in accordance with the clock signal CLK1, and the operation of the third cycle is as shown in FIG. 6, and each operation of each cycle after the fourth time is the same as described above.
As described above, according to the second embodiment, the selection destination of the row decoders 31 and 32 can be moved to a row separated by N / 2 by the selection operation of the selection circuits 61 and 62. The circuit scale can be reduced without requiring a circuit for storing the selection start row (shift start row of the shift register).

Next, the operation will be described with reference to Table 1.
When the row decoder 31 shifts to a lower row, output starts from X (z ^{− (n / 2 + 1)} ) from a certain arbitrary row A. Since the selected row of the row decoder is shifted ((N / 2) -1) times in one cycle, it moves to the A-((N / 2) -1) row and the selection is completed.
In order to output X (z ^{− (n / 2 + 1)} ) in the next cycle, it is necessary to start selection from the (A + 1) row, which is the selection part of the selection circuits 61 and 62. It can be realized by switching.
Therefore, if the selection destination can be changed to a row separated by N / 2 rows after ((N / 2) -1) shifts, the selection start row can be shifted by every row, so the same order in each cycle. You can start selecting from the data.

(Embodiment of digital filter)
Next, an embodiment of the digital filter of the present invention will be described with reference to FIG.
FIG. 7 is a schematic configuration diagram of a ΔΣ DA converter using an embodiment of the digital filter of the present invention.
As shown in FIG. 7, this ΔΣ DADA converter includes interpolation filters 1, 2, and 3, a ΔΣ modulator 4, and low-pass filters 5a and 5b.
The interpolation filters 1 to 3 are digital filters having a predetermined frequency characteristic by interpolating each input digital signal to increase the sampling frequency. The ΔΣ modulator 4 is also called a noise shaper, and pushes noise up to a high frequency and outputs a 1-bit or multi-bit density-modulated PDM signal.

  In the block diagram shown in FIG. 7, the digital signal is mainly time-divided and processed by the same hardware, and is separated into multiple channels at the output of the ΔΣ modulator 4. After separation for each channel, high-frequency noise is removed by low-pass filters 5a and 5b, respectively, and an analog signal is output. Interpolation filters 1 to 3 are each constituted by a digital filter, and a pre-adding method is adopted by a half-band FIR filter.

  As shown in FIG. 7, the interpolation filters 1 to 3 include a storage device 12 that stores and holds each input digital signal, a coefficient storage device 11 that stores a coefficient to be multiplied, and an adder for pre-adding. 13. An adder 16 for multiplying data and accumulating and adding and a register 15 are provided. Here, each embodiment of the semiconductor memory device described above is used as the memory device 12.

In the interpolation filters 1 to 3 having such a configuration, as shown in the equation (2), the data X (z ^−k ) and X (z ^{− (n−k + 1} ) stored in the storage device 12 are stored. ⁾ ) Are simultaneously read, the read data pairs are added by the adder 13, the addition result is multiplied by a predetermined coefficient _h2k-1 , the addition result is cumulatively added, and the interpolation filter is used. Interpolated data Y (z) is output.

As described above, in the embodiment of the digital filter of the present invention, the area of the semiconductor circuit can be effectively reduced by using the memory device according to the embodiment of the present invention as the memory device.
In particular, in order to improve the performance of a digital filter, a method of increasing the number of taps of the digital filter is usually used, and the total number of coefficients to be handled and the number of data are increased. Become bigger.
In addition, the present invention is not limited to a ΔΣ type DA converter, but is also used for a decimation filter of a ΔΣ type AD converter when a digital filter that obtains an output by multiplying input time series data by a time symmetric coefficient is used. Can do.

1 is a diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment of the present invention. FIG. 4 is a diagram for explaining a relationship between a memory cell array and bit lines according to the first embodiment. FIG. 3 is a circuit diagram showing a specific configuration of the memory cell array according to the first embodiment. FIG. 3 is a circuit diagram showing a specific configuration of a row decoder according to the first embodiment. FIG. 6 is a circuit diagram showing a specific configuration of a row decoder according to a second embodiment of the semiconductor memory device of the present invention. It is a time chart for demonstrating operation | movement of the row decoder based on the 2nd Embodiment. 1 is a schematic configuration diagram of a ΔΣ DA converter using an embodiment of a digital filter of the present invention. It is the schematic of a digital filter when not using a pre-adding method. It is the schematic of the digital filter using the pre-adding method. It is a timing chart for demonstrating a pre-adding method. It is a schematic block diagram of the semiconductor memory device used for the digital filter of a conventional method. It is a schematic block diagram of a dual port type memory cell. It is a schematic block diagram of a single port type memory cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 12 Memory | storage device 20 Memory cell 21 Switch 31, 32 Row decoder 33 OR circuit 34 Word line 35, 36 Bit line 37, 38 Sense amplifier 41, 43 Flip-flop circuit (FF circuit)
49-52 switch 61, 62 selection circuit 63, 64 selection control circuit

Claims (5)

A memory cell array composed of a plurality of memory cells arranged in a two-dimensional matrix in the row direction and the column direction;
A group of word lines for selecting a row address of the memory cell array;
A first bit line group that is freely connectable to an odd-numbered memory cell among memory cells arranged in a column direction, and selects a column address of the memory cell array;
A second bit line group which is connectable to even-numbered memory cells among memory cells arranged in the column direction, and selects a column address of the memory cell array;
A sense amplifier group for outputting each output data on the first and second bit line groups;
Two word lines of the word line group are simultaneously selected under a predetermined condition, and data stored in a memory cell selected in accordance with the selection is transferred to the first bit line group and the second bit line. Reading means for reading simultaneously to the line group;
A semiconductor memory device comprising: The reading means includes
A first row decoder for generating and outputting a signal for selecting a predetermined one of the word line groups;
A second row decoder for generating and outputting a signal for selecting a predetermined other one of the word line groups;
A plurality of OR circuits each performing a logical OR operation of corresponding output signals output from the both row decoders,
2. The semiconductor memory device according to claim 1, wherein each output signal of the plurality of OR circuits is supplied to each word line of the word line group. Each of the first and second row decoders includes first and second shift registers,
The output of the final stage flip-flop of each shift register is fed back to the first stage flip-flop so that the data of the shift register is circulated.
3. The semiconductor memory device according to claim 2, wherein directions in which data of the first shift register and the second shift register circulate are opposite to each other. The memory cell array has a first row, a ((N / 2) +1) row, a second row, a ((N / 2) +2) row,... I row, ((N / 2) + I) The line is composed of N lines arranged in the order of ((N / 2) -1) line, (N-1) line, (N / 2) line, and N line,
Each of the first and second shift registers is configured by connecting half of N flip-flops in series,
In addition, each flip-flop of the shift register has a selection unit, and the first selection unit can select either the first row or the ((N / 2) +1) th row. The selection part can select either the second line or the ((N / 2) +2) line, and the I-th selection part is the I line and the ((N / 2) + I) line. 4. The semiconductor memory device according to claim 3, wherein any one of the above can be selected. 5. The semiconductor memory device according to claim 1, and an adding unit that adds a first output and a second output output from the semiconductor memory device;
Multiplication means for multiplying the output signal added by the addition means by a coefficient;
Cumulative addition means for cumulatively adding the multiplication results multiplied by the multiplication means;
A digital filter characterized by comprising:

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