JP2005308893A - Plasma display panel device and driving method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel device in which high light emission efficiency is stably attained and uniformity of a display image over a whole panel is attained, and to provide a driving method for the same. <P>SOLUTION: In a sustain period T<SB>3</SB>when display light emission is obtained, a first Dat electrode voltage pulse V<SB>p1</SB>of a desired period and voltage is applied to a first Dat electrode 122a in timing t11 when a Scn electrode voltage pulse V<SB>scn</SB>of the desired period and voltage which is applied to a Scn electrode 112a begins to fall from a High level to a Low level and in timing t13 to be approximately synchronized with this. A Sus electrode voltage pulse V<SB>sus</SB>of the desired voltage whose phase is different from the applied voltage pulse to the Scn electrode 112a by 180 degrees is applied to a Sus electrode 112b and an alternate voltage is applied between the electrodes 112 for displaying. The High level and the Low level setting times of a Scn electrode voltage pulse Vsc and the Sus electrode voltage pulse V<SB>sus</SB>are made same. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a plasma display panel device and a driving method thereof.

Plasma display panel devices (hereinafter referred to as “PDP devices”) include an alternating current type (AC type) and a direct current type (DC). Currently, the AC type, which is superior in terms of reliability and image quality, has become widespread. ing. Of the configuration of the AC type PDP apparatus, the configuration of the panel unit will be described with reference to FIG.
As shown in FIG. 8, the panel unit 500 of the PDP apparatus is configured such that the front panel 510 and the back panel 520 face each other with the partition wall 524 of the back panel 520 interposed therebetween, and the outer peripheral portions of the panels 510 and 520 are arranged. Has a sealed structure. And between the panels 510 and 520, the discharge space 530 partitioned by the partition 524 is filled with a discharge gas such as Ne—Xe or He—Xe.

  Of the two panels 510 and 520, the front panel 510 has a configuration in which a display electrode pair 512, a dielectric layer 513, and a protective layer 514 are sequentially stacked on the surface of the front substrate 511. The display electrode pair 512 includes a scan electrode (hereinafter referred to as “Scn electrode”) 512a and a sustain electrode (hereinafter referred to as “Sus electrode”) each having a laminated structure of transparent electrodes 512a1, 512b1 and bus electrodes 512a2, 512b2. It is described as “electrode”.) 512b.

  On the other hand, in the back panel 520, a data electrode (hereinafter referred to as “Dat electrode”) 522 and a dielectric layer 523 are sequentially laminated on the surface of the back substrate 521, and further on the surface of the dielectric layer 523. A partition wall 524 is formed between the Dat electrodes 522. In addition, red, green, and blue phosphor layers 525 are sequentially formed in each groove portion formed of the dielectric layer 523 and a pair of adjacent partition walls 524. The arrangement direction of the front panel 510 and the back panel 520 is such that the display electrode pair 512 and the Dat electrode 522 are substantially orthogonal to each other.

  In addition to the panel unit 500, the PDP device includes a drive unit (not shown) that applies a voltage to each of the electrodes 512 and 522. A so-called time-division gray scale display method is generally used for driving a PDP device. One field is divided into a plurality of subfields, and each subfield is initialized, written, maintained, etc. Consists of. Among them, the sustain period will be described with reference to FIG.

As shown in FIG. 9A, in the sustain period, the scan pulse V _SCN and the sustain pulse V _SUS are applied between the Scn electrode 512a and the Sus electrode 512b in a state where the phases are different from each other. On the other hand, in the sustain period, the Dat electrode 522 is in a state of being maintained constant at zero potential. The PDP device has a configuration in which a sustain discharge is generated by applying an alternating voltage to the display electrode pair 512 in such a sustain period, and visible light is emitted from each discharge cell selected in the write period.

By the way, the PDP device has a problem that its luminous efficiency is lower than that of a CRT device or the like that has been widely used as an image display device. Various measures have been taken for this problem. For example, Patent Document 1 discloses a method in which a call discharge is generated prior to a sustain discharge in a sustain period. In this method, as shown in FIG. 9B, in the sustain period, a pulse voltage is applied to the Dat electrode 522 prior to the occurrence of the sustain discharge, whereby a preliminary discharge as shown in FIG. Give rise to In the PDP device of this publication, the discharge start voltage between the Scn electrode 512a and the Sus electrode 512b can be reduced with a priming effect by preliminary discharge.
JP 2001-5425 A

  However, in the PDP device disclosed in Patent Document 1, the setting margin of the application timing of the pulse voltage to the Dat electrode 522 in the sustain period may be very narrow, which causes problems such as variations in light emission efficiency and display image non-uniformity. May occur. That is, in the PDP device disclosed in Patent Document 1, a pulse voltage is continuously applied to one Dat electrode 522 provided corresponding to each discharge cell during the sustain period. The timing setting margin is very narrow depending on conditions. In particular, the light emission efficiency of the panel has a characteristic that changes rapidly depending on the falling timing of the pulse voltage applied to the Dat electrode 522 in the sustain period. If there is a deviation in the application timing or speed variation, the light emission efficiency as described above. This causes problems such as variations in display and non-uniformity in the displayed image.

  In the PDP device of Patent Document 1, the application timing of the pulse voltage to the Dat electrode 522 in the sustain period is greatly influenced by the discharge gas component sealed in the discharge space 530 and the structure of the discharge cell. For this reason, in the PDP device of Patent Document 1, it is difficult to maintain the driving conditions in an optimum range in order to ensure high light emission efficiency and uniformity of display video.

  The present invention has been made to solve the above problems, and can provide a plasma display panel device capable of stably obtaining high luminous efficiency and obtaining uniformity of a display image in the entire panel, and An object is to provide a driving method thereof.

In order to achieve the above object, the present invention has the following features.
(1) having a sealed container filled with discharge gas in the discharge space, and in the sealed container, a plurality of display electrode pairs (a pair of Scn electrode and Sus electrode) are formed on one side of the discharge space; On the other hand, a plurality of Dat electrodes are formed in a direction substantially perpendicular to the display electrode pair, and a discharge cell is formed at each three-dimensional intersection between the display electrode pair and the Dat electrode. A PDP apparatus including a display unit using a display method, and a drive unit that applies a voltage between the display electrode pair and applies a voltage to the Dat electrode to perform image display drive of the panel unit in the sustain period, The plurality of Dat electrodes are divided into two groups of a first Dat electrode group and a second Dat electrode group, and the first Dat electrode and the second Dat electrode are paired with each of the discharge cells. During the maintenance period The driving unit applies a voltage to the first Dat electrode at a timing corresponding to the voltage application to one of the display electrode pairs (Scn electrode or Sus electrode), and on the other hand, to the second Dat electrode, the display electrode pair A voltage is applied at a timing according to the voltage application to the other of the two.

(2) In the PDP device according to (1), in the sustain period, a sustain discharge generated between the display electrode pair is extended toward the first Dat electrode by applying a voltage to the first Dat electrode, By applying a voltage to the second Dat electrode, the sustain discharge generated between the display electrode pairs extends toward the second Dat electrode.
(3) In the PDP device according to (1), display is performed at a timing until a sustain discharge is generated between the display electrode pair due to voltage application to the first Dat electrode in the sustain period. A preliminary discharge is generated between the electrode pair and the first Dat electrode, and a voltage is applied to the second Dat electrode, and then a sustain discharge is generated between the display electrode pair, Preliminary discharge is generated between the second Dat electrode and the second Dat electrode.

(4) In the PDP device according to any one of (1) to (3), the drive unit alternately applies a voltage to the first Dat electrode and the second Dat electrode in the sustain period. And
(5) In the PDP device according to (3) or (4), a preliminary discharge generated between the first Dat electrode and one of the display electrode pairs is defined as a first preliminary discharge, and the second Dat electrode and the display electrode When the preliminary discharge generated between the other pair of the pair is set as the second preliminary discharge, the driving unit causes the first preliminary discharge prior to the sustain discharge generated between the display electrode pair with respect to the first Dat electrode in the sustain period. A voltage is applied at a timing at which discharge occurs, and a voltage is applied to the second Dat electrode at a timing at which a second preliminary discharge occurs prior to a sustain discharge generated between the display electrode pair. To do.

  (6) In the PDP device according to any one of (1) to (5), the sealed container includes a first panel having a display electrode pair as a constituent element, a Dat electrode as a constituent element, A second panel arranged opposite to each other with a discharge space interposed therebetween is overlapped, and an outer peripheral portion thereof is hermetically sealed, and a plurality of discharge cells are arranged in a matrix in the surface direction of the first panel and the second panel. The display electrode pair is composed of an Scn electrode and a Sus electrode that are arranged in parallel. The drive unit includes an Scn driver that applies a voltage to the Scn electrode, and a voltage applied to the Sus electrode. , A first Dat driver that applies a voltage to the first Dat electrode, and a second Dat driver that applies a voltage to the second Dat electrode, and the four drivers have independent timings. It has been characterized in that it is drivable configuration.

  (7) having a sealed container filled with discharge gas in the discharge space, and in the sealed container, a plurality of display electrode pairs (a pair of Scn electrode and Sus electrode) are formed on one side of the discharge space; On the other hand, a plurality of Dat electrodes are formed in a direction substantially orthogonal to the display electrode pair, and both writing and maintaining are performed on a panel portion in which a discharge cell is formed at each three-dimensional intersection between the display electrode pair and the Dat electrode. A driving method of a PDP apparatus that uses a display method with a period, applies a voltage between a pair of display electrodes in a sustain period, and applies a voltage to a Dat electrode to perform image display driving. The electrode is divided into two groups of a first Dat electrode group and a second Dat electrode group, and the first Dat electrode and the second Dat electrode are arranged in pairs for each of the discharge cells. In the period, the first A voltage is applied to the at electrode at a timing corresponding to the voltage application to one of the display electrode pairs (Scn electrode or Sus electrode), while the second Dat electrode is applied to a voltage applied to the other of the display electrode pair. The voltage is applied at a predetermined timing.

  (8) In the driving method of the PDP device according to (7) above, the display electrode pair is composed of the Scn electrode and the Sus electrode arranged in parallel, and each of the Scn electrode and the Sus electrode is maintained in the sustain period. The applied voltage is a pulse having a binary value of a high level and a low level, and the setting time of the high level in the pulsed voltage is the same as or longer than the setting time of the low level. In the sustain period, the voltage application timing to the first Dat electrode is set according to the timing at which the voltage applied to the Scn electrode starts to fall from the high level to the low level, and the voltage applied to the Sus electrode Is applied to the second Dat electrode according to the timing at which the voltage starts to fall from the high level to the low level. Characterized in that it is a constant.

  (9) In the driving method of the PDP device according to the above (8), the rising timing of the applied voltage to the first Dat electrode in the sustain period is based on the starting timing of the falling voltage in the applied voltage to the Scn electrode. , 1.0 μsec. 0.5 μsec. From the previous time point. On the other hand, the rising timing of the applied voltage to the second Dat electrode is set to a timing at which the falling of the applied voltage to the Sus electrode starts as a reference, and is 1 with respect to the reference. 0.0 μsec. 0.5 μsec. From the previous time point. It is characterized in that it is set within a period until reaching the elapsed time.

  (10) The driving method of the PDP device according to (7) above, wherein the display electrode pair is composed of a Scn electrode and a Sus electrode arranged in parallel, and is applied to each of the display electrode pair during the sustain period The voltage to be applied is a pulse having a binary value of a high level and a low level, and when the set time of the high level in the pulsed voltage is shorter than the set time of the low level, the sustain period , The voltage application timing to the first Dat electrode is set according to the timing at which the voltage applied to the Scn electrode starts to rise from the low level to the high level, and the voltage applied to the Sus electrode is set from the low level to the high level. The timing of applying a voltage to the second Dat electrode is set according to the timing of starting to rise.

  (11) In the driving method of the PDP device according to the above (10), the rising start timing of the applied voltage to the first Dat electrode is based on the rising start timing of the applied voltage to the Scn electrode in the sustain period, 1.0 μsec. 0.5 μsec. From the previous time point. The timing at which the applied voltage to the second Dat electrode begins to rise is based on the timing at which the applied voltage to the Sus electrode begins to rise, and 1.0 μsec. 0.5 μsec. From the previous time point. It is characterized in that it is set within a period until reaching the elapsed time.

(12) In the driving method of the PDP device according to any one of (7) to (11), voltages applied to the first Dat electrode and the second Dat electrode are each in a pulse form in the sustain period. Both are set to the same period length as the period of the voltage applied to each of the display electrode pairs.
(13) In the driving method of the PDP device according to any of (8) to (12) above, the timing at which the applied voltage to each of the first Dat electrode and the second Dat electrode starts falling in the sustain period is It is set after the sustain discharge between the display electrodes is completed.

  (14) In the driving method of the PDP device according to any one of (8) to (13), the voltage applied to each of the first Dat electrode and the second Dat electrode in the sustain period has a pulse waveform. The voltage applied to the first Dat electrode and the voltage applied to the second Dat electrode are set so that the high level states of the waveforms do not overlap in time.

  In the PDP device and the driving method thereof according to the present invention, the Dat electrode is divided into two groups of the first Dat electrode group and the second Dat electrode group, and the first Dat electrode and the second Dat electrode are paired in each discharge cell. In addition, a voltage can be alternately applied to the first Dat electrode and the second Dat electrode in the sustain period. In this case, in the discharge space of each discharge cell, during the sustain period, the sustain discharge when a voltage is applied to the first Dat electrode is induced to the side where the first Dat electrode is arranged, while the voltage is applied to the second Dat electrode. The sustain discharge when the voltage is applied is induced to the side where the second Dat electrode is disposed.

  By applying a voltage to the first Dat electrode and the second Dat electrode during the sustain period, the PDP device and the driving method thereof according to the present invention can obtain high luminous efficiency. In the PDP device and the driving method thereof according to the present invention, the voltage is alternately applied to the first Dat electrode and the second Dat electrode in the sustain period. As described above, it is difficult to cause deviations in application timing, speed variations, and the like, and it is difficult to cause problems such as variations in light emission efficiency and display image non-uniformity. That is, for each of the first Dat electrode or the second Dat electrode, the voltage application interval in the sustain period can be set much longer than in the case of the driving method of the PDP device disclosed in Patent Document 1. The voltage can be applied to the Dat electrode in the sustain period at an optimal timing in consideration of the configuration of the unit.

Therefore, in the PDP device and the driving method thereof according to the present invention, it is possible to stably obtain high light emission efficiency and to obtain display image uniformity across the entire panel.
Note that, as described in the above (2) and (3), in the present invention, by applying a voltage to the first Dat electrode and the second Dat electrode during the sustain period, the sustain discharge is preceded between the Dat electrode and the display electrode pair. The above advantages can be obtained regardless of whether or not the preliminary discharge is performed. That is, even if the preliminary discharge is not generated by the voltage application n to the first Dat electrode and the second Dat electrode, it is possible to affect the electric field state in the discharge space, and the sustain discharge is applied to the voltage. It can be generated in a state of extending toward the Dat electrode on the implemented side.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, about embodiment described below, it uses as an example for demonstrating the characteristic in a structure and an effect | action of this invention, This invention is not limited to this.
(Embodiment 1)
1. Configuration of Panel Unit 10 The configuration of the panel unit 10 of the PDP apparatus 1 according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a perspective view showing the structure of the panel unit 10 according to the first embodiment. Compared with the conventional panel unit 500 shown in FIG. The data electrode (hereinafter referred to as “first Dat electrode”) 122a and the second data electrode (hereinafter referred to as “second Dat electrode”) 122b are arranged in parallel in a pair. It is different, but the others are similar.

1-1. Configuration of Front Panel 11 The front panel 11 has a scan electrode (hereinafter referred to as “Scn electrode”) 112a and a sustain electrode on a surface (a lower surface in FIG. 1) of the front substrate 111 facing the rear panel 12. (Hereinafter referred to as “Sus electrodes”.) A plurality of pairs of display electrodes 112 made of 112b are arranged in parallel to each other, and the dielectric layer 113 and the protective layer 114 are sequentially arranged so as to cover the display electrode pairs 112. A coating is formed.

Each of the Scn electrode 112a and the Sus electrode 112b is made of wide transparent electrodes 112a1 and 112b1 made of ITO (tin-doped indium oxide), SnO ₂ , ZnO, etc., and Cr—Cu—Cr or Ag for reducing electric resistance. The formed bus electrodes 112a2 and 112b2 are respectively combined. The paired Scn electrode 112a and Sus electrode 112b are arranged side by side with a gap d (for example, 80 μm) therebetween.

The dielectric layer 113 is made of a low melting point glass material, and the protective layer 114 is made of magnesium oxide (MgO).
1-2. Configuration of the Back Panel 12 The back panel 12 has a first Dat electrode 122a and a second Dat in a direction substantially orthogonal to the display electrode pair 112 on the surface of the back substrate 121 facing the front panel 11 (upper surface in FIG. 1). A plurality of data electrode pairs (hereinafter referred to as “Dat electrode pairs”) 122 configured with the electrodes 122 b are arranged, and a dielectric layer 123 is formed so as to cover the Dat electrode pairs 122. ing. Further, a partition wall 124 is provided between the adjacent Dat electrode pair 122 on the dielectric layer 123, and the Dat electrode pair is formed on the inner wall surface of the groove formed by the partition wall 124 adjacent to the dielectric layer 123. A phosphor layer 125 is provided in a direction along 122.

Each of the Dat electrodes 122a and 122b constituting the Dat electrode pair 122 is formed of a metal material such as silver (Ag), for example. In addition to Ag, the forming material may be a metal material such as gold (Au), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), or a combination thereof. You can also.
The dielectric layer 123 is basically formed of a low-melting glass material, similar to the dielectric layer 113 of the front panel 11, but may include titanium oxide (TiO ₂ ). The partition wall 124 is formed using, for example, a lead glass material.

The phosphor layer 125 is composed of three colors of red (R), green (G), and blue (B). For example, the following phosphors are used, and R, G, B in order of each groove. It is formed repeatedly.
R phosphor; (Y, Gd) BO ₃ : Eu
G phosphor; Zn ₂ SiO ₄ : Mn
B phosphor; BaMg ₂ Al ₁₄ O ₂₄ : Eu
1-3. Arrangement of Front Panel 11 and Rear Panel 12 The panel unit 10 includes a front panel 11 and a rear panel 12 sandwiching a partition wall 124 formed on the rear panel 12 as a gap material, and a display electrode pair 112 and a Dat. The electrode pair 122 is arranged in a substantially perpendicular direction, and the outer peripheral portions of the panels 11 and 12 are sealed in this state. As a result, a discharge space 13 partitioned by each partition 124 is formed between the front panel 11 and the back panel 12, and the discharge space 13 is filled with a discharge gas in which Ne, Xe, He, or the like is mixed. Is configured. The sealed pressure of the discharge gas is, for example, about 50 to 80 (kPa).

In the panel unit 10, discharge cells (not shown) are formed at locations where the display electrode pair 112 and the Dat electrode pair 122 are three-dimensionally crossed. The panel unit 10 has a plurality of discharge cells arranged in a matrix.
2. Overall Configuration of PDP Device 1 Next, the overall configuration of the PDP device 1 including the panel unit 10 will be described with reference to FIG. FIG. 2 is a block diagram showing the overall configuration of the PDP display device 1. In FIG. 2, the power supply path and the like are omitted.

As shown in FIG. 2, the PDP apparatus 1 according to the present embodiment includes the above-described panel unit 10 and a drive circuit unit 20 that drives the image display. Here, the drive circuit unit 20 controls the gradation of the panel unit 10 by the time-division gradation display method in the field and drives the image display.
The display driver 20 includes a preprocessor 21, a frame memory 22, a synchronization pulse / timing generator 23, a sustain data pulse / timing generator 28, a scan driver (hereinafter referred to as “Scn driver”) 24, and a sustain driver. (Hereinafter referred to as “Sus driver”), a first data driver (hereinafter referred to as “first Dat driver”) 26, a second data driver (hereinafter referred to as “second Dat driver”). .) 27.

  Among these, the preprocessor 21 extracts video data (field data) for each field from the video data input to the device 1, and creates video data (subfield data) for each subfield from the extracted field data. . The preprocessor 21 stores the created subfield data in the frame memory 22. The preprocessor 21 outputs data from the current subfield data stored in the frame memory 22 to each of the first Dat driver 26 and the second Dat driver 27 one line at a time. A synchronization signal such as a synchronization signal is detected, and a timing signal is transmitted to the synchronization pulse / timing generator 23 for each field and each subfield.

  The frame memory 22 is a two-port frame memory having two memory areas (for example, storing eight subfield data) for each field, and while writing the subfield data in one memory area, The operation of reading out the subfield data written here from the other memory area can be executed alternately.

  The synchronization pulse / timing generation unit 23 refers to the timing signal sent from the preprocessor 21, generates a timing signal for raising the initialization pulse, the scan pulse, and the sustain pulse, and each driver 24, 25, 26, 27. Send to. The synchronization pulse / timing generator 23 transmits a timing signal to the sustain data pulse / timing generator 28 that generates a pulse application timing signal to each of the first Dat driver 26 and the second Dat driver 27 during the sustain period. .

The Scn driver 24 is configured by a drive circuit including a known driver IC, generates an initialization pulse and a scan pulse in accordance with a timing signal sent from the synchronization pulse / timing generation unit 23, and a panel unit. 10 to each of the Scn electrodes 112a.
The Sus driver 25 is configured by a drive circuit including a known driver IC, generates an initialization pulse and a sustain pulse according to the timing signal sent from the synchronization pulse / timing signal generation unit 23, and the panel unit 10. Is applied to each of the Sus electrodes 112b.

  The first Dat driver 26 and the second Dat driver 27 are configured by a drive circuit including a known driver IC, and are connected to the first Dat electrode 122a and the second Dat electrode 122b of the panel unit 10, respectively. Each of these drivers 26 and 27 selectively writes a write pulse from a plurality of Dat electrode pairs 122 in the write period based on the subfield data from the preprocessor 21 and the timing signal from the synchronization pulse / timing generator 23. Apply. In addition, the first Dat driver 26 and the second Dat driver 27 are connected to the first Dat electrode 122a and the second Dat electrode 122b for each built-in drive circuit based on the timing signal from the sustain data pulse / timing generation unit 28 in the sustain period. A pulse (hereinafter referred to as “sustain Dat pulse”) is applied to each of them. A control method related to this application will be described later.

3. 3. Driving method of PDP device 1 3-1. Overall Driving Method Next, a driving method of the PDP device 1 will be described with reference to FIG. FIG. 3 shows a method of dividing one field into eight subfields SF1 to SF8 in order to express, for example, 256 gradations using an intra-field time division gradation display method. The hatched area indicates the writing period.

  As shown in FIG. 3, in the driving method of PDP device 1 according to the present embodiment, one field is divided into eight subfields SF1 to SF8, and the relative luminance ratio of each subfield is 1: 2: 4: 8. The number of sustain pulses is set to be 16: 32: 64: 128. By controlling lighting / non-lighting of each of the subfields SF1 to SF8 according to display luminance data, 256 gradations can be displayed with a combination of eight subfields. In this embodiment, control is performed with 256 gradations, but the present invention is not limited to this.

Each subfield includes an initialization period T ₁ to which a certain time is allocated, a writing period T _2, and a sustain period T ₃ set with a length of time corresponding to the relative ratio of luminance. For example, when the display drive of the panel unit 10 according to the present embodiment is performed, first, an initialization discharge is generated in all the discharge cells of the panel unit 10 in the initialization period T ₁ , thereby causing the subframe to Also, initialization for removing the influence of the discharge performed in the previous subframe and absorbing the variation in the discharge characteristics is performed.

Then, in the write period T _2, Scn electrodes 112a (1) on the basis of the subfield data ~112a (k) the continue to scan sequentially for each line, the discharge cell to cause a sustain discharge in the subfield , A slight discharge is generated between the Scn electrode 112a and the Dat electrode pair 122. As described above, in the discharge cell in which a slight discharge is generated between the Scn electrode 112 a and the Dat electrode pair 122, wall charges are stored on the surface of the protective layer 114 of the front panel 11. In the writing period T ₂ , it is not always necessary to apply a voltage pulse to both the first Dat electrode 122a and the second Dat electrode 122b constituting the Dat electrode pair 122, and it may be applied to either one of them. Good.

Thereafter, in the sustain period T ₃ , sustain pulses 300 and 310 of rectangular waves are applied to the Sus electrode 112b and the Scn electrode 112a at a predetermined cycle (for example, 6 μsec.) And a predetermined voltage (for example, 180 V). The sustain pulse 300 applied to the Sus electrode 112b and the sustain pulse 310 applied to the Scn electrode 112a have the same period and are out of phase by a half period. It is simultaneously applied to the discharge cells.

Further, as shown in FIG. 3, the PDP apparatus 1 according to this embodiment, in the sustain period T _3, with respect to the 1Dat electrode 122a and the 2Dat electrode 122b of the rectangular pulse (sustain Dat pulse) 320, 330 is applied.
3-2. Next, with regard to the application of the sustain Dat pulses 320 and 330, the drive mode in the sustain period T _3, which is a characteristic part of the first embodiment, will be described with reference to FIGS. 4 and 5. To do. FIG. 5 is a conceptual diagram showing a discharge process in a discharge cell which is a discharge display unit of the PDP device 1 of the first embodiment.

As shown in FIG. 4, in the sustain period T ₃ to obtain a display emission, Scn electrode voltage pulse V _scn applied to the Scn electrodes 122a (1) ~ (k) is the timing t11 to start falling from High level to Low level The first Dat electrode voltage pulse V _p1 having a required period (for example, 6 μsec.) And a required voltage (for example, about 70 V) is applied to the first Dat electrode 122a at a timing t13 substantially synchronized with this. A Sus electrode voltage pulse Vsus having a required voltage (for example, about 180 V) that is 180 degrees out of phase with the applied voltage pulse to the Scn electrode 112a is applied to the Sus electrode 112b, and an AC voltage is applied between the display electrodes 112. To do. Thereby, a light emission waveform is observed from timing t15 when the potential difference between the Scn electrode 112a and the Sus electrode 112b exceeds the discharge start voltage. In the present embodiment, the setting times of the high level and the low level of the Scn electrode voltage pulse V _scn and the Sus electrode voltage pulse V _sus are the same.

  As shown in FIG. 5A, the sustain discharge generated between the display electrode pair 112 is driven between the first Dat electrode 122a and the Scn electrode 112a and the Sus electrode 112b by the driving by the method shown in FIG. The line is affected by the potential of the first Dat electrode 122a, and the first sustain discharge induced on the first Dat electrode 122a side (the left side in FIG. 5A) of the back panel 13 is generated.

The first Dat electrode voltage pulse and the second Dat electrode voltage pulse described below are applied in the same cycle as the Scn electrode voltage pulse and the Sus electrode voltage pulse, respectively. Further, in the sustain period T ₃ , the first Dat electrode voltage pulse V _p1 and the second Dat electrode voltage pulse V _p2 applied to the first Dat electrode 122a and the second Dat electrode 122b respectively do not maintain the High level period at the same time. It is desirable to do so.

Further, the first Dat electrode voltage pulse V _p1 applied to the first Dat electrode 112a falls at a timing after the first sustain discharge is completed.
Next, as shown in FIG. 4, the Sus electrode voltage pulse Vsus having the required period (for example, 6 μsec.) And the required voltage (for example, about 180 V) applied to the Sus electrode 112b starts to fall from the High level to the Low level. At a timing t14 substantially synchronized with the timing t12, a second Dat electrode voltage pulse V _p2 having a required period (for example, 6 μsec.) And a required voltage (for example, about 70 V) is applied to the second Dat electrode 122b. In the same manner as described above, the emission waveform is observed from timing t16 when the potential difference between the Scn electrode 112a and the Sus electrode 112b exceeds the discharge start voltage.

  Further, as shown in FIG. 5B, the sustain discharge generated between the display electrode pair 112 is caused by the lines of electric force between the second Dat electrode 122b and the Scn electrode 112a and the Sus electrode 112b. Under the influence of the potential, the second sustain discharge induced on the second Dat electrode 122b side (right side in FIG. 5B) of the back panel 13 is generated.

Similarly to the first Dat electrode voltage pulse V _p1 applied to the first Dat electrode 122a, the second Dat electrode voltage pulse V _p2 applied to the second Dat electrode 122b is a timing after the second sustain discharge is completed. Fall down.
4). Advantages of PDP Device 1 As described above, in the PDP device 1 according to the present embodiment, by adopting the above-described configuration and driving method, at least two pairs that form a pair in the sustain period T ₃ in which display light emission is obtained. The sustain Dat pulses V _p1 and V _p2 are alternately applied to the Dat electrodes 122a and 122b to drive the sustain discharge generated between the Scn electrode 112a and the Sus electrode 112b to the Dat electrodes 122a and 122b side of the rear panel 12. It can be generated in the state of being extended alternately. As a result, in the PDP device 1, the discharge path of the sustain discharge becomes longer than in the conventional case, and the discharge approaches the phosphor layer 125 formed on the back panel 12. Therefore, the positive column region at the time of sustain discharge generation can be increased, and the ultraviolet ray generation efficiency can be increased, and at the same time, the ultraviolet ray transmission efficiency can be improved.

Further, by alternately applying the Dat electrode voltage pulses V _p1 and V _p2 to the paired first and second Dat electrodes 122a and 122b, the period until the next sustain discharge corresponding to each Dat electrode 122a and 122b is lengthened. Become. For this reason, the falling timing of the Dat electrode voltage pulse is less severe in the PDP device 1 than in the conventional PDP device. Therefore, the setting margin of the application timing of the Dat electrode voltage pulses V _p1 and V _p2 for improving the light emission efficiency can be widened, and the light emission efficiency can be improved uniformly in all the discharge cells. Furthermore, the slope of the voltage waveforms of the Dat electrode voltage pulses V _p1 and V _p2 can be set gently, and the reactive power recovery efficiency can be improved.

In addition, the Dat electrode voltage pulses V _p1 and V _p2 of the Dat electrodes 122a and 122b are lowered at the timing after the sustain discharge is completed, so that a stable light emission state can be obtained compared to the conventional case. Can keep.
According to an experiment conducted by the present inventors to confirm the above-described superiority, at least two Dat electrodes 122a and 122b of each discharge cell are provided so as to form a pair to obtain display light emission. In the sustain period T ₃ , a sustain discharge having a long discharge path alternately between the two Dat electrodes 122a and 122b forming a pair facing the Scn electrode 112a and the Sus electrode 112b (first sustain discharge, second sustain discharge) With the configuration in which the sustain discharge is generated, the luminous efficiency can be improved by 30% compared to the PDP device 500 of Patent Document 1 that is driven by the method of FIG. 9B.

Further, the same effect as described above can be obtained even if preliminary discharge occurs between the front panel 11 and the back panel 12 by applying the voltage pulses V _p1 and V _p2 to the first Dat electrode 122a and the second Dat electrode 122b. Can be obtained.
5). That in this embodiment the application timing of the Dat electrode voltage pulse V _p1, V _p2, but it was decided to apply a Dat electrode voltage pulse V _p1, V _p2 with the timing shown in FIG. 4, increase the luminous efficiency From the viewpoint, it is desirable to set the timings t13 and t14 according to the following conditions.

5-1. When the set time of the High level in each of the Scn electrode voltage pulse V _scn and the Sus electrode voltage pulse V _sus is set to be equal to or longer than the set time of the Low level In this case, the Scn electrode voltage pulse V _The timing at which the _scn pulse waveform starts to fall from the High level to the Low level (timing t11) is used as a reference, and the timing at which the first Dat electrode voltage pulse V _p1 starts to rise (timing t13) is set based on this reference. the pulse waveform of Sus electrode voltage pulse V _sus is the basis of the timing to start falling from the High level to the Low level (timing t12), the rise start timing (timing of the 2Dat electrode voltage pulse V _p2 based on the reference t14 Hope to set) .

More specifically, for example, the rising start timing (timing t13) of the first Dat electrode voltage pulse V _p1 is set to 1.0 μsec. 0.5 μsec. From the previous time point. It is desirable to set it within a period up to the point of time, and the timing at which the second Dat electrode voltage pulse V _p2 starts to rise (timing t14) is set to 1.0 μsec. 0.5 μsec. From the previous time point. It is desirable to set within the period up to the point of time.

5-2. When the set time of the High level in each of the Scn electrode voltage pulse V _scn and the Sus electrode voltage pulse V _sus is set shorter than the set time of the Low level In this case, the pulse waveform of the Scn electrode voltage pulse V _scn Is based on the timing at which the first starts to rise from the Low level to the High level, and the timing at which the first Dat electrode voltage pulse V _p1 starts to rise (timing t13) is set based on this reference, while the pulse of the Sus electrode voltage pulse V _sus The timing at which the waveform starts to rise from the Low level to the High level is used as a reference, and it is desirable to set the timing at which the second Dat electrode voltage pulse V _p2 starts to rise (timing t14) based on this reference.

More specifically, for example, the timing at which the first Dat electrode voltage pulse V _p1 starts to rise (timing t13) is based on the timing at which the pulse waveform of the Scn electrode voltage pulse V _scn starts to rise from the low level to the high level. 1.0 μsec. 0.5 μsec. From the previous time point. It is desirable to set the period until elapsed time, also, the rising start timing of the 2Dat electrode voltage pulse V _p2 (timing t14), pulse waveform Sus electrode voltage pulse V _sus from Low level to High level With respect to this reference, 1.0 μsec. 0.5 μsec. From the previous time point. It is desirable to set within the period up to the point of time.

5-3. And the 1Dat electrode voltage pulse V _p1 relationship between the 1Dat electrode voltage pulse V _p1 and the 2Dat electrode voltage pulse V _p2 is a second 2Dat electrode voltage pulse V _p2, as shown in FIG. 4, the Scn electrode voltage pulse V _scn It is desirable to set the period to the same length as the period of the pulse waveform and the period of the pulse waveform of the Sus electrode voltage pulse _Vsus .
Also, it is desirable that the first Dat electrode voltage pulse V _p1 and the second Dat electrode voltage pulse V _p2 are set so that their high level states do not overlap with each other as shown in FIG.
(Embodiment 2)
A PDP apparatus 2 according to Embodiment 2 of the present invention will be described with reference to the drawings. The PDP device 2 according to the present embodiment has no structural difference from the PDP device 1 according to the first embodiment except that the gap d in FIG. 1 is 200 (μm). . Hereinafter, the driving method, in particular a driving method during the sustain period T _3, will be described with reference to FIGS.

As shown in FIG. 6, in driving the PDP device 2, a Scn electrode having a required period (for example, 6 μsec.) And a required voltage (for example, about 270 V) applied to the Scn electrode 112 a in the sustain period T ₃ for obtaining display light emission. A first Dat electrode voltage having a required period (for example, 6 μsec.) And a required voltage (for example, about 70 V) is applied to the first Dat electrode 122a at a timing t23 preceding the timing t21 at which the voltage pulse V _scn starts rising from the Low level to the Hghi level. A pulse V _p1 is applied to generate a first preliminary discharge between the first Dat electrode 122a and the Sus electrode 112b as shown in FIG.

Next, by applying a Scn electrode voltage pulse V _scn to the Scn electrode 112a, a sustain discharge for display light emission is generated between the Scn electrode 112a and the Sus electrode 112b as shown in FIG. 7B.
Subsequently, as shown in FIG. 6, the required cycle applied to the Sus electrodes 112b (e.g., 6μsec.), The required voltage (e.g., about 270 V) timing Sus electrode voltage pulse V _sus of starts rising from Low level to High level At timing t24 preceding t22, a second Dat electrode voltage pulse V _p2 having a required period (for example, 6 μsec.) and a required voltage (for example, about 70 V) is applied to the second Dat electrode 122b, as shown in FIG. In addition, a second preliminary discharge is generated between the second Dat electrode 122b and the Scn electrode 112a.

Next, by applying a Sus electrode voltage pulse _Vsus to the Sus electrode 112b, as shown in FIG. 7D, a sustain discharge for display light emission is generated between the Scn electrode 112a and the Sus electrode 112b. Then, preliminary discharge and sustain discharge are repeatedly generated alternately.
Further, in the sustain period T ₃ , the first Dat electrode voltage pulse V _p1 and the second Dat electrode voltage pulse V _p2 applied to the first Dat electrode 122a and the second Dat electrode 122b, respectively, are subjected to the sustain discharge between the Scn electrode 112a and the Sus electrode 112b. It is desirable to change the high level to the low level and to fall at the timing after the end of the process. Thereby, the stable light emission state can be maintained.

In the sustain period T ₃ , the first Dat electrode voltage pulse V _p1 and the second Dat electrode voltage pulse V _p2 applied to the first Dat electrode 122a and the second Dat electrode 122b, respectively, do not maintain the High level period at the same time. It is desirable.
As described above, in the PDP apparatus 2 according to the present embodiment, by employing the driving method, in the sustain period T ₃ to obtain a display emission, prior to sustain discharge, and Scn electrodes 112a and Sus electrodes 112b By generating a preliminary discharge between a plurality of opposing Dat electrodes 122, the discharge start voltage and the sustain discharge voltage between the Scn electrode 112a and the Sus electrode 112b of the discharge cell are reduced by a priming effect by the preliminary discharge. Can do.

Further, by alternately applying the Dat electrode voltage pulses V _p1 and V _p2 to at least the two Dat electrodes 122a and 122b that make a pair, the period until the next sustain discharge corresponding to each Dat electrode 122a and 122b is increased. _Therefore , the falling timing of the Dat electrode voltage pulses V _p1 and V _p2 is not stricter than that of the conventional PDP device. Therefore, the setting margin of the application timing of the Dat electrode voltage pulses V _p1 and V _p2 that maximizes the light emission efficiency can be widened. For this reason, in the PDP device 2, the light emission efficiency can be improved uniformly in all the discharge cells. Furthermore, the slope of the voltage waveforms of the Dat electrode voltage pulses V _p1 and V _p2 can be set gently, and the reactive power recovery efficiency can be improved.

In addition, by reducing the falling time of the data electrode voltage pulse of each data electrode to the time after the end of each sustain discharge, a stable light emission state can be maintained as compared with the conventional case.
According to an experiment conducted by the present inventors to confirm the above-described superiority, at least two Dat electrodes 122a and 122b of each discharge cell are provided so as to form a pair to obtain display light emission. in the sustain period T _3, prior to the sustain discharge, Scn electrodes 112a and Sus electrode 112b opposed to two Dat electrodes 122a, between 122b, by configuring such preliminary discharge is alternately generated, Luminous efficiency could be improved by 20% compared to the conventional method in which preliminary discharge is caused between one Dat electrode 122 facing the Scn electrode 112a and the Sus electrode 112b.
(Other matters)
The configurations and driving methods of the first embodiment and the second embodiment can be changed as appropriate. For example, changes can be made as follows.

  (1) In the first and second embodiments, the Dat electrode pair 122 is configured by the first Dat electrode 122a and the second Dat 122b in each discharge cell. However, three or more Dat electrodes are arranged in each discharge cell. It doesn't matter if you do. At this time, the arrangement of the plurality of Dat electrodes in the discharge cell may or may not be parallel to each other. Further, when the number of Dat electrodes per discharge cell is three or more, they may be arranged together like the first Dat electrode group and the second Dat electrode group, which are alternately arranged. They may be arranged in the form of comb electrodes in common. Further, the shape of the plurality of Dat electrodes may be a rod shape, an uneven shape, or a shape fitted to each other.

(2) In the first and second embodiments, the Scn electrode voltage pulse V _scn and the sustain electrode voltage pulse V _sus are set to voltages having the same set time for the High level and the Low level as shown in FIG. Although the pulse is used, the present invention can be similarly implemented even in the case of a voltage pulse having a high level set time longer than the low level or a voltage pulse having a high level set time shorter than the low level.

(3) In the first and second embodiments, the first Dat electrode voltage pulse V _p1 and the second Dat electrode voltage pulse V _p2 applied to the first Dat electrode 122a and the second Dat electrode 122b, respectively, are converted into the Scn electrode voltage pulse V _scn. And the Sus electrode voltage pulse _Vsus is applied at a timing that is substantially synchronized with the timing at which the Sus electrode voltage pulse _Vsus starts to fall. However, depending on the setting width of the high level and low level periods of the Scn electrode voltage pulse _Vscn and the Sus electrode voltage pulse _Vsus . Needless to say, the optimum application timing of the Dat electrode voltage pulses V _p1 and V _p2 can be appropriately changed.

(4) In the first and second embodiments described above, the voltage values of the Scn electrode voltage pulse V _scn , the Sus electrode voltage pulse V _sus , and the Dat electrode voltage pulses V _p1 , V _p2 , their period, or duty ratio are specified as an example However, any numerical value within the scope of the gist of the present invention is not limited thereto.
(5) In the first and second embodiments, the voltage values at the low level of the Scn electrode voltage pulse V _scn , the Sus electrode voltage pulse V _sus , and the Dat electrode voltage pulses V _p1 and V _p2 are set to zero potential as an example. A DC bias may be superimposed if necessary.

(6) In the first and second embodiments, the pulse time widths at which the Dat electrode voltage pulses V _p1 and V _p2 applied to the first Dat electrode 122a and the second Dat electrode 122b are at the high level are the same. When the discharge cells are formed in an asymmetric shape, the voltage pulse widths of the Dat electrode voltage pulses V _p1 and V _p2 may be different from each other.
(7) In the first and second embodiments, the application timing of the first Dat electrode voltage pulse V _p1 is controlled according to the application timing of the Scn electrode voltage pulse V _scn , and the application timing of the Sus electrode voltage pulse V _sus The application timing of the second Dat electrode voltage pulse V _p2 is controlled according to the above, but the association is not limited to this. For example, the application timing of the first Dat electrode voltage pulse V _p1 is controlled according to the application timing of the Sus electrode voltage pulse V _{sus, and} the application timing of the second Dat electrode voltage pulse V _p2 is controlled according to the application timing of the Scn electrode voltage pulse V _scn. May be controlled. Even in such a case, the same effect as in the first and second embodiments can be obtained.

(8) In the first and second embodiments, as shown in FIG. 2, it is assumed that data is written to the write period T ₂ in both the first 1Dat electrode 122a and the 2Dat electrode 122b, the 1Dat electrode Data may be written only to either the 122a or the second Dat electrode 122b. However, when this manner to write data using one of the Dat electrodes (122a or 122b) in the write period T ₂ are, although it is superior in terms of manufacturing cost of the drive unit, improving the luminous efficiency of the panel In order to obtain the above effects, it is desirable to write data to both Dat electrodes 122a and 122b during the writing period T2 as in the _first and _second embodiments.

  INDUSTRIAL APPLICABILITY The present invention is effective in realizing a PDP device used in the video equipment industry, advertising equipment industry, industrial equipment and other industrial fields such as a large television, a high-definition television, or a large display device.

It is a principal part perspective view which shows the panel part 10 of the plasma display panel apparatus 1 which concerns on Embodiment 1 of this invention. It is a block diagram which shows the plasma display panel apparatus 1 which concerns on Embodiment 1 of this invention. FIG. 4 is a timing chart showing pulse application timings for each electrode in driving the plasma display panel device 1. In the plasma display panel device 1 is a timing diagram illustrating the application timing of the pulse with respect to each electrode in the sustain period T _3. It is a conceptual diagram showing a discharge process of the sustain discharge period T ₃ in the plasma display panel device 1. In the plasma display panel apparatus 2 according to the second embodiment of the present invention, in the sustain period T ₃ is a timing diagram illustrating the application timing of pulses of the respective electrodes. In the plasma display panel apparatus 2, in the sustain period T ₃ is a timing diagram illustrating the application timing of pulses of the respective electrodes. It is a principal part perspective view which shows the panel part 500 of the conventional plasma display panel apparatus. FIG. 10 is a timing chart showing pulse application timings for each electrode in a sustain period in driving of a conventional plasma display panel device. It is a conceptual diagram which shows the generation | occurrence | production form of the preliminary discharge in the sustain period in the conventional plasma display panel apparatus.

Explanation of symbols

1. Plasma display panel device 10. Panel section 11. Front panel 12. Rear panel 13. Discharge space 20. Drive circuit section 28. Maintenance data pulse / timing generator 112a. Scan electrode 112b. Sustain electrodes 113, 123. Dielectric layer 114. Protective layer 122a. First data electrode 122b. Second data electrode 125. Phosphor layer

Claims (14)

A discharge container filled with a discharge gas, the display container having a plurality of display electrode pairs formed on one side of the discharge space and the other in a direction substantially perpendicular to the display electrode pairs; A display unit having a plurality of data electrodes and a display unit having a discharge cell at each three-dimensional intersection of the display electrode pair and the data electrode, and a writing and sustain period, and the sustain period A plasma display panel device comprising: a driving unit that applies a voltage between the display electrode pair and applies a voltage to the data electrode to perform image display driving of the panel unit;
The plurality of data electrodes are divided into two groups of a first data electrode group and a second data electrode group, and the first data electrode group and the first data electrode are provided for each of the discharge cells. 2 data electrode groups are arranged in pairs,
In the sustain period, the driving unit
A voltage is applied to the first data electrode at a timing according to voltage application to one of the display electrode pairs,
A voltage is applied to the second data electrode at a timing according to voltage application to the other of the display electrode pair. In the sustain period, due to voltage application to the first data electrode, a sustain discharge between the display electrode pair is generated in a state of being extended toward the first data electrode,
The plasma according to claim 1, wherein a sustain discharge between the pair of display electrodes is generated in a state of being extended toward the second data electrode by applying a voltage to the second data electrode. Display panel device. Between the display electrode pair and the first data electrode at a timing until a sustain discharge is subsequently generated between the display electrode pair due to voltage application to the first data electrode in the sustain period. A preliminary discharge occurs,
By applying a voltage to the second data electrode, a preliminary discharge is generated between the display electrode pair and the second data electrode at a timing until a sustain discharge is subsequently generated between the display electrode pair. The plasma display panel device according to claim 1, wherein: 4. The plasma display panel device according to claim 1, wherein, in the sustain period, the driving unit alternately applies a voltage to the first data electrode and the second data electrode. 5. A preliminary discharge generated between the first data electrode and one of the display electrode pairs is referred to as a first preliminary discharge, and a preliminary discharge generated between the second data electrode and the other of the display electrode pair is a second preliminary discharge. And when
In the sustain period, the driving unit
A voltage is applied to the first data electrode at a timing at which the first preliminary discharge occurs prior to the sustain discharge generated between the display electrode pair,
5. The voltage according to claim 3, wherein a voltage is applied to the second data electrode at a timing at which the second preliminary discharge occurs prior to a sustain discharge generated between the display electrode pair. Plasma display panel device. The sealed container includes a first panel having the display electrode pair as a constituent element and a second panel having the data electrode as a constituent element and the first panel and a second panel disposed opposite to each other with a discharge space interposed therebetween, The outer peripheral portion is hermetically sealed, and the plurality of discharge cells are arranged in a matrix in the surface direction of the first panel and the second panel,
The display electrode pair is composed of a scan electrode and a sustain electrode arranged in parallel,
The driving unit includes a scan driver that applies a voltage to the scan electrode, a sustain driver that applies a voltage to the sustain electrode, a first data driver that applies a voltage to the first data electrode, and the second data. A second data driver for applying a voltage to the electrodes,
The plasma display panel device according to any one of claims 1 to 5, wherein the four drivers are configured to be driven at timings independent of each other. A discharge container filled with a discharge gas, the display container having a plurality of display electrode pairs formed on one side of the discharge space and the other in a direction substantially perpendicular to the display electrode pairs; For a panel portion in which a plurality of data electrodes are formed and a discharge cell is formed at each three-dimensional intersection between the display electrode pair and the data electrode, a display method having both writing and sustaining periods is used. In the sustain period, a method for driving a plasma display panel device that applies a voltage between the display electrode pair and applies a voltage to the data electrode to perform image display driving,
The plurality of data electrodes are divided into two groups of a first data electrode group and a second data electrode group, and the first data electrode and the second data for each of the discharge cells. The electrode and the pair are arranged,
In the maintenance period,
A voltage is applied to the first data electrode at a timing according to voltage application to one of the display electrode pair,
A voltage is applied to the second data electrode at a timing according to voltage application to the other of the display electrode pair. A driving method of a plasma display panel device, wherein: The display electrode pair is composed of a scan electrode and a sustain electrode arranged in parallel, and a voltage applied to each of the display electrode pair during the sustain period is a binary value of a high level and a low level. Having a pulse shape,
When the set time of the high level in the pulse voltage is the same as or longer than the set time of the low level,
In the maintenance period,
The application timing of the voltage to the first data electrode is set according to the timing at which the voltage applied to the scan electrode starts to fall from the high level to the low level, and the voltage applied to the sustain electrode is 8. The method of driving a plasma display panel device according to claim 7, wherein the application timing of the voltage to the second data electrode is set in accordance with the timing at which the falling starts from the high level to the low level. In the maintenance period,
The timing at which the applied voltage to the first data electrode starts to rise is based on the timing at which the applied voltage to the scan electrode starts to fall, and 1.0 μsec. 0.5 μsec. From the previous time point. It is set within the period until the elapsed time,
The timing at which the voltage applied to the second data electrode begins to rise is based on the timing at which the voltage applied to the sustain electrode starts to fall, and 1.0 μsec. 0.5 μsec. From the previous time point. The driving method of the plasma display panel device according to claim 8, wherein the driving time is set within a period until reaching an elapsed time point. The display electrode pair is composed of a scan electrode and a sustain electrode arranged in parallel, and a voltage applied to each of the display electrode pair during the sustain period is a binary value of a high level and a low level. Having a pulse shape,
When the set time of the high level in the pulse voltage is shorter than the set time of the low level,
In the maintenance period,
The application timing of the voltage to the first data electrode is set according to the timing at which the voltage applied to the scan electrode starts to rise from the low level to the high level, and the voltage applied to the sustain electrode is set to the low level. 8. The method of driving a plasma display panel device according to claim 7, wherein a timing for applying a voltage to the second data electrode is set in accordance with a timing at which rising starts from a level to a high level. In the maintenance period,
The timing at which the voltage applied to the first data electrode starts to rise is based on the timing at which the voltage applied to the scan electrode starts to rise, and 1.0 μsec. 0.5 μsec. From the previous time point. It is set within the period until the elapsed time,
The timing at which the voltage applied to the second data electrode starts to rise is based on the timing at which the voltage applied to the sustain electrode starts to rise, and 1.0 μsec. 0.5 μsec. From the previous time point. The method for driving a plasma display panel device according to claim 10, wherein the method is set within a period until reaching an elapsed time point. In the sustain period, the voltages applied to the first data electrode and the second data electrode are each pulsed, and both have the same period length as the period of the voltage applied to each of the display electrode pairs. The method for driving a plasma display panel device according to any one of claims 7 to 11, wherein In the maintenance period,
13. The timing at which the voltage applied to each of the first data electrode and the second data electrode starts to fall is set after the sustain discharge between the display electrodes is completed. A driving method of a plasma display panel device according to any one of the above. The voltage applied to each of the first data electrode and the second data electrode during the sustain period has a pulse waveform,
14. The voltage applied to the first data electrode and the voltage applied to the second data electrode are set so that the high level states of the waveforms do not overlap in time. A driving method of a plasma display panel device according to any one of the above.

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