JP2005303777A - Method for improving precision in clock reproduction and clock regenerator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain clock stability required for synchronous multiplexing transmission as a clock for a transmission device using an Ethernet interface for transmitting and receiving data to and from the Ethernet (R). <P>SOLUTION: An Ether frame including data having preset lengths from a transmission section 100 of the Ethernet (R) is transmitted at least at a preset time interval. Timelike variations in the clock extracted from reception data are detected at a clock speed adjustment section 13 based on an SFD (frame start section) detected by a speed conversion/frame conversion section 12 in the received Ether frames. A clock frequency generated at a clock generation section 14 is corrected based on the extracted clock. The corrected clock frequency is used for allowing a voltage-controlled crystal oscillator 17 to oscillate. The stability in the clock frequency at a network synchronization system level is obtained as the clock for transmitting devices at a desired frequency. When a fraction is generated while the clock for transmitting devices is divided, a division ratio is controlled by an automatic control division section 19. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a clock regeneration accuracy improving method and a clock regenerator, and more particularly, to a digital data synchronization subordinate to a synchronous communication network by a transmission device using an Ethernet interface mounting device that transmits / receives digital data to / from Ethernet (R). The present invention relates to a clock regeneration accuracy improving method and a clock regenerator for improving the stability of a clock for a transmission device regenerated in the transmission device so that multiplexed transmission can be performed.

  In recent years, infrastructure development using an Ethernet interface-equipped device for connection with Ethernet (R) has been rapidly progressing in many fields, and transmission lines have been made IP (Internet Protocol). However, in this case, it is difficult to convert the entire conventional synchronous multiplexing system to IP at once, and a transition period to IP conversion is essential.

  On the other hand, by making it possible to connect a conventional network synchronous communication system using an Ethernet interface, it is possible to easily construct a system at the time of shifting to digitalization and IP. In the field of use, there has been a significant demand for technology using an Ethernet interface. For example, there is a remarkable demand in the following transmission device field (device fields for various transmissions including terminal stations and multiplexing devices).

Taking a power security communication network as an example, an Ethernet interface-equipped device is used as a transmission device, and a conventional synchronous communication network (network synchronization device (NSE-LS) class of 5 × 10 ⁻⁵ or less as clock stability) The field of transmission terminal equipment that attempts to realize a connection with a system that is required to achieve stability.
Taking a power security communication network as an example, when an Ethernet interface-equipped device is used as a transmission device and the transmission speed of the transmission line is 176 kb / s, 384 kb / s, 768 kb / s, etc., there is a transmission band restriction The field of transmission terminal equipment that intends to realize synchronous multiplexing.
-Realizes the use of a system where synchronous communication was performed by LINE subordinate synchronization from a terminal station device at a business site where no network synchronization device was installed, with a transmission line that uses an Ethernet interface-equipped device as the transmission device. The field of transmission terminal equipment to try.

  In the following description, the clock stability of a transmission apparatus applied to a synchronous communication network will be described by taking a power security communication network as an example, but the same applies to other fields as described above.

  First, FIG. 5 shows an example of a system configuration using an Ethernet interface mounting device as a transmission device. When data transmission is performed from the PC 53 to the PC 54 or in the opposite direction via the Ethernet interface mounting devices 51 and 52, since packet communication uses IP (Internet Protocol) as a communication protocol, Data is transmitted and received asynchronously between the PCs 54 without synchronization.

  On the other hand, in the example of the existing power security communication network dependent synchronous transmission system shown in FIG. 6, a reference operation clock for data signal transmission is supplied from the network synchronization device (NSE-LS) 65 to the multiplexer master side 61. Thus, the data signal from the data transmission device 63 synchronized with the reference operation clock is received and transmitted to the multiplexing device clock LINE dependent side 62.

Further, the multiplexer clock LINE dependent side 62 reproduces a clock synchronized with the reference operation clock from the received data signal (B8ZS code: Bipolar with 8 Zeros Substation code) from the multiplexer master side 61. At this time, when the clock synchronized with the reference operation clock is regenerated from the received data signal as the subordinate synchronous transmission method, the stability of the clock regenerated on the multiplexer clock LINE subordinate side 62 is generally determined by the network synchronizer (NSE). -LS) Class 5 × 10 ⁻⁵ or less is required.

  Conventionally, when data transmission is performed as a synchronous transmission system that absorbs the configuration shown in FIG. 6 using the IP-based Ethernet interface configuration shown in FIG. 5, an HDSL (High-Bit-Rate Digital Subscriber Line) shown in FIG. 7 is used. The interface of the modems 71 and 72 is set to ITU-T G.264. As an interface of the 703 standard, synchronous multiplexed data transmission in which transmission is performed at a transmission rate of 1.544 Mb / s by connecting to the multiplexer master side 73 and the multiplexer clock LINE slave side 74 has been put into practical use. . FIG. 7 is an explanatory diagram for explaining synchronous multiplexing communication using a conventional IP transmission path.

  In the configuration shown in FIG. 5, it is assumed that the transmission signal speed is 768 kb / s, 384 kb / s, 176 kb / s or the like of 1.544 Mb / s or less. However, in the case of the synchronous multiplexed data transmission shown in FIG. The 703 standard interface does not specify these speeds. Therefore, when the HDSL modems 71 and 72 are switched to the 10BASE-T interface side in FIG. 7, even if an attempt is made to realize a synchronous multiplexing configuration with a transmission signal speed of 1.544 Mb / s or less, it corresponds to the transmission signal speed. Since clock recovery is not possible, a synchronous multiplexing configuration at 1.544 Mb / s or less cannot be realized as the prior art, and is limited to a transmission rate of 1.544 Mb / s.

  On the other hand, assuming a synchronous multiplexed transmission with a transmission signal speed of 1.544 Mb / s or less, ITU-T X. Considering the realization with the 21 standard, it is as shown in FIG. Here, FIG. FIG. 21 is an explanatory diagram for explaining an example of a transmission frame format in FIG. As shown in FIG. 8, the transmission frame has an envelope format and requires redundant bits such as the frame bit F and the status bit S before and after the data bits D1 to D6. Therefore, the transmission rate (for example, 64 kb / s) The data rate (for example, 48 kb / s) is not equal, and the transmission efficiency decreases.

In addition, in the physical layer (layer 1) of the Ethernet interface defined by the IEEE 802.3 standard shown in FIG. 5 (hereinafter described assuming 10BASE-T in the case of 10 Mb / s Ethernet (R)), a 10 MHz Manchester A code (Manchester code) is used. When the clock for the transmission apparatus is recovered from the received data signal by the Manchester code, the communication method in 10BASE-T is asynchronous communication, so the 10 MHz Manchester code is not continuously output and is extracted from the received data signal. The stability of the recovered clock can be obtained only about 2 × 10 ⁻² . For this reason, it is difficult to construct a synchronous multiplexed communication dependent on the signal on the LINE of the communication partner as a synchronous communication network, which hinders the transition to a transmission infrastructure for the future, and a solution is sought. It has been. It should be noted that the related art similar to the present invention having such a solution has been extensively investigated, but the similar technique could not be detected.

When performing synchronous multiplexing transmission synchronized with a synchronous communication network using an Ethernet interface that transmits / receives digital data to / from Ethernet (R) as a transmission device, it is extracted from the data signal received from Ethernet (R). As described above, the stability of the clock is 2 × 10 ⁻² , and does not become the network synchronization clock stability (5 × 10 ⁻⁵ or less) required for synchronous multiplexing transmission. Therefore, the transmission device using the Ethernet interface Connection to a synchronous communication network is difficult.

  For transmissions of 1.544 Mb / s or less, ITU-T G. Since there is no provision as an interface of 703 recommendation and arbitrary clock recovery corresponding to a transmission speed of 1.544 Mb / s or less is not realized, 1.544 Mb such as 768 kb / s, 384 kb / s, 176 kb / s, etc. / S or less synchronous multiplexing transmission cannot be realized, which hinders future transition to a transmission infrastructure.

The present invention has been made in consideration of the actual situation as described above. Even when an Ethernet interface that controls transmission / reception of digital data to / from the Ethernet (R) is used, the transmission device is subordinated to a synchronous communication network. The purpose is to improve the stability of the clock for the transmission device reproduced in the transmission device up to the network synchronization clock stability (5 × 10 ⁻⁵ or less) necessary for enabling the synchronous multiplexing transmission. It is a thing.

  According to a first aspect of the present invention, there is provided a clock reproduction accuracy improving method for improving the stability of a clock reproduced in a transmission apparatus for synchronously transmitting digital data via a synchronous communication network, wherein the transmission apparatus is connected to an Ethernet (R). When digital data transmission dependent on a synchronous communication network is performed using an Ethernet interface that transmits and receives digital data, the digital data received via the Ethernet interface is used for transmission within the transmission device. Therefore, the stability of the reproduction apparatus clock to be reproduced is improved.

  According to a second invention, in the first invention, the Ethernet interface is set to a predetermined data length, and digital data is transmitted and received at least at a predetermined time interval. The stability of the clock for the transmission device to be reproduced based on the received clock extracted from the received digital data is improved, and the digital data transmission dependent on the synchronous communication network is enabled. .

  According to a third aspect, in the second aspect, the stability of the received clock extracted from the digital data received via the Ethernet interface is the clock stability that enables digital data transmission depending on the synchronous communication network. The stability of the transmission device clock that is regenerated based on the received clock is set to a stability that enables digital data transmission depending on the synchronous communication network. It is characterized by that.

  According to a fourth aspect, in the third aspect, the digital data received from the Ethernet (R) via the Ethernet interface is converted to continuous serial data by buffering at least a predetermined data length. Based on the reception timing of the digital data obtained by the output, the time variation of the reception clock extracted from the reception digital data is corrected, and the stability of the reception clock is improved.

  According to a fifth aspect of the present invention, in any one of the first to fourth aspects, when the transmission device clock with improved clock stability is divided and output at an arbitrary clock frequency, the fraction is reduced at the time of division. When it occurs, automatic control of the division ratio to an arbitrary ratio makes it possible to generate an arbitrary clock frequency with improved clock stability, and using this clock frequency, digital data dependent on the synchronous communication network It is characterized by performing transmission.

  According to a sixth aspect of the present invention, there is provided a clock regenerator for regenerating a clock for a transmission device mounted in a transmission device for synchronously multiplexing transmission of digital data via a synchronous communication network, wherein the transmission device is connected to the Ethernet (R). When digital data transmission subordinate to a synchronous communication network is performed using an Ethernet interface that transmits and receives digital data between them, the digital data received via the Ethernet interface is used for transmission within the transmission device. It is characterized by having means for improving the stability of the clock for the transmission device to be reproduced for use.

  According to a seventh aspect, in the sixth aspect, the Ethernet interface is set to a predetermined data length, and digital data is transmitted / received at least at a predetermined time interval. The stability of the clock for the transmission device to be reproduced based on the received clock extracted from the received digital data is improved, and the digital data transmission dependent on the synchronous communication network is enabled. .

  According to an eighth aspect of the present invention, in the seventh aspect, the stability of the received clock extracted from the digital data received via the Ethernet interface is the clock stability that enables digital data transmission depending on the synchronous communication network. The stability of the transmission device clock that is regenerated based on the received clock is set to a stability that enables digital data transmission depending on the synchronous communication network. It is characterized by that.

  According to a ninth aspect, in the eighth aspect, the digital data received from the Ethernet (R) via the Ethernet interface is converted into continuous serial data by buffering at least a predetermined data length. Based on the reception timing of the digital data obtained by the output, the time variation of the reception clock extracted from the reception digital data is corrected, and the stability of the reception clock is improved.

  According to a tenth aspect of the present invention, in any one of the sixth to ninth aspects, when the transmission device clock with improved clock stability is divided and output at an arbitrary clock frequency, the fraction is reduced during division. If it occurs, it has a means to automatically control the frequency division ratio to an arbitrary ratio, so that an arbitrary clock frequency with improved clock stability can be generated, and the clock frequency is used to depend on the synchronous communication network. The digital data transmission is performed.

As is apparent from the technical means as described above, according to the present invention, at an arbitrary clock frequency based on the reception clock (reception timing signal) extracted from the reception data received from the Ethernet (R) via the Ethernet interface. It is possible to improve the stability of the generated transmission device clock to 5 × 10 ⁻⁵ or less of the network synchronization device (NSE-LS) class that enables synchronous multiplexed transmission depending on the synchronous communication network. As a result, synchronous multiplexing transmission is possible even on a transmission line having a transmission rate of 1.544 Mb / s or less. In addition, since it is possible to perform synchronous multiplexing transmission dependent on the synchronous communication network by the LINE dependent synchronization method, even if it is information in the office where the network synchronization device is not installed, the received signal from the transmission path is transmitted. Subordinate synchronization can be performed based on the data, and data transmission can be performed in the synchronous communication network, thereby improving the efficiency of the system configuration.

  As described above, the present invention relates to a clock recovery accuracy improvement method and a clock recovery unit that improve the stability of a clock that is reproduced in a transmission device that synchronously transmits digital data via a synchronous communication network. When digital data transmission dependent on a synchronous communication network is performed using an Ethernet interface that transmits / receives digital data to / from Ethernet (R), the transmission is performed using digital data received via the Ethernet interface. It is characterized by improving the stability of a transmission device clock to be reproduced for use in transmission within the device. Furthermore, the data is extracted from the digital data received through the Ethernet interface by setting the data length to be arbitrarily determined in advance as the Ethernet interface and transmitting / receiving digital data at least at a predetermined time interval. It is characterized in that the stability of the clock for the transmission device to be reproduced based on the reception clock is improved, and digital data transmission dependent on the synchronous communication network is enabled.

Accordingly, the clock stability of an arbitrary clock frequency reproduced as a transmission clock in the transmission apparatus is improved to 5 × 10 ⁻⁵ or less of the network synchronization apparatus (NSE-LS) class, and the transmission speed is 1.544 Mb. Synchronous multiplexed transmission is possible even on transmission lines below / s, and synchronous multiplexed transmission dependent on a synchronous communication network is also possible using the LINE dependent synchronization method.

  Hereinafter, an example of an embodiment of a clock regeneration accuracy improving method and a clock regenerator according to the present invention will be described in detail with reference to the drawings. In the following description, an embodiment for improving clock stability in a synchronous communication network will be described by taking a power security communication network as an example. However, the present invention is not limited to such a case, and Ethernet (R As long as it is a transmission apparatus having an Ethernet interface that transmits and receives digital data via the communication network, the same applies to any communication network.

  FIG. 1 is an explanatory diagram for explaining an embodiment of a clock reproduction accuracy improving method according to the present invention. As an example of a configuration for improving the stability of a clock reproduced as a transmission clock in a transmission apparatus, the present invention is described. 2 shows an example of a system configuration of an Ethernet interface mounting device receiving unit (clock transmission device side of the transmission device) mounted in the transmission device according to FIG. FIG. 2 is a frame configuration diagram for explaining an embodiment of the configuration of the Ethernet frame format according to the present invention. In the Ethernet interface mounting device receiving unit 10 shown in FIG. 1, the decoding unit 11 converts the 10 MHz-T 10 MHz Manchester code received from the Ethernet (R) transmitting unit 100 configured by the 10BASE-T transmission path to the 10 MHz NRZ signal. Is converted to digital data and output to the speed conversion / frame conversion unit 12, and at the same time, a 10 MHz clock component is extracted as a reception clock from the 10 MHz Manchester code received from the transmission unit 100, and the speed conversion / frame conversion unit 12 and the clock generator are generated. To the unit 14.

  At this time, the speed conversion / frame conversion unit 12 sends the received digital data received from the Ethernet (R) side to the data processing unit 10A at a data rate arbitrarily set (the clock generated by the clock generation unit 14). Speed) and output as application data in the NRZ signal format.

Further, the speed conversion / frame conversion unit 12 buffers the digital data in the ether frame (reference numeral 22a in FIG. 2) converted into the 10 MHz NRZ signal in the decoding unit 11, converts the digital data into continuous serial data, and sequentially outputs them. Thus, based on the reception timing of the digital data of the Ethernet frame 22a, a signal used for correcting the time variation of the reception clock extracted in the transmission apparatus is output. That is, the speed conversion / frame conversion unit 12 transmits the Ethernet frame transmitted from the transmission unit 100 of the Ethernet interface at a predetermined time interval (transmission interval [T ₀ ] in FIG. 2) with a predetermined data length. 22a is received via the decoding unit 11, and one byte of an SFD (Start Frame Delimiter) 22a ₂ following the preamble 22a ₁ shown in FIG. Then, a notification (SFD detection signal) indicating that the SFD 22a ₂ has been detected is output to the clock speed adjustment unit 13 for correction of clock time fluctuation.

The clock speed adjustment unit 13 extracts in the transmission device based on the reception start timing of the DATA 22a _3-1 (that is, the reception timing of the SFD 22a ₂ ) set in advance to an arbitrary data length in the DATA unit 22a ₃ of the Ethernet frame 22a. The time variation of the generated clock is detected, and an adjustment instruction (correction instruction) in a direction to cancel the error of the 10 MHz clock reproduced by the decoding unit 11 is output to the clock generation unit 14. The clock generation unit 14 reproduces an arbitrary clock frequency as a reception clock from the corrected 10 MHz clock corrected based on the adjustment instruction (correction instruction). At this time, the reception clock having an arbitrary clock frequency output from the clock generation unit 14 is input to the speed conversion / frame conversion unit 12, whereby the speed conversion / frame conversion unit 12 receives the digital received from the decoding unit 11. The speed of the data is converted into application data synchronized with the clock frequency input from the clock generator 14 and output to the data processor 10A.

FIG. 3 shows an example of a clock generation operation regenerated in the transmission apparatus. FIG. 3 illustrates an operation when the generated clock frequency is 176 kHz. 3, the SFD detection signal 31 is a signal output from the speed conversion / frame conversion unit 12 of FIG. 1 to the clock speed adjustment unit 13 when the SFD 22a ₂ shown in FIG. 2 is detected. The clock speed adjustment unit 13 monitors the SFD detection signal 31 output from the speed conversion / frame conversion unit 12 using a counter 32 that sequentially counts with a 10 MHz clock, and generates a phase of a 176 kHz clock to be generated. A correction instruction for correcting the error is output to the clock generation unit 14. In this case, in the normal state, the counter 32 uses a count value of 0 to 56, and monitors the temporal detection position of the SFD 22a ₂ with reference to the count value = 28 which is the central value of the counter 32.

When the clock frequency to be generated as the reception clock in the clock generation unit 14 is 176 kHz, the count value used as the counter 32 is given by a ratio with the 10 MHz clock,
10MHz / 176kHz = 56.8 ...
Therefore, the count value is in the range of 0 to 56 in the normal state. Therefore, when the clock frequency generated by the clock generator 14 is changed, the maximum value indicating the range counted by the counter 32 is changed and set according to the following equation 1.

  “Count” on the left side of Equation 1 represents the maximum value of the counter 32 to be obtained. On the other hand, “clk” on the right side of Expression 1 indicates a value of a clock frequency to be generated which is arbitrarily set.

In the example shown in FIG. 3, if the SFD 22a ₂ is detected just at the time when the count value of the counter 32 is 28, like the SFD detection signals 31a and 31d, the generated clock 35 is generated without error. Assuming that there is no phase error between the generated clock 35 and 10 MHz reproduced by the decoding unit 11, as shown in the generated clock 35, the counter 32 falls at the time “28”, and then reaches the maximum value “56”. The generated clock 35 rises at the time of the next “0”.

Further, when the SFD 22a ₂ is detected at the time when the count value of the counter 32 = 27 (count value <28) as in the SFD detection signal 31b, the phase delay of the generated clock 35 as shown in the phase delay detection 33 is shown. Is generated, the final value of the counter 32 is set to “55”, and the counter 32 is returned to “0” at the next count. At this time, as shown in FIG. 3, the generated clock 35 rises when the counter 32 that is the falling position of the pulse of the phase delay detection 33 is “0”, the error of the generated clock 35 is corrected, and the clock of FIG. It is output from the generator 14 to the frequency divider 15.

Further, when the SFD signal 22a ₂ is detected when the count value of the counter 32 is 29 (count value> 28) as in the SFD detection signal 31c, the phase of the generated clock 35 as indicated by the phase advance detection 34 is shown. A pulse signal for correcting the advance is generated, the final value of the counter 32 is set to “57”, and the counter 32 is returned to “0” at the next count. At this time, as shown in FIG. 3, the generated clock 35 rises when the counter 32 that is the falling position of the pulse of the phase advance detection 34 is “0”, the error of the generated clock 35 is corrected, and the clock of FIG. Output from the generator 14 to the frequency divider 15.

  The frequency dividing unit 15 shown in FIG. 1 inputs a clock generated as an arbitrary clock frequency by the clock generating unit 14 to the phase comparing unit 16 and is input to the phase comparing unit 16 for phase correction. The same frequency as the output from the peripheral portion 16A is generated. Here, the phase comparison unit 16 can perform phase correction on the generated arbitrary clock frequency based on the outputs of the voltage controlled crystal oscillator 17 and the phase correction frequency dividing unit 16A.

The voltage controlled crystal oscillator 17 shown in FIG. 1 is subjected to phase correction at an arbitrary clock frequency by the phase comparator 16 and has a frequency stability as a network synchronization device (NSE-LS) as a transmission device clock used for data transmission. ) Oscillate and output as a clock frequency with improved accuracy to 5 × 10 ⁻⁵ or less of level The external output clock divider / clock generator 18 arbitrarily sets the clock frequency of the clock for the transmission device of the voltage controlled crystal oscillator 17 whose frequency stability is improved to 5 × 10 ⁻⁵ or less as required. The frequency is divided to the set frequency, and a clock as necessary is generated and output to the outside.

  1 generates an arbitrary clock frequency of the transmission device clock, and when a frequency dividing fraction is generated by frequency division according to the transmission speed, the automatic control frequency dividing unit 19 sets the frequency dividing ratio to an arbitrary ratio. To generate an arbitrary clock frequency in which fractions are absorbed and output as a LINE clock.

Here, when the frequency dividing fraction is generated by the transmission speed, the automatic control frequency dividing unit 19 automatically controls the frequency dividing ratio to an arbitrary ratio, for example, as shown in the following Expression 2, To generate an averaged clock frequency. As a result, the frequency is appropriately divided, and the clock frequency of the transmission device clock corresponding to an arbitrary transmission speed is improved to a frequency synchronization level of 5 × 10 ⁻⁵ or less of the network synchronization device (NSE-LS) level. It becomes possible to reproduce the frequency.

  “Clk” on the left side of Equation 2 represents a desired clock frequency. “An” and “Bm” on the right side of Equation 2 are the values of the trace results for each frequency obtained at the arbitrarily set frequency division ratio. In addition, “i” and “k” in Equation 2 are the number of traces at an arbitrarily set division ratio.

FIG. 2 is a diagram for explaining an embodiment of the configuration of the ether frame format according to the present invention as described above. In the present invention, at least a predetermined time interval from the transmission unit 100 shown in FIG. An embodiment in which a time interval and a data length are set in advance for digital data transmitted with a predetermined data length is also described. In the figure, reference numeral 21 denotes an Ether frame transmission period waveform representing a pulse waveform of a predetermined transmission period [T ₀ ] of the Ether frame, and the transmission period [T ₀ ] is the transmission time [T ₁ ] of the Ether frame 22a. And the guard time defined in the IEEE 802.5 standard, that is, the guard time [T ₂ ] 22b.

Also, reference numeral 22 in FIG. 2 denotes an Ethernet frame configuration indicating the timing relationship between the Ethernet frame 22a and the guard time [T ₂ ] 22b of received data transmitted from the transmission unit 100 shown in FIG. In synchronization with the change in state of the pulse waveform of the periodic waveform 21, the Ethernet frame 22a and the guard time [T ₂ ] 22b are output.

In the figure, reference numeral 22a ₁ is a preamble in the ether frame 22a as described above, and is composed of 7 bytes, and constitutes a header identification signal of the ether frame 22a.
The SFD signal 22a ₂ is a delimiter indicating the start of the DATA part 22a ₃ and is composed of 1 byte.

The DATA unit 22a ₃ is reception data transmitted from the transmission unit 100 shown in FIG. Of the DATA part 22a ₃ , DATA 22a _3-1 represents a fixed-length data portion arbitrarily determined and set in advance by the present invention, and in this example, has a fixed length of 2 bytes. As described above, the Ethernet frame 22a including the DATA portion 22a ₃ is reliably transmitted at least at a predetermined time interval of the transmission cycle [T ₀ ].

The PAD 22a _3-2 is dummy data, which is 62 bytes in this example. That is, in this example, the DATA portion 22a ₃ has a fixed length of 64 bytes, which is the minimum data length defined by the IEEE 802.5 standard. Therefore, 2 bytes of DATA 22a _3-1 and 62 of dummy data PAD 22a _3-2 are used. It is composed of bytes.

  FIG. 4 shows an example of a synchronous multiplex transmission in the case of improving the clock stability according to the present invention as a connection configuration example of a multiplexing apparatus for synchronously multiplexing and transmitting digital data via a synchronous communication network. Yes. In the example shown in FIG. 4, instead of the conventional HDSL modems 71 and 72 shown in FIG. 7, two offices 1 and 2 each have an Ethernet interface mounting device 41 having the configuration shown in FIG. 42 shows a configuration in which 42 is installed and synchronously multiplexed at an arbitrarily determined transmission rate to transmit / receive data to / from each other. In FIG. 4, the multiplexer master side 43 arranged on the office 1 side transfers the data received from the data transmission device 45 in synchronization with the network synchronization clock from the network synchronization device 47 to the Ethernet interface (physical layer). The data is transmitted to the Ethernet interface mounting device 41 via the layer), and is synchronously transmitted as transmission data from the Ethernet interface mounting device 41 to the Ethernet interface mounting device 42 on the office 2 side.

  Here, the Ethernet interface mounting device 41 is arranged at the office 2 at a transmission path speed arbitrarily set to 768 kb / s, 384 kb / s, 176 kb / s, etc. even if it is 1.544 Mb / s or less. The transmission data can be synchronously transmitted to the Ethernet interface mounting device 42. The data signal received from the Ethernet interface mounting device 42 via the Ethernet interface (physical layer) is output to the data transmission device 46 via the multiplexing device clock LINE dependent side 44.

The multiplexing device clock LINE dependent side 44 extracts a clock dependent on the LINE from the data signal received from the Ethernet interface mounting device 42 via the Ethernet interface (physical layer layer). The clock having the same stability (5 × 10 ⁻⁵ or less) as that of the network synchronization device 47 used in the station 1 can be reproduced, and synchronous multiplexing transmission is possible. That is, since synchronous multiplexed transmission dependent on the synchronous communication network is possible in the LINE dependent synchronization method, even information in the office 2 where the network synchronization device 47 is not installed can be transmitted from the transmission line. Subordinate synchronization can be performed on the basis of the received signal, and data transmission can be performed in the synchronous communication network, so that the system configuration can be made more efficient.

It is explanatory drawing for demonstrating one Example of the structure for improving the clock reproduction | regeneration precision by this invention. It is explanatory drawing for demonstrating one Example of the structure of the ether frame format by this invention. It is explanatory drawing for demonstrating an example of the clock generation operation | movement by this invention. It is a block diagram which shows one Example of the synchronous multiplexing transmission at the time of aiming at the clock stability improvement by this invention. It is explanatory drawing for demonstrating the system configuration | structure with the conventional ether interface mounting apparatus. It is explanatory drawing for demonstrating the conventional power security communication network subordinate synchronous transmission. It is explanatory drawing for demonstrating the synchronous multiplexing communication using the transmission path made into the conventional IP. Conventional x. FIG. 21 is an explanatory diagram for explaining an example of a transmission frame format in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Ethernet interface mounting apparatus receiving part (clock regenerator side of transmission apparatus), 10A ... Data processing part, 11 ... Decoding part, 12 ... Speed conversion / frame conversion part, 13 ... Clock speed adjustment part, 14 ... Clock generation 15, frequency dividing unit, 16, phase comparison unit, 16 A, phase correcting frequency dividing unit, 17, voltage controlled crystal oscillator, 18, external output clock frequency dividing / clock generating unit, 19, automatic control frequency dividing unit 21 ... Ether frame transmission period waveform, 22 ... Ether frame configuration, 22a ... Ether frame, 22b ... Guard time, 22a ₁ ... Preamble, 22a ₂ ... SFD, 22a ₃ ... DATA part, 22a _3-1 ... DATA, 22a _{3 -2} ... PAD, 31, 31a, 31b, 31c, 31d ... SFD detection signal, 32 ... counter, 33 ... phase delay detection, 34 ... phase advance detection, 35 ... Generated clock, 41, 42 ... Ethernet interface mounting device, 43 ... Multiplexer master side, 44 ... Multiplexer clock LINE slave side, 45,46 ... Data transmission device, 47 ... Network synchronization device (NSE-LS), 51, 52... Ether interface mounting device, 53, 54... PC, 61 .. Multiplexer master side, 62... Multiplexer clock LINE slave side, 63, 64. , 71, 72 ... HDSL modem, 73 ... multiplexer master side, 74 ... multiplexer clock LINE subordinate side, 75, 76 ... data transmission device, 77 ... network synchronization device (NSE-LS), 100 ... transmitter .

Claims (10)

  In a clock reproduction accuracy improving method for improving the stability of a clock reproduced in a transmission apparatus that synchronously transmits digital data via a synchronous communication network, the transmission apparatus transmits / receives digital data to / from Ethernet (R). When digital data transmission dependent on a synchronous communication network is performed using an Ethernet interface, the digital data received via the Ethernet interface is used for reproduction within the transmission apparatus for use in transmission. A method for improving the clock reproduction accuracy, characterized by improving the stability of the clock for use.   2. The clock reproduction accuracy improving method according to claim 1, wherein the Ethernet interface is set to a predetermined data length and digital data is transmitted / received at least at a predetermined time interval. Clock recovery accuracy, which improves the stability of the clock for the transmission device that is recovered based on the received clock extracted from the received digital data, and enables digital data transmission dependent on the synchronous communication network Improvement method.   3. The clock recovery accuracy improving method according to claim 2, wherein the stability of the received clock extracted from the digital data received via the Ethernet interface is set to a clock stability that enables digital data transmission depending on a synchronous communication network. The stability of the transmission device clock that is regenerated based on the received clock is set to a stability that enables digital data transmission depending on the synchronous communication network. A method for improving the accuracy of clock recovery.   4. The clock reproduction accuracy improving method according to claim 3, wherein digital data received from the Ethernet (R) through the Ethernet interface is converted into continuous serial data by buffering at least a predetermined data length. Based on the reception timing of the digital data obtained by the output, the time variation of the reception clock extracted from the reception digital data is corrected, and the stability of the reception clock is improved. Method.   5. The clock regeneration accuracy improving method according to claim 1, wherein a fraction is generated at the time of frequency division when the clock for transmission device with improved clock stability is divided and output at an arbitrary clock frequency. In such a case, it is possible to generate an arbitrary clock frequency with improved clock stability by automatically controlling the division ratio to an arbitrary ratio, and using this clock frequency, digital data transmission dependent on the synchronous communication network A method for improving clock reproduction accuracy, characterized in that:   In a clock regenerator that regenerates a clock for a transmission device mounted in a transmission device that synchronously multiplexes and transmits digital data via a synchronous communication network, the transmission device transmits and receives digital data to and from the Ethernet (R). When digital data transmission dependent on a synchronous communication network is performed using an Ethernet interface, the digital data received via the Ethernet interface is used for transmission to be used for transmission within the transmission apparatus. A clock regenerator comprising means for improving the stability of a device clock.   7. The clock regenerator according to claim 6, wherein the ether interface is set to a predetermined data length, and is received via the ether interface by transmitting / receiving digital data at least at a predetermined time interval. A clock regenerator that improves the stability of a clock for a transmission device that is regenerated based on a received clock extracted from the digital data, and enables digital data transmission dependent on a synchronous communication network.   8. The clock regenerator according to claim 7, wherein the stability of the received clock extracted from the digital data received via the Ethernet interface is increased to a clock stability capable of digital data transmission depending on a synchronous communication network. By setting to a level that can be improved, the stability of the clock for the transmission device that is regenerated based on the received clock is set to a stability that enables digital data transmission depending on the synchronous communication network. A featured clock regenerator.   9. The clock regenerator according to claim 8, wherein digital data received from the Ethernet (R) via the Ethernet interface is converted into continuous serial data by buffering at least a predetermined data length and output. A clock regenerator which corrects the time variation of the reception clock extracted from the reception digital data based on the reception timing of the digital data obtained thereby to improve the stability of the reception clock.   10. The clock regenerator according to any one of claims 6 to 9, wherein a fraction occurs during frequency division when the transmission device clock with improved clock stability is divided into an arbitrary clock frequency and output. By providing means for automatically controlling the division ratio to an arbitrary ratio, it is possible to generate an arbitrary clock frequency with improved clock stability, and using the clock frequency, digital data dependent on the synchronous communication network is generated. A clock regenerator that performs transmission.

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