JP2005303120A - Method for simulating characteristic of semiconductor device, structure design of semiconductor device by using the method, and manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To calculate the whole action of a power device (element) more accurately as compared with a conventional method when voltage is impressed to the element in the characteristic simulation of a semiconductor device having the element. <P>SOLUTION: A simulation mode is constituted of an inner cell 1 and a peripheral cell 2. For instance, all drain contacts 3 of the inner cell 1 and the peripheral cell 2 are connected in parallel and electrically connected to a drain electrode terminal 25. A first drain electrode resistor 31 is arranged in a wire 24a for connecting the drain contact 3 of the peripheral cell 2 to the drain electrode terminal 25. A second drain electrode resistor 32 is arranged on a position 24b which is included in a wire 24, and excluded from the wire 24a connecting the drain contact 3 of the peripheral cell 2 to the drain electrode terminal 25. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device characteristic simulation method, and a semiconductor device structure design method and manufacturing method using the method, and more particularly, to a power device characteristic simulation and a semiconductor device structure design method and manufacture having a power device. Regarding the method.

  Conventionally, in the power device field, the software required for analysis and design of semiconductor devices on a computer (computer) called TCAD (Technology Computer Aided Design) has been used to improve the efficiency of device structure design. Yes.

  As a method for simulating the behavior of the entire device such as surge analysis of a power device and withstand voltage DC characteristics, there are the following methods.

  For example, when performing IGBT surge analysis, an IGBT simulation model in which a cell region and a cell peripheral region are modeled is created.

At this time, a model of the cell region is obtained by converting an N ⁺ type buffer layer, an N ⁻ type drift region, a P type base region, and a surface layer portion of the P type base region, which are sequentially formed on the P ⁺ type semiconductor substrate (collector region). and the N ⁺ -type emitter region formed in the gate insulating film and a gate electrode formed in a trench penetrating through the P-type base region and the N ⁺ -type emitter region, the emitter region, respectively and the collector region is electrically connected to A structure having an emitter electrode and a collector electrode.

Moreover, the model of the cell edge region, N ⁺ -type buffer layer formed in this order on a P ⁺ -type semiconductor substrate, N ^- has a guard ring formed in the surface layer of the type drift region like ^- -type drift region, N Structure.

Then, the N ⁺ type buffer layers of the respective models are electrically connected through a coupling resistor.

  Surge analysis is performed by TCAD using a simulation model having such a structure (see, for example, Patent Document 1).

Such a simulation model is usually formed by a user inputting coordinates (numerical values) of each component of the power device to a computer using a draw tool (software). That is, the coordinates (x, y, z) of the part to be modeled in the power device are input to the TCAD, and further, the constituent elements (silicon, oxide film, impurity introduction region) of the power device are obtained by combining these coordinate points. Etc.) is specified, a simulation model is created. In this coordinate input, if the cell is modeled, it is necessary to input the coordinates of all the points of the cell. In particular, the creation of the model of the 3D structure is very troublesome.
JP 2002-373899 A

  However, the above-described simulation model of the structure is not a structure that takes into account the resistance of the gate electrode made of PolySi and the wiring resistance of the emitter and collector electrodes. For this reason, in the simulation model having the above structure, the wiring resistance difference due to the distance between the distance from the cell region to the electrode terminal (pad) and the distance from the cell peripheral region to the electrode terminal (pad) has not been reproduced.

  In an actual power device, a current bias that the current flowing in the cell region and the current flowing in the cell peripheral region differ due to the wiring resistance difference between the cell region and the cell peripheral region. This current bias causes local breakdown due to surge.

  Therefore, in the simulation method described above, the current bias in the cell region and the cell peripheral region, which cause local breakdown due to surge, could not be reproduced, so it was not possible to calculate accurately in surge analysis of power devices. .

  Note that this problem is not limited to a discrete element composed of a single power device, but also to a composite IC in which a power device, a bipolar transistor, a CMOS, and the like are formed on the same substrate. Arise. In general, a composite IC has a thin electrode wiring and a large wiring resistance as compared with a discrete element composed of a single power device. Therefore, a current generated by a distance from a cell region or a cell peripheral region to a pad is reduced. Bias tends to occur. For this reason, the above-described problem is particularly noticeable in the composite IC than in the discrete element configured from a single power device.

  In the simulation method described above, when a simulation is performed by changing a model once simulated to another model, the user has to input coordinates again to the computer. For example, when changing the width of the oxide film formed by the LOCOS method, it is necessary to specify from which point to which point the oxide film is, and therefore it is necessary to input coordinates again.

  For this reason, in particular, when there are many coordinates to be input as in the case where the simulation model has a three-dimensional structure, there is a problem that it takes much time and the user's work efficiency is poor.

  In view of the above points, the present invention provides the entire device when a voltage is applied to the element in the characteristic simulation of the semiconductor device having the power device (element) and the structure design and manufacturing method of the semiconductor device using the simulation method. The first object is to make it possible to calculate the above behavior more accurately than in the prior art, and the second object is to increase the work efficiency compared to the prior art.

  To achieve the above object, according to the first aspect of the present invention, the first cell (1) having the first electrode (3, 4, 22), the first electrode (3, 4, 22), A second cell (2, 2a, 2b, 2c) having a second electrode (3, 4, 22) electrically connected in parallel, a first electrode (3, 4, 22) and a second Electrode terminals (25, 27, 29) and first electrodes (3, 4, 22) electrically connected to both electrodes (3, 4, 22) by wiring (24, 26, 28). And in the wiring (24, 26, 28) connecting the electrode terminal (25, 27, 29) and the second electrode (3, 4, 22) and the electrode terminal (25, 27, 29) A first resistor (31, 33, 35) disposed in the wiring (24a, 26a, 28a) connecting the first electrode (3, 4, 22), and In the wiring (24, 26, 28) connecting the electrode terminals (25, 27, 29), the second electrode (3, 4, 22) and the electrode terminals (25, 27, 29) are connected. Using a simulation model of a structure having a second resistor (32, 34, 36) arranged at a position (24b, 26b, 28b) excluding the inside of the wiring (24a, 26a, 28a) to be It is characterized by simulating characteristics.

  By setting the structure of the simulation model to the structure having the first resistance and the second resistance in this way, the wiring resistance of the electrodes of the actual power device can be included in the simulation model.

  Then, the structure of the simulation model is obtained by arranging both the first resistor and the second resistor in the wiring connecting the first electrode and the electrode terminal of the first cell, and the second cell has By adopting a structure in which only the first resistor of the first resistor and the second resistor is disposed in the wiring connecting the two electrodes and the electrode terminal, the electrodes from the electrodes in the plurality of cells of the power device are provided. It is possible to reproduce the wiring resistance difference of the electrodes due to the difference in distance to the terminals.

  As a result, according to the present invention, it is possible to calculate the behavior of the entire element when a voltage is applied to the element by reproducing the current bias generated in the actual power device to be simulated. As a result, according to the present invention, the behavior of the entire device can be calculated more accurately than the conventional simulation method.

  Note that the resistance values of the first resistor and the second resistor are arbitrarily set in consideration of the distance to the electrode terminal in the actual cell to be modeled.

  For example, as shown in claim 2, in a planar layout in which a plurality of cells are arranged, a model of a cell located inside is set as a first cell, and the cell is located around the inside cell in the plane layout. In the case where the modeled cell is the second cell, the resistance value of the second resistor (32, 34, 36) located in the vicinity is determined from the resistance value of the first resistor (31, 33, 35). Can also be set to be large.

  This is because the electrode terminals are usually arranged on the outer periphery of the cell in a planar layout, and the internal cells are farther away from the peripheral cells than the peripheral cells.

  The invention according to claim 3 is characterized in that a predetermined dimension is input to a computer, a plurality of coordinates are calculated based on the dimension by the computer, and a simulation model is created.

  In this way, by calculating the coordinates from the dimensions between the coordinates and creating the simulation model from the calculated coordinates, compared with the case where the coordinates of all points are input to the computer in order to create the simulation model Thus, items to be input to the computer can be reduced.

  This allows you to change the model once simulated to another model and perform the simulation, because there are fewer input items than when inputting the coordinates of all points to the computer. Compared with the case where it does, work efficiency can be improved.

  In the invention according to claim 4, the boundary surfaces (5a, 5b, 5c) between the constituent parts (5, 11, 22) made of different materials among the plurality of constituent parts are formed on the semiconductor substrate (17). It is characterized by being approximated to a plane parallel to or perpendicular to the main surface.

  For example, in the power device to be simulated, if the component part is a tapered shape, a simulation model that approximates the tapered shape to a rectangular parallelepiped, compared with a structure that does not approximate the simulated tapered shape to a rectangular parallelepiped Thus, it is possible to reduce the number of irregular meshes that causes a decrease in the convergence of calculation.

  This makes it possible to increase the convergence of the calculation, shorten the calculation time, and enable the calculation itself, compared with the simulation model in which the taper shape of the simulation target is a structure that does not approximate a rectangular parallelepiped. .

  Further, as shown in claim 5, the first and second cells (1, 2, 2a, 2b, 2c) can have a three-dimensional structure.

  Thereby, compared with the case where a simulation model is made into a two-dimensional structure, a highly accurate calculation result can be obtained.

  Further, as shown in claim 6, the device structure of the semiconductor device can be designed by using the simulation result by the characteristic simulation method of the semiconductor device according to any one of claims 1 to 5.

  According to a seventh aspect of the present invention, device design is performed using a simulation result obtained by the semiconductor device characteristic simulation method according to any one of the first to fifth aspects, and a semiconductor element is formed based on the device design. can do.

  In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

(First embodiment)
In the present embodiment, a case where a surge analysis of a power MOS transistor (LDMOS) is performed will be described as an example. Note that the present embodiment is different from the prior art mainly in the structure and creation method of a simulation model used for characteristic simulation.

  FIG. 1 shows a simulation model used for characteristic simulation in the first embodiment of the present invention. 2 shows a plan view of the internal cell 1 in FIG. 1, FIG. 3 shows a cross-sectional structure of the internal cell 1 in FIG. 1 (an enlarged view of the hatched area in FIG. 1), and FIG. The cross-sectional structure (enlarged view of the hatched area in FIG. 1) of the peripheral cell 2 is shown.

  On the other hand, FIG. 5 shows a plan view of the LDMOS to be simulated, and FIG. 6 shows a cross section along line A-A ′ of the LDMOS of FIG. 5. 7 to 11 are exploded views of the LDMOS of FIG. The LDMOS shown in FIG. 5 is obtained by sequentially stacking the patterns shown in FIGS. 8 to 11 on the pattern shown in FIG.

  First, the structure of the LDMOS to be simulated will be described.

  The LDMOS that is a simulation target of the present embodiment is formed as a power device for a composite IC, and is formed on an SOI substrate.

  As shown in FIG. 5, the LDMOS includes a cell region in which a plurality of drain cells 41 and a plurality of source cells 42 are disposed, a gate wiring region disposed around the cell region and provided with a gate contact 43. In addition, it has electrode terminals (pads) 44 disposed around the electrodes and electrically connected to the electrodes formed in the cell region.

In the drain cell 41, as shown in FIG. 6, the N ^{− of the} SOI substrate 48 having a P ⁺ type Si substrate 45, a buried oxide film (SiO ₂ ) 46, an N ⁺ type Si layer 47, and an N ⁻ type Si layer 11. An N-type well layer 12 is formed on the Si-type layer 11, and an N ⁺ -type contact layer 13 is formed on the surface layer of the N-type well layer 12.

  In the drain cell 41, an oxide film (LOCOS oxide film) 5 formed by the LOCOS method is disposed on the main surface of the SOI substrate 48 and on both ends of the N-type well layer 12. The end of the LOCOS oxide film 5 has a tapered shape called a bird's beak.

Further, on the surface of the SOI substrate 48, a BPSG film 49, 1stAl wirings 50 and 50a, TEOS film 51, 2ndAl wirings 52 and 52a, and a SiN film 53 are sequentially arranged. The 1stAl wiring 50a is electrically connected to the N ⁺ -type contact layer 13 through a contact hole formed in the BPSG film 46, and the 2stAl wiring 52a is connected through a via hole formed in the TEOS film 51. It is electrically connected to the 1st Al wiring 50a. The 1stAl wiring 50a, the 2stAl wiring 52a, and the like are drain electrodes.

In the source cell 42, the channel P type well layer 14 is formed in a region different from the drain cell 41 region in the N ⁻ type Si layer 11 of the SOI substrate 48, and the N ⁺ type layer 15 is formed in the channel P type well layer 14. In the source cell 42 in which the P ⁺ -type layer 16 is formed, the gate oxide film 21 is formed on the surfaces of the N ⁻ -type Si layer 11 and the channel P-type well region 14, and the PolySi is formed on the gate oxide film 21. A gate electrode 22 is formed.

Also in the source cell 42, a BPSG film 46, 1st Al wirings 50 and 50 b, TEOS film 51, 2nd Al wirings 52 and 52 b, and a SiN film 53 are sequentially arranged on the surface of the SOI substrate 48. The 1stAl wiring 50b is electrically connected to the P ⁺ -type layer 15 and the N ⁺ -type layer 16 through a contact hole formed in the BPSG film 46, and the 2stAl wiring 52b is formed in the TEOS film 51. It is electrically connected to the 1st Al wiring 50b through a via hole. The 1stAl wiring 50b and the 2stAl wiring 52b are source electrodes.

As shown in FIG. 7, the drain cell 41 and the source cell 42 are alternately arranged in the vertical and horizontal directions in the plan layout. In FIG. 7, in the drain cell 41 and the source cell 42, the contact surface (drain contact) 3 of the drain electrode and the N ⁺ -type contact layer 13, the source electrode, the P ⁺ -type layer 15, and the N ⁺ -type layer, respectively. The contact surface (source contact) 4 with 16 is shown. The area of the entire LDMOS is about several mm 2 and the cell pitch 54 is, for example, 10 μm.

  In the gate wiring region, a LOCOS oxide film 5 is formed on the surface of the SOI substrate 48 as shown in FIG. On the surface of the LOCOS oxide film 5, a gate electrode 22 made of PolySi extends from the cell region, and the gate electrode 22 is electrically connected to the gate electrode wiring 50 c made of 1st Al on the BPSG film 46. Connected.

  Although omitted in FIG. 6, a trench 55 for element isolation is formed in the gate wiring region as shown in FIG.

  Further, as shown in FIG. 8, the gate electrode 22 has a pattern in which unnecessary portions of PolySi formed on the entire surface of the LDMOS substrate are removed. A gate contact 43 that is a contact surface between the gate electrode 22 and the gate wiring 50c is arranged in a peripheral region (gate wiring region) of the cell region.

  Further, as shown in FIG. 9, in the first layout 50a and 50b constituting the drain electrode and the source electrode, the strip-like source electrode 50b and the drain electrode 50a are alternately and obliquely arranged on the cell region in the planar layout. . Further, as shown in FIG. 9, the 1st Al 50c constituting the gate wiring is arranged in a square frame shape so as to surround the cell region. The 1stAl 50c constituting the gate wiring has a gate terminal 50d on the lower left side in the figure, and is electrically connected to a gate drive circuit (not shown) via this gate terminal.

  Also in the region where the electrode terminal 44 is formed, 1st Al wirings 50e and 50f connected to the drain electrode and the source electrode, respectively, are arranged.

  These 1st Al 50a, 50b, 50c, 50e, and 50f are composed of the 2nd Al wiring 52a by the via 56a for the drain electrode, the via 56b for the source electrode, and the vias 56c and 56d for the electrode terminal 44 shown in FIG. , 52b, 52c, and 52d.

  Further, as shown in FIG. 11, the 2ndAl wiring 52 constituting the drain electrode and the source electrode has cell-shaped portions 52a and 52b extending in both the left and right directions in the figure, and are alternately arranged in the plane layout. Is arranged. The 2ndAl wirings 52a and 52b in the cell region are connected to the 2ndAl 52c and 52d formed in the region of the electrode terminal 44, respectively. In this way, the drain electrode and the source electrode in the cell region are electrically connected to the drain electrode terminal 44 and the source electrode terminal 44, respectively.

  Next, a simulation model of the LDMOS having the above structure will be described. The simulation model shown in FIG. 1 is a 3D (three-dimensional structure) model in which the LDMOS structure is divided into an inner part and a peripheral part, and includes an internal cell 1 and a peripheral part cell 2. The internal cell 1 and the peripheral cell 2 correspond to the first cell and the second cell of the present invention, respectively.

  Here, the inside of the LDMOS is a region on the inner side of the cell region and the gate wiring region shown in FIG. 7. For example, when attention is paid to the drain cell 41, the drain cell 41 is driven by the source cell 42 from four directions. It is an enclosed area. Thus, the inside means a region where the drain cells 41 and the source cells 42 are periodically arranged.

  On the other hand, the peripheral portion of the LDMOS is the inner peripheral region of the cell region and the gate wiring region shown in FIG. 7, for example, the drain cell 41 is surrounded by the source cell 42 from three directions and two directions. It is the area that is. Thus, the peripheral portion means a region where the periodicity of the drain cell 41 and the source cell 42 is different from the inside.

  As described above, the LDMOS is roughly classified into two types, that is, the inner part and the peripheral part in terms of the periodicity of the drain cell 41 and the source cell 42 in the planar layout.

  Therefore, in this embodiment, the simulation model is configured by the internal cell 1 and the peripheral cell 2. Specifically, each of the internal cell 1 and the peripheral cell 2 models a broken line region B located in the center in the drawing and a broken line region C located in the periphery of the cell regions shown in FIG. It has become. In FIG. 1, the same components as those in FIGS. 5 and 6 are denoted by the same reference numerals.

  The internal cell 1 of the simulation model has the same cross-sectional structure as that of the broken line region D in FIG. 6, and the source contact 4 of the source cell 42 from the center of the drain contact 3 of the drain cell 41 as shown in FIG. 6. This corresponds to a single cell when the region up to the center of the cell is a single cell.

  On the other hand, the peripheral cell 2 of the simulation model has a cross-sectional structure similar to the cross-sectional structure of the broken line region E in FIG. 6, and includes 1.5 single cells described above and a gate wiring region. .

  As shown in FIG. 2, the internal cells 1 in FIG. 1 have a substantially square planar shape and are alternately arranged so that the drain contacts 3 and the source contacts 4 are adjacent to each other at the four corners of the substantially square. .

  1 has a drain contact 3, a LOCOS oxide film 5, a gate oxide film 6, and a source contact 4 arranged in this order from the lower left to the lower right in FIG. . 1 and 2, the drain electrode 18, the source electrode 20, and the gate electrode 22 are omitted.

The internal cell 1 in FIG. 1, as shown in FIG. 3, N ^- -type Si layer 11, N ^- and N-type well layer 12 formed in the surface layer of the type Si layer 11, N-type well layer 12 An N ⁺ -type contact layer 13 formed on the surface layer and an N ⁻ -type Si layer 11, a P-type well layer 14 formed in a region different from the N-type well layer 12, and a P-type well layer 14 The cross-sectional structure has an N ⁺ type layer 15 and a P ⁺ type layer 16 formed on the surface layer.

The internal cell 1 in FIG. 1, as shown in FIG. 3, N ^- A on the main surface of the substrate 17 having the type Si layer 11, N-type well layer 12 and the P-type well layer 14, ^{N +} Drain electrode 18 disposed on type contact layer 13, LOCOS oxide film 19 disposed on N type well layer 12 and N ⁻ type Si layer 11, P ⁺ type layer 16 and N ⁺ type layer 15. Source electrode 20 disposed on the gate electrode, gate oxide film 21 disposed on P-type well layer 14 and N ⁻ -type Si layer 11, gate oxide film 21 and LOCOS oxide film 5. , And a gate electrode 22 made of PolySi.

In the present embodiment, the tapered shape at the end portion 5 a of the LOCOS oxide film 5 is a plane or a plane perpendicular to the surface of the N ⁻ -type Si layer 11. Of the surface of the N ⁻ -type Si layer 11, the boundary surface 5 b with the LOCOS oxide film 5 is a surface parallel to or perpendicular to the main surface of the substrate 17. Further, in the gate electrode 22, the boundary surface 5 c with the LOCOS oxide film 5 is a surface parallel to or perpendicular to the main surface of the substrate 17. Thus, in the model of FIG. 1, the shapes of the LOCOS oxide film 5 and the gate electrode 22 are rectangular parallelepipeds.

On the other hand, as shown in FIG. 4, the peripheral cell 2 in FIG. 1 has the same structure as that of the internal cell 1 in the left half of FIG. 4 and a gate wiring region added to the right half. Specifically, as shown in the right side of FIG. 4, peripheral cell 2 includes LOCOS oxide film 5 and gate oxide film 21 disposed on the surface of N ⁻ -type Si layer 11, LOCOS oxide film 5 and The gate electrode 22 is disposed on the gate oxide film 21 and made of PolySi.

Also in the peripheral cell 2, the end surface 5 a of the LOCOS oxide film 5 is not tapered but is a surface parallel to or perpendicular to the main surface of the substrate 17. Of the surface of the N ⁻ -type Si layer 11, the boundary surface 5 b with the LOCOS oxide film 5 is a surface parallel to or perpendicular to the main surface of the substrate 17. Further, in the gate electrode 22, the boundary surface 5 c with the LOCOS oxide film 5 is a surface parallel to or perpendicular to the main surface of the substrate 17. These surfaces 5a, 5b, and 5c correspond to the boundary surfaces between components that are made of different materials of the present invention.

As shown in FIGS. 3 and 4, the internal cell 1 and the peripheral cell in FIG. 1 are provided with a thermal electrode 23 on the bottom surface of the N ⁻ -type Si layer 11. The hot electrode 23 is a virtual electrode for calculation in consideration of heat radiation from the element due to a heat sink or the like normally provided in the semiconductor device.

  Further, as shown in FIG. 1, all the drain electrodes 18 (drain contacts 3) of the internal cell 1 and the peripheral cell 2 are connected in parallel to each other by the wiring 24, and further, the drain electrode terminal 25 and the wiring 24 is electrically connected. The drain electrode terminal 25 corresponds to the electrode terminal 44a in FIG.

  Similarly, all the source electrodes 20 (source contacts 4) of the internal cell 1 and the peripheral cell 2 are also connected in parallel to each other by the wiring 26, and are further electrically connected by the source electrode terminal 27 and the wiring 26. In addition, all the gate electrodes 22 (not shown in FIG. 1) of the internal cell 1 and the peripheral cell 2 are also connected in parallel by the wiring 28, and are further electrically connected by the gate electrode terminal 29 and the wiring 28. It is connected to the. The source electrode terminal 27 and the gate electrode terminal 29 correspond to the 1st Al wiring 50d as the electrode terminal 44b and the gate electrode terminal in FIG. 5, respectively. Note that the wiring itself in the model is assumed to have no resistance.

  The drain electrode 18 (drain contact 3), the source electrode 20 (source contact 4) and the gate electrode 22 of the internal cell 1 correspond to the first electrode of the present invention, and the drain electrode 18 (drain contact) of the peripheral cell 2 3) The source electrode 20 (source contact 4) and the gate electrode 22 correspond to the second electrode of the present invention. The broken lines 24, 26 and 28 correspond to the wiring of the present invention.

  As shown in FIG. 1, the simulation model of the present embodiment is in the wiring 24 that connects the drain electrode 18 (only the drain contact 3 is shown in FIG. 1) of the internal cell 1 and the drain electrode terminal 25. The first drain electrode resistor 31 disposed in the wiring 24 a connecting the drain electrode 18 (drain contact 3) and the drain electrode terminal 25 of the peripheral cell 2 among the wiring 24, and the internal cell 1 The drain electrode 18 (drain contact 3) and the drain electrode terminal 25 of the peripheral cell 2 are connected to the drain electrode 18 (drain contact 3) and the drain electrode terminal 25. And a second drain electrode resistor 32 disposed only in the wiring 24b except in the wiring 24a.

  That is, in the present embodiment, the structure of the simulation model is configured such that the first drain electrode resistor 31 and the second drain electrode 18 (drain contact 3) and the drain electrode terminal 25 included in the internal cell 1 are connected in the wiring 24. Both the first drain electrode resistor 31 and the second drain electrode resistor 32 are disposed in a wiring 24 a that connects the drain electrode 18 (drain contact 3) of the peripheral cell 2 and the drain electrode terminal 25. Of the two drain electrode resistors 32, only the first drain electrode resistor 32 is arranged. The first drain electrode resistor 31 and the second drain electrode resistor 32 correspond to the first resistor and the second resistor of the present invention, respectively.

  At this time, the first drain electrode resistor 31 has a width (W), a length (L), and a thickness (d) of the 1st Al wiring 50a, the via 56a, and the 2nd wiring 52a shown in FIGS. It is calculated and set from the resistance value peculiar to the material. That is, the size of the first drain electrode resistor 31 depends on the average distance from the cell in the peripheral part (position of the broken line region C) in FIG. 7 to the drain electrode terminal 25 and the pattern of the electrode wirings 50, 52, and 56. It is set in consideration of the occupation rate.

  Similarly, the size of the second drain electrode resistor 32 takes into account the average distance from the cell (in the broken line region B) in FIG. 7 to the drain electrode terminal 25 and the pattern occupancy of the electrode wiring. The resistance value of the first drain electrode resistor 31 is subtracted from the resistance value thus set.

  At this time, in the LDMOS to be simulated, the distance from the drain electrode 18 (drain contact 3) to the drain electrode terminal 25 is longer in the internal cell 1 than in the peripheral cell 2. For this reason, each resistance value is set so that the resistance value of the second drain electrode resistor 32 is larger than that of the first drain electrode resistor 31.

  Further, in the simulation model of FIG. 1, in the wiring 26 that electrically connects the source electrode 20 (only the source contact 4 is shown in FIG. 1) of the internal cell 1 and the peripheral cell 2 and the source electrode terminal 27. Similar to the drain, a first source electrode resistor 33 and a second source electrode resistor 34 are arranged. The magnitudes of the first source electrode resistor 33 and the second source electrode resistor 34 are set in the same manner as the first drain electrode resistor 31 and the second drain electrode resistor 32.

  In the simulation model of FIG. 1, the wiring 28 that electrically connects the gate electrode 22 (source contact 4) and the gate electrode terminal 29 of the internal cell 1 and the peripheral cell 2 and the gate electrode terminal 29, as well as the drain, A first gate electrode resistor 35 and a second gate electrode resistor 36 are arranged.

  As shown in FIGS. 8 and 9, the sizes of the first gate electrode resistor 35 and the second gate electrode resistor 36 are also the distance from each cell to the gate electrode terminal 50d and the pattern occupation ratio of the patterned PolySi 22 And the width (W), length (L), thickness (d), and resistance value peculiar to the material of the 1st Al wiring 50c.

  The first source electrode resistor 33 and the first gate electrode resistor 35 correspond to the first resistor of the present invention, and the second source electrode resistor 34 and the second gate electrode resistor 36 are the main resistors. This corresponds to the second resistor of the invention.

  Next, a surge analysis method using the model configured as described above will be described. First, when a user inputs structural parameters to a computer having TCAD software, a simulation model having the above-described structure is created by the computer.

  As described in the above background art section, conventionally, a simulation model is created by inputting all the coordinates of a cell to be modeled into a computer. On the other hand, in this embodiment, focusing on the fact that the coordinates of the cell can be defined only by the structural parameters necessary for the computer without inputting all the coordinates of the cell, the coordinates are automatically calculated from the structural parameters by the computer. I am trying to calculate.

These structural parameters are the dimensions that serve as design criteria for the simulation model.
Combining these dimensions allows the program to calculate coordinates and form a model. This structural parameter corresponds to the predetermined dimension of the present invention.

  FIG. 12A shows an example of numerical input setting of the structural parameter, FIG. 12B shows an example of conversion from the structural parameter to the coordinate variable, and FIG. 12C shows an example of definition of the electrode by the coordinate variable.

In FIG. 2, the structural parameters in the planar direction are shown together with the planar structure of the internal cell. As shown in FIG. 2, for example, CD is half the size of the drain contact 3, MCD is the distance from the drain contact 3 to the LOCOS oxide film 5, and LL is the N-type well from the left end of the LOCOS oxide film 5. The distance from the right end of the LOCOS oxide film 5 to the opening end of the N-type well mask, GOX is the width of the gate oxide film 21, and MCS is from the source contact 4. The distance to the gate oxide film 21, CS is half the size of the source contact 4, MPB is the distance from the end of the source contact 4 to the P ⁺ -type layer 16, and WPO is the gate electrode 22 in the drain cell 41. Width.

  Although not shown, the vertical parameters of the structural parameters include the film thickness, diffusion depth, and concentration of the gate oxide film 21. Other input items necessary for creating a model include a density profile (depth) and a mesh size and roughness required for simulation.

  Then, as shown in FIG. 12A, numerical values are input for such structural parameters. For example, 4.0 μm is input to LR and 1.5 μm is input to CD.

  When such structural parameters are directly input to the computer, the coordinates describing the simulation model are all set using the input parameters by a pre-configured program such as the calculation formula shown in FIG. Calculated automatically.

  Thereby, as shown in FIG. 12C, for example, coordinates constituting the drain contact 3, that is, coordinates P1, P3, P18, and P20 in FIG. 2 are specified. After all coordinates necessary for creating the model are calculated in this way, a simulation model is created by TCAD as in the conventional case.

  Next, in consideration of actual LDMOS, the user inputs the number of basic cell models of the internal cell 1 and the peripheral cell 2 created by the above-described method to the computer. In addition, a circuit configuration necessary for performing the surge analysis is input to the computer.

  Here, FIG. 13 shows a configuration example of a circuit when a surge is applied to the LDMOS. As shown in FIG. 13, for example, a 1 μH coil 61, a 150Ω resistor 62, and a 150 pF capacitor 63 are connected in series to the drain electrode terminal 25, and the capacitor 63 is grounded. On the other hand, the source electrode terminal 27 is grounded, and the gate electrode terminal 29 is grounded via a 10 kΩ resistor 64. It is assumed that a surge voltage of 25 kV is applied to the drain electrode 18 and a surge current flows through the drain electrode 18.

  When the user inputs such conditions, the current values flowing in the internal cell 1 and the peripheral cells in this case are calculated by the computer.

  Then, a device design is performed using the simulation result thus obtained, and an LDMOS is formed based on the device design, whereby a semiconductor device is manufactured.

  As described above, in this embodiment, the simulation model is configured by the internal cell 1 and the peripheral cell 2. The drain electrode 18 included in the internal cell 1 and the drain electrode 18 included in the peripheral cell 2 are all connected in parallel, and the drain electrode 18 is electrically connected to the drain electrode terminal 25.

  Further, in the wiring 24 connecting the drain electrode 18 and the drain electrode terminal 25 of the internal cell 1 and in the wiring 24 connecting the drain electrode 18 and the drain electrode terminal 25 of the peripheral cell 2, the first is provided. The drain electrode resistor 31 is disposed. Further, the positions within the wiring 24 connecting the drain electrode 18 and the drain electrode terminal 25 of the internal cell 1 and excluding the inside of the wiring 24a connecting the drain electrode 18 and the drain electrode terminal 25 of the peripheral cell 2. A second drain electrode resistor 32 is arranged at 24b.

  Similarly, in the source electrode 20 and the gate electrode 22, the internal cell 1 and the peripheral cell 2 are electrically connected to the source electrode terminal 27 and the gate electrode terminal 29, and the first source electrode resistor 33 and the second electrode 2 A source electrode resistor 34, a first gate electrode resistor 35, and a second gate electrode resistor 36 are arranged.

  For example, the size of the first drain electrode resistor 31 is set in consideration of the average distance from the peripheral cell to the drain electrode terminal 25 and the pattern occupancy of the electrode wiring, and the second drain electrode The resistance value of the first drain electrode resistor 31 is subtracted from the resistance value in consideration of the average distance from the internal cell to the drain electrode terminal 25 and the pattern occupation ratio of the electrode wiring. The size is set.

  By making the simulation model such a structure, it is possible to reproduce the wiring resistance difference of the electrodes due to the difference in the distance from the electrode (contact surface) to the electrode terminal 44 in the cell in the periphery and the periphery of the LDMOS.

  In this embodiment, surge analysis is performed by TCAD using a simulation model having such a structure.

  As a result, the current bias generated in the LDMOS at the time of surge application such as current bias can be reproduced, and the local breakdown at the time of surge application in the entire LDMOS can be analyzed. That is, according to the present embodiment, the behavior of the entire LDMOS at the time of surge application can be calculated more accurately than in the conventional simulation method.

  Further, in the present embodiment, as described above, after the user inputs the numerical value of the structural parameter to the computer having TCAD, the computer is programmed according to a pre-configured program such as the calculation formula shown in FIG. The coordinates describing the simulation model are automatically calculated from the numerical values of the input structural parameters.

  That is, conventionally, when creating a simulation model, a user inputs, for example, coordinates of points A and B to a computer. On the other hand, in the present embodiment, when the user inputs the distance between AB to the computer, the coordinates of the points A and B are obtained from the distance by a program built in advance by the computer.

  Then, a simulation model is created by the computer from the coordinates calculated by the computer.

  In this way, by calculating the coordinates from the dimensions between the coordinates and creating the simulation model from the calculated coordinates, compared with the case where the coordinates of all points are input to the computer in order to create the simulation model Thus, items to be input to the computer can be reduced.

  This allows you to change the model once simulated to another model and perform the simulation, because there are fewer input items than when inputting the coordinates of all points to the computer. Compared with the case where it does, work efficiency can be improved.

In the simulation model of the present embodiment, the tapered shape at the end of the LOCOS oxide film 5 is a plane or a plane perpendicular to the surface of the N ⁻ type Si layer 11. Further, of the surface of the N ⁻ -type Si layer 11, the boundary surface with the LOCOS oxide film 5 is a plane parallel to or perpendicular to the surface of the N ⁻ -type Si layer 11. Further, the boundary surface of the gate electrode 22 with the LOCOS oxide film 5 is a plane surface or a surface perpendicular to the surface of the N ⁻ -type Si layer 11. That is, in this embodiment, in the simulation model, the shapes of the LOCOS oxide film 5 and the gate electrode 22 are rectangular parallelepiped shapes.

Thus, in the simulation model of the present embodiment, different materials such as the boundary surface 5b between the LOCOS oxide film 5 and the N ⁻ -type Si layer 11 (SOI substrate), the boundary surface 5c between the LOCOS oxide film 5 and the gate electrode 22, and the like. The boundary surface between the constituent parts constituted by is approximated to a plane parallel or perpendicular to the main surface of the SOI substrate.

  Here, in general, power device simulation by TCAD is performed by drawing a lattice-like line on a simulation model, setting an unknown on the point (grid point) where the line intersects, and calculating a variable. Is called. This grid-like line is hereinafter referred to as a mesh.

  FIG. 14A shows an example of a mesh in a simulation model having a tapered structure portion. As shown in FIG. 14A, when the calculation is performed using a simulation model having a structure portion having a complicated shape such as a tapered shape, the shape of the mesh 71 needs to be complicated. This is because, since the coordinates of the mesh 71 are basically described in the xyz orthogonal coordinate system, more coordinates need to be specified when the surface of the structure portion is displaced from the axis and is inclined.

  When calculating by TCAD, the more lines that intersect at one grid point 72, the greater the influence that one point receives from surrounding grid points, and the calculation itself tends not to converge.

  For this reason, when a simulation model having a three-dimensional structure in which the edges and corners of the LOCOS oxide film 5 are complex shapes rather than parallel or perpendicular to the main surface of the SOI substrate is created, the mesh shape used in the calculation is Due to the complexity, the convergence of the calculation is low, and the calculation time may be long, or the calculation itself may not be possible.

  In contrast, in the present embodiment, as described above, for example, a simulation model is obtained by approximating the tapered portion of the LOCOS oxide film 5 to a rectangular parallelepiped. That is, the LOCOS oxide film 5 configured by a plane parallel to the x, y, and z axes is used as a simulation model.

  Thereby, as shown in FIG.14 (b), the shape of the mesh 71 of a simulation model can be made into a simple shape. FIG. 14B is an example of a mesh in the vicinity of the LOCOS oxide film 5 in the simulation model of the present embodiment, and is a view of the hatched region in the internal cell in FIG.

  For this reason, according to the present embodiment, for example, an irregular mesh that causes a decrease in the convergence of the calculation as compared with a case where a simulation model that does not approximate the tapered portion of the LOCOS oxide film 5 to a rectangular parallelepiped is used. The number of can be reduced.

  As a result, according to the present embodiment, for example, compared to the case where a simulation model that does not approximate the tapered shape portion of the LOCOS oxide film 5 to a rectangular parallelepiped is used, the convergence of calculation is increased, and the calculation time is shortened. The calculation itself can be made possible.

(Second Embodiment)
In the first embodiment, the case where an actual LDMOS structure is divided into two types, an internal part and a peripheral part, to create a simulation model of a structure based on the two kinds of structures has been described as an example. As described above, the LDMOS structure can be divided not only into two types but also into more structural parts, and a simulation model based on these structures can be created.

  FIG. 15 shows a simulation model in the present embodiment, and FIG. 16 shows a portion corresponding to the simulation model of FIG. 15 in the planar layout of the LDMOS.

  As shown in FIG. 16, in the planar layout of the LDMOS cell, the cell type can be broadly classified into two types, that is, the inner part and the peripheral part. Further, in the peripheral part 2, the drain corner part where the drain cell 41 is located at the corner. (A broken line area F), a source corner portion where the source cell 42 is located at a corner (broken line area G), and an edge portion (a broken line area C) located in an area excluding the corner portion.

  The drain corner portion is a region where the drain cell 41 is adjacent to the two source cells 42, the source corner portion is a region where the source cell 42 is adjacent to the two drain cells 41, and the edge portion is For example, the drain cell 41 is a region adjacent to three source cells 42.

  Therefore, in the present embodiment, as shown in FIG. 15, the simulation model is configured by an internal cell 1, a drain corner cell 2a, an edge cell 2b, and a source corner cell 2c.

  The drain corner cell 2a is a model of the broken line area F in FIG. 16, and the source corner cell 2c is a model of the broken line area G in FIG. The internal cell 1 and the edge cell 2b are obtained by modeling the same parts as the internal cell 1 and the peripheral cell 2 of the first embodiment.

  The peripheral portion of the LDMOS has a different structure at the corner portion and the edge portion. Therefore, as in the present embodiment, by creating a simulation model having a structure having the inner peripheral cell 1 and the three types of peripheral cells 2a, 2b, and 2c, the LDMOS is compared with the first embodiment. Surge analysis can be performed more accurately.

(Other embodiments)
(1) In each of the above-described embodiments, the case where LDMOS surge analysis is performed has been described as an example. However, the present invention is not limited to surge analysis, and other characteristics evaluation such as withstand voltage calculation can also be performed.

  FIG. 17 shows a circuit configuration diagram when the breakdown voltage calculation is performed. As shown in FIG. 17, the circuit configuration is such that, for example, a DC power supply 66 is connected in series to the drain electrode terminal 25 via a resistor 65 of 10 kΩ, the source electrode terminal 27 is grounded, and the gate electrode terminal 29 is 10 kΩ. In this case, the grounding is made through the resistor 67.

  By inputting such a circuit configuration into a computer and using the simulation model of each of the embodiments described above, it is possible to evaluate the DC breakdown voltage characteristics of the LDMOS.

  (2) In each of the above-described embodiments, the case where the type of the internal cell 1 is one type in the structure of the simulation model has been described as an example. However, two or more types of the internal cell 1 can be used.

  For example, the type of the internal cell 1 can be set to two types of a cell located in the center and a cell located on the peripheral side among the plurality of internal cells 1 in the planar layout of the cells in the actual LDMOS. .

  Thereby, it is possible to reproduce the magnitude of the wiring resistance of the electrode in the actual LDMOS between the cell located in the center and the cell located on the peripheral side.

(3) In the above-described embodiment, the LDMOS has been described as an example. However, the present invention also applies to an IGBT in which the N ⁺ -type Si layer 47 of the MOS is replaced with a P ⁺ -type Si layer, the source is the emitter, and the drain is the collector. Can be applied. The present invention can also be applied to the case where a characteristic simulation is performed on a power device such as a diode, thyristor, triac, or GTO thyristor.

  (4) In the above-described embodiment, the case where the simulation model has a three-dimensional structure has been described as an example. However, the simulation model can also have a two-dimensional structure. Even when the simulation model has a two-dimensional structure, the same effects as those of the above-described embodiments can be obtained.

  Since the actual power device to be simulated has a three-dimensional structure, the structure of the simulation model is preferably a three-dimensional structure rather than a two-dimensional structure.

It is a figure which shows the simulation model used for the characteristic simulation in 1st Embodiment of this invention. It is a top view of the internal cell 1 in FIG. It is a figure which shows the cross-section of the internal cell 1 in FIG. It is a figure which shows the cross-section of the peripheral part cell 2 in FIG. It is a top view of LDMOS which is a simulation object. FIG. 6 is a cross-sectional view of the LDMOS of FIG. 5 taken along the line A-A ′. It is a figure which shows the planar layout of the cell in LDMOS of FIG. It is a figure which shows the planar pattern of PolySi which comprises the gate electrode 22 of LDMOS of FIG. FIG. 6 is a diagram showing a planar pattern of 1st Al wiring constituting the drain electrode 18, the source electrode 20 and the electrode terminal 44 of the LDMOS of FIG. FIG. 6 is a diagram showing a planar layout of vias constituting the electrode terminal 44, the drain electrode 18 and the source electrode 20 of the LDMOS of FIG. FIG. 6 is a diagram showing a planar pattern of 2nd Al wiring constituting the drain electrode 18, the source electrode 20 and the electrode terminal 44 of the LDMOS of FIG. (A) is a figure which shows the example of numerical input setting of a structural parameter, (b) is a figure which shows the example of conversion from a structural parameter to a coordinate variable, (c) is a figure which shows the example of an electrode definition by a coordinate variable It is. It is a figure which shows the circuit structure in the case of applying a surge with respect to LDMOS. (A) is a figure which shows an example of the mesh formed in the simulation model which has a taper-shaped structure part, (b) is a figure which shows an example of the mesh formed in the simulation model of FIG. It is a figure which shows the simulation model used for the characteristic simulation in 2nd Embodiment of this invention. It is a figure which shows the correspondence of the simulation model of FIG. 15, and LDMOS of FIG. It is a figure which shows the circuit structure in the case of simulating the DC proof pressure characteristic of LDMOS.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Internal cell, 2 ... Peripheral cell, 3 ... Drain contact, 4 ... Source contact,
5 ... LOCOS oxide film, 6 ... gate oxide film, 12 ... N-type well layer,
14 ... P-type well layer, 16 ... P ⁺ type layer, 22 ... Gate electrode,
24, 26, 28 ... wiring, 25 ... drain electrode terminal,
27 ... Source electrode terminal, 29 ... Gate electrode terminal,
31... First drain electrode resistance, 32... Second drain electrode resistance,
33... First source electrode resistance, 34... Second source electrode resistance,
35... First gate electrode resistor, 36... Second gate electrode resistor.

Claims (7)

A first cell (1) having a first electrode (3, 4, 22);
A second cell (2, 2a, 2b, 2c) having a second electrode (3, 4, 22) electrically connected in parallel with the first electrode (3, 4, 22);
Electrode terminals (25, 27) electrically connected to both the first electrode (3, 4, 22) and the second electrode (3, 4, 22) by wiring (24, 26, 28). 29)
In the wiring (24, 26, 28) connecting the first electrode (3, 4, 22) and the electrode terminal (25, 27, 29), and in the second electrode (3 4, 22) and the first resistor (31, 33, 35) disposed in the wiring (24a, 26a, 28a) connecting the electrode terminal (25, 27, 29);
In the wiring (24, 26, 28) connecting the first electrode (3, 4, 22) and the electrode terminal (25, 27, 29), the second electrode (3, 4, 22) and the electrode terminals (25, 27, 29) and the second resistors (32, 28b, 28b) disposed at positions (24b, 26b, 28b) excluding the inside of the wirings (24a, 26a, 28a). 34, 36), and a semiconductor device characteristic simulation method characterized by simulating the characteristic of the semiconductor device. The first cell (1) is a model of a cell located inside a planar layout in which a plurality of cells are arranged, and the second cell (2, 2a, 2b, 2c) , A model of a cell located around the inner cell in the planar layout,
2. The semiconductor device characteristic simulation method according to claim 1, wherein a resistance value of the second resistor (32, 34, 36) is larger than a resistance value of the first resistor (31, 33, 35). . The simulation model is created by the computer by the computer calculating based on a plurality of coordinates,
The predetermined size is input to the computer, the plurality of coordinates are calculated based on the size by the computer, and the simulation model is created. Semiconductor device characteristic simulation method. The first and second cells (1, 2, 2a, 2b, 2c) are models of cells composed of a plurality of components including a semiconductor substrate,
Of the plurality of components, the boundary surfaces (5a, 5b, 5c) between the components (5, 11, 22) made of different materials are parallel to the main surface of the semiconductor substrate (17). 4. The semiconductor device characteristic simulation method according to claim 1, wherein the method is approximated to a vertical plane. 5. The semiconductor device characteristic simulation method according to claim 1, wherein the first and second cells (1, 2, 2a, 2b, 2c) have a three-dimensional structure. A device structure design method for a semiconductor device, which is performed using a simulation result obtained by the method for simulating a characteristic of a semiconductor device according to any one of claims 1 to 5. 6. A semiconductor device characterized in that device design is performed using a simulation result of the semiconductor device characteristic simulation method according to claim 1, and a semiconductor element is formed based on the device design. Production method.

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