JP2005301665A - Data processor and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DMA system with arithmetic processing for processing data in an arbitrary data format without being restricted by the input/output format of the arithmetic processing. <P>SOLUTION: This data processor 1 is provided with: a DMA device 11 for input for DMA-transferring processing object data from a memory 22; an input register 12 for temporarily storing the processing object data transferred from the DMA device 11 for input; and an arithmetic processing part 15 for operating the arithmetic processing of the processing object data stored in the input register 12. The processing object data in the input register 12 are rearranged according to the input format of the arithmetic processing part 15 by a format converting part 14 according to a pickup table stored in a pickup table part 13 for input, and inputted to the arithmetic processing part 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data processing device and a data processing method in the data processing device.

As a method for transferring data inside the apparatus, a DMA (Direct Memory Access) method is known. There is also known a DMA system with arithmetic processing that performs arithmetic processing when data is transferred from a memory by the DMA system (see, for example, Patent Document 1).
JP-A-7-79353

Hereinafter, a conventional DMA system with arithmetic processing will be described with reference to FIGS.
A data processing device 3 shown in FIG. 8 is an example of a device that transfers data using a conventional DMA system with arithmetic processing. Output.

  The processing execution unit 30a of the processing unit 30 performs arithmetic processing on the processing target data Ain, Bin, Cin, Din input from the input interface 30b, and outputs Aout, Bout, Cout, Dout. The processing unit 30 includes an input interface 30b to which processing target data Ain, Bin, Cin, and Din are input, and an output interface 30c that outputs output data Aout, Bout, Cout, and Dout generated by the processing of the processing execution unit 30a. Is provided.

In the input memory area 31, processing target data corresponding to a plurality of times of processing by the processing execution unit 30a is stored, and the processing target data for the plurality of times are all in accordance with the input format in the input interface 30b, Ain, A set of four data sets in the order of Bin, Cin, and Din.
Further, in the output memory area 32, all the data output by the processing executed by the processing execution unit 30a is stored in the format output from the output interface 30c, that is, in the order of Aout, Bout, Cout, and Dout. Is done.

  That is, the data format in the input memory area 31 and the output memory area 32 is compatible with the input / output format of the processing unit 30. When the format of the processing target data in the input memory area 31 is different from the input format of the processing unit 30, a process of converting the format as shown in FIG. 9 is necessary.

In the input memory area 31 shown in FIG. 9, the processing object data Ain [0], Bin [0], Cin [0], Din [0],. 0], Din [0], Ain [0], Cin [0], and so on.
In this case, the processing target data once stored in the input memory area 31 is rearranged according to the input format of the input interface 30b, and the rearranged data is sequentially output from the input memory area 31 to the input interface 30b. It was.

  As described above, in the conventional DMA system with arithmetic processing, the format of the processing target data needs to be matched with the input format of the processing unit that executes arithmetic processing in advance. The output data output by the arithmetic processing by the processing unit is stored in the memory area according to the output format. That is, there is a problem that the format of the processing target data and the output data is restricted by the input / output format in the processing unit 30.

  In addition, when data in a format different from the input format in the processing unit 30 is transferred and processed, it is necessary to perform processing such as converting the data format in advance, and the processing load increases and high-speed data transfer is performed. There was a problem that it might interfere.

  Therefore, an object of the present invention is to enable processing of data in an arbitrary data format without being limited to the input / output format of arithmetic processing in the DMA system with arithmetic processing.

  In order to achieve the above object, the present invention has the following features. In the following description, a configuration corresponding to the embodiment is shown as an example in parentheses. Reference numerals and the like are reference numerals for drawings to be described later.

  The data processing apparatus according to the present invention includes an arithmetic processing unit (for example, the arithmetic processing unit 15) that performs arithmetic processing on processing target data, and a processing target data transfer unit (for example, a DMA transfer of processing target data in a memory (for example, the memory 22)). For example, from the input DMA device 11), the first storage means (for example, the input register 12) for temporarily storing the processing target data transferred by the processing target data transfer means, and the first storage means , Input format conversion means for reading at least processing target data required for one processing by the arithmetic processing means, and inputting the read processing target data to the arithmetic processing means in a state suitable for the input format of the arithmetic processing means ( For example, a format conversion unit 14) is provided.

  The present invention further comprises setting table holding means (for example, an input pickup table section 13) for holding a setting table for determining the arrangement order of the processing target data stored in the first storage means. The conversion unit may arrange the processing target data stored in the first storage unit according to the arrangement order defined in the setting table held by the setting table holding unit, and input the data to the arithmetic processing unit. .

  In the present invention, the setting table held in the setting table holding unit includes a plurality of specific data among a plurality of data stored in the first storage unit and an arrangement of the specific plurality of data. The input format conversion means refers to the setting table held in the setting table holding means, and the first storage means stores a plurality of specific data set in the setting table. It is good also as a structure which reads out from and arranges according to the arrangement | sequence order defined in the said setting table, and inputs into the said arithmetic processing means.

  In the present invention, the output data output from the arithmetic processing means is arranged in accordance with a predetermined format. For example, the output format conversion means (for example, the format conversion section 17) and the output data arranged by the output format conversion means are temporarily stored. Second storage means (for example, output register 18) for storing the output data, and output data transfer means (for example, output DMA device 19) for DMA-transferring the output data stored in the second storage means to the memory It is good also as a structure further equipped with these.

  Further, the data processing method of the present invention is a data processing method in which processing target data in a memory (for example, the memory 22) is DMA-transferred and arithmetic processing is performed by an arithmetic processing means (for example, the arithmetic processing unit 15). Data to be processed transferred from the memory is temporarily stored in a first storage means (for example, the input register 12), and is necessary for at least one process by the arithmetic processing means from the first storage means. The processing target data is read out, and the read processing target data is input to the arithmetic processing unit in a state suitable for the input format of the arithmetic processing unit.

  According to the present invention, when the processing target data in the memory is DMA-transferred by the processing target data transfer unit, and the processing target data is arithmetically processed by the arithmetic processing unit, the processing target data transferred by the transfer unit is the first data Temporarily stored in the storage means, the input format conversion means reads from the first storage means at least processing target data necessary for the processing by the arithmetic processing means, and the read processing target data is input to the arithmetic processing means. Since the data is input to the arithmetic processing means in conformity with the format, the arithmetic processing means is suitable for the input format of the arithmetic processing means regardless of the format of the data to be processed that is DMA-transferred from the memory. Processed data is input. This makes it possible to execute DMA transfer with arithmetic processing on data in various formats regardless of the input format of arithmetic processing.

  In the present invention, the setting table for determining the arrangement order of the processing target data stored in the first storage means is held by the setting table holding means, and the input format conversion means is the process stored in the first storage means. When the target data is arranged according to the arrangement order defined in the setting table held by the setting table holding means and is input to the arithmetic processing means, the input format conversion means refers to the setting table and stores the first memory The processing target data stored in the means may be read and arranged. Therefore, it is possible to deal with data in various formats by simply holding a setting table that matches the format of the processing target data transferred from the memory and the input format of the arithmetic processing means. Furthermore, the processing load is small and processing can be performed at a very high speed compared to the case where processing such as batch conversion of the format of all data to be processed is performed, so that various processing can be performed without impairing the DMA transfer processing speed. Can process data in various formats.

  In the present invention, the setting table held in the setting table holding unit determines a plurality of specific data among the plurality of data stored in the first storage unit and the arrangement order of the plurality of data. The input format conversion means refers to the setting table held in the setting table holding means, reads a plurality of specific data defined in the setting table from the first storage means, and sets the setting table. When the input format conversion unit reads the specific data stored in the first storage unit and rearranges it, the input data is converted to the first storage unit. Whether the data stored in the means is read once or when one piece of data is read multiple times, the time and procedure required for the process do not change at all. . That is, when a plurality of data having the same contents are processed by the arithmetic processing means, only one piece of the data is stored in the first storage means, and the data is read out a plurality of times by the input format conversion means. If so, the amount of data to be stored in the first storage means can be compressed. As a result, it is possible to compress the amount of data without any loss in processing speed.

  In the present invention, the output data output from the arithmetic processing means is arranged in accordance with a predetermined format by the output format conversion means, the arranged output data is temporarily stored in the second storage means, and the second storage When the output data stored in the means is DMA-transferred to the memory by the output data transfer means, the output data output after the processing by the arithmetic processing means is rearranged into a format different from the output format of the arithmetic processing means. Since the data can be transferred to the memory, the output data can be obtained in various formats.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a functional configuration of a data processing device 1 according to an embodiment of the present invention. As shown in FIG. 1, the data processing apparatus 1 includes a sequence control unit 10, an input DMA device 11, an input register 12, an input pickup table unit 13, a format conversion unit 14, an arithmetic processing unit 15, and an output pickup table unit 16. , A format conversion unit 17, an output register 18, and an output DMA device 19.
Each unit of the sequence control unit 10, the input DMA device 11, and the output DMA device 19 of the data processing device 1 is connected to the bus 20, and is connected to a CPU (Central Processing Unit) 21 and a memory 22 via the bus 20. Send and receive data between them.

  The sequence control unit 10 controls each unit of the data processing device 1 in accordance with a control signal input from the CPU 21. That is, the sequence control unit 10 controls the input DMA device 11 and the output DMA device 19 to transfer data to and from the memory 22 by the DMA method. Further, the sequence control unit 10 controls the input pickup table unit 13 and the output pickup table unit 16 to reset a counter for selecting the pickup table.

The input DMA device 11 reads processing target data from the memory 22 via the bus 20 and stores it in the input register 12 under the control of the sequence control unit 10.
The input register 12 is a buffer memory that temporarily stores processing target data input from the input DMA device 11.

The input pickup table unit 13 stores a plurality of pickup tables referred to by the format conversion unit 14. The input pickup table unit 13 includes a counter (not shown) for selecting a stored pickup table, and increments (+1) the counter every time the pickup table is referred to by the format conversion unit 14.
The format conversion unit 14 refers to the pickup table stored in the input pickup table unit 13 based on the count value of a counter (not shown) in the input pickup table unit 13, and in the input register 12 according to the pickup table. The processing target data is read out and output to the arithmetic processing unit 15.

The arithmetic processing unit 15 performs arithmetic processing on the processing target data input from the format conversion unit 14 to generate output data, and outputs the output data to the format conversion unit 17.
The output pickup table unit 16 stores a plurality of pickup tables referred to by the format conversion unit 17. The output pickup table unit 16 includes a counter (not shown) for selecting the stored pickup table, and increments (+1) the counter each time the pickup table is referred to by the format conversion unit 17.
The format conversion unit 17 refers to the pickup table stored in the output pickup table unit 16 based on the count value of a counter (not shown) in the output pickup table unit 16, and operates in accordance with this pickup table. The output data output from 15 is output to the output register 18.

The output register 18 is a buffer memory that temporarily stores output data input from the format conversion unit 17.
The output DMA device 19 reads the output data stored in the output register 18 under the control of the sequence control unit 10 and outputs it to the memory 22 via the bus 20.

FIG. 2 is a diagram schematically illustrating a configuration example of a pickup table stored in the input pickup table unit 13.
As shown in FIG. 2, a plurality of tables are stored in the input pickup table unit 13, and a pickup index for identifying each pickup table is attached.

  Each pickup table stores addresses in the input register 12 in a predetermined order. For example, “Pickup table 0” in FIG. 2 stores X addresses “P00”, “P01”,..., “P0x”. These addresses indicate addresses where processing target data is stored in the input register 12. Further, the order of the addresses “P00”, “P01”,..., “P0x” in the pickup table indicates the order for arranging the processing target data of each address according to the input format of the arithmetic processing unit 15. Therefore, the format conversion unit 14 sequentially reads out the processing target data stored at the addresses “P00”, “P01”,..., “P0x” of the “pickup table 0” from the input register 12 and stores them in the “pickup table 0”. By arranging according to the order, the format of the processing target data can be adapted to the input format of the arithmetic processing unit 15.

As described above, the input pickup table unit 13 includes a counter (not shown). When referring to the pickup table in the input pickup table unit 13, the format conversion unit 14 selects the pickup table based on the count value of the counter. For example, when the count value is “0”, the format conversion unit 14 refers to “pickup table 0” in the input pickup table unit 13, and when the count value is “1”, the format conversion unit 14 selects “pickup table”. Refer to “Table 1”.
Accordingly, the plurality of pickup tables stored in the input pickup table unit 13 are referred to in order as the process proceeds.

  2 shows an example of the configuration of the pickup table stored in the input pickup table unit 13, the configuration of the pickup table stored in the output pickup table unit 16 is the same. In other words, in the pickup table stored in the output pickup table unit 16, addresses where output data is stored in the output register 18 are stored in a predetermined order. The format conversion unit 17 acquires the address in the output register 18 by referring to the pickup table in the output pickup table unit 16, and sequentially stores the output data at the acquired address. Thereby, the data format in the output register 18 can be changed to an arbitrary format regardless of the output format of the arithmetic processing unit 15.

FIG. 3 is a flowchart showing the operation of processing data in the data processing apparatus 1 by the DMA system with arithmetic processing. FIG. 4 is a diagram illustrating processing of a plurality of processing target data stored in the memory 22 by the data processing apparatus 1.
The memory area 22a is an area for storing processing target data to be processed by the arithmetic processing unit 15, and in the example shown in FIG. 4, n processing target data scr_1, scr_2,..., Scr_n are stored. . In addition, the memory area 22b is an area for storing output data generated by the arithmetic processing unit 15, and in the example shown in FIG. 4, n output data dst_1, dst_2,..., Dst_n are stored.

Hereinafter, the operation of the data processing apparatus 1 will be described with reference to FIGS. 3 and 4.
First, the sequence control unit 10 updates the status indicating the operation state of the data processing apparatus 1 to “in operation” (step S11 in FIG. 3). Subsequently, the sequence control unit 10 controls the input DMA device 11 to perform DMA transfer of processing target data for one processing unit (step S12).

  Here, the input DMA device 11 reads out processing target data for one processing unit, that is, scr_1 (FIG. 4) in the memory area 22a via the bus 20 (FIG. 1) and stores it in the input register 12. (Step S13 in FIG. 3).

  Subsequently, the sequence control unit 10 controls the input pickup table unit 13 and the output pickup table unit 16, and among the plurality of pickup tables stored in the input pickup table unit 13 and the output pickup table unit 16. The counter for selecting the pickup table from the reset is reset (step S14).

Here, the format conversion unit 14 refers to the pickup table in the input pickup table unit 13 according to the count value of a counter (not shown) in the input pickup table unit 13, and from the input register 12 in accordance with this pickup table. Data to be processed is read out and input to the arithmetic processing unit 15 (step S15).
The arithmetic processing unit 15 performs arithmetic processing based on the processing target data input from the format conversion unit 14, generates output data, and outputs the output data to the format conversion unit 17 (step S16).

  When the processing by the arithmetic processing unit 15 is finished, the format conversion unit 17 refers to the pickup table stored in the output pickup table unit 16 according to the count value of the counter (not shown) in the output pickup table unit 16, According to this pickup table, the output data output from the arithmetic processing unit 15 is stored in the output register 18 (step S17).

  Further, the input pickup table unit 13 and the output pickup table unit 16 increment (+1) the count value of the built-in counter (step S18).

The sequence control unit 10 determines whether or not the count values of the counters in the input pickup table unit 13 and the output pickup table unit 16 have reached specified values specified in advance (step S19).
Here, the specified value is a value indicating whether or not all of the scr_1 read from the memory area 22a (FIG. 4) by the input DMA device 11 and stored in the input register 12 has been processed. It is. For example, when the processing target data scr_1 includes data exceeding the amount that can be processed at one time by the arithmetic processing unit 15, in order to process all the processing target data scr_1 in the input register 12, the arithmetic processing unit 15 Needs to be processed once. In this case, if the number of processes to be executed by the arithmetic processing unit 15 is obtained in advance and the number is set as a specified value, all the processing target data in the input register 12 can be reliably processed.

  If the count values of the counters in the input pickup table unit 13 and the output pickup table unit 16 have not reached the specified values (step S19 in FIG. 3; No), the operation of the data processing device 1 returns to step S15.

  When the count values of the counters in the input pickup table unit 13 and the output pickup table unit 16 reach the specified values (step S19; Yes), the sequence control unit 10 controls the output DMA device 19 to The output data for one processing unit stored in the output register 18 is DMA-transferred to the memory 22 (FIG. 1) and stored as dst_1 in the memory area 22b (FIG. 4) (step S20 in FIG. 3).

  Thereafter, the sequence control unit 10 determines whether or not all the processes are completed according to the control signal input from the CPU 21 via the bus 20 (FIG. 1) (step S21). The state in which all the processes are completed means that all the n processing target data scr_1, scr_2,..., Scr_n in the memory area 22a shown in FIG. This refers to the state where the output data dst_1, dst_2,..., Dst_n are stored.

  In step S21 of FIG. 3, if the processing by the data processing device 1 is not completed, the operation of the data processing device 1 returns to step S11 to process the next processing target data stored in the memory area 22a (FIG. 4). To do. When the process is completed (step S21 in FIG. 3; Yes), the sequence control unit 10 updates the status indicating the operation state of the data processing apparatus 1 to “idle state” (step S22), and performs this process. finish.

  FIG. 5 is an explanatory diagram illustrating a specific configuration example of the pickup table stored in the input pickup table unit 13 and the output pickup table unit 16 and processing based on the pickup table.

  In FIG. 5, the sequence controller 10, the input DMA device 11, the output DMA device 19, the bus 20, the CPU 21, and the memory 22 are not shown. For the input pickup table unit 13 and the output pickup table unit 16, only the pickup tables 13a and 16a stored therein are shown.

The arithmetic processing unit 15 is a process execution unit 15a that executes arithmetic processing, an input interface 15b that receives input of information processed by the process execution unit 15a, and an output that outputs data generated by the processing performed by the process execution unit 15a. And an interface 15c.
Hereinafter, subscripts [0] to [3] indicating the order of processing and generation by the processing execution unit 15a are attached to the processing target data and the output data.

In the example shown in FIG. 5, the arithmetic processing unit 15 executes arithmetic processing based on four processing target data of Ain, Bin, Cin, and Din, and outputs output data Aout, Bout, Cout, and Dout.
In the input register 12, No. Corresponding to 16 addresses from 0 to F, processing target data Bin [0], Din [0], Ain [0], Cin [0], ..., Bin [3], Din [3], Ain [3] , Cin [3] is stored. These 16 pieces of data to be processed are processed by four calculation processes by the calculation processing unit 15.

  In the pickup table 13a, 16 data in the input register 12 are arranged in the order of Ain, Bin, Cin, and Din in accordance with the input format of the arithmetic processing unit 15, so that the data arrangement order, the address in the input register 12, and Are stored in association with each other.

  The format conversion unit 14 first refers to the data 2, 0, 3, 1 indicating the processing target data address to be processed first in the pickup table 13a, and stores the data at addresses 2, 0, 3, 1 of the input register 12. The processed data Ain [0], Bin [0], Cin [0], and Din [0] are read. Thereby, the processing target data Bin [0], Din [0], Ain [0], and Cin [0] in the input register 12 are matched with the input format of the input interface 15b by Ain [0] and Bin [0]. , Cin [0], Din [0] are arranged in this order and are input to the processing execution unit 15a of the arithmetic processing unit 15.

When the processing by the processing execution unit 15a is executed based on the data Ain [0], Bin [0], Cin [0], Din [0] input to the input interface 15b, the output interface 15c Output data Aout [0], Bout [0], Cout [0], and Dout [0] by the first processing are output.
The format converter 17 refers to the pickup table 16a, and addresses 0, 1, and 2 in the output register 18 where the first output data Aout [0], Bout [0], Cout [0], and Dout [0] are to be stored. 2 and 3 are acquired, and Aout [0], Bout [0], Cout [0], and Dout [0] are stored in the addresses 0, 1, 2, and 3, respectively.

  Thereafter, similarly, the processing target data Bin [1], Din [1], Ain [1], Cin [1], ..., Bin [3], Din [3], Ain [3], in the input register 12 Cin [3] is arranged in accordance with the input format of the input interface 15b by the format conversion unit 14, processed by the arithmetic processing unit 15, and output data Aout [1], Bout [1], Cout [1], Dout [1],..., Aout [3], Bout [3], Cout [3], Dout [3] are stored in the output register 18 in a format determined by the pickup table 16a.

As described above, in the data processing device 1 according to the embodiment to which the present invention is applied, the processing target data transferred from the memory 22 to the input register 12 by the DMA transfer is processed by the arithmetic processing unit 15, and the output after processing is performed. In a series of operations in which data is stored in the output register 18, the format conversion unit 14 arranges the processing target data stored in the input register 12 in the order based on the pickup table in the input pickup table unit 13. The data is input to the arithmetic processing unit 15 in a state compatible with the input format of the processing unit 15.
Thereby, even if the format of the processing target data stored in the input register 12 is different from the input format of the arithmetic processing unit 15, it can be processed quickly, so that data of various data formats can be processed efficiently and at high speed.

  Further, since the pickup table stored in the input pickup table unit 13 specifies an address in the input register 12, the processing target data in the input register 12 can be specified in detail. Thus, when the same data is used in a plurality of processes by the arithmetic processing unit 15, only one piece of the data is stored in the input register 12, and the address of the data is designated in a plurality of pickup tables. For example, every time the data is processed by the format conversion unit 14, the data is read from the input register 12 and input to the arithmetic processing unit 15. Therefore, it is not necessary to store a plurality of identical data in the input register 12, and only one of the plurality of data can be stored. Therefore, the data amount of the input register 12 can be compressed. Further, the process of reading one data in the input register 12 a plurality of times is performed in exactly the same procedure as the process of reading a plurality of data once, so that there is an advantage that the data amount can be compressed without impairing the processing speed. .

  Further, the output data generated by the processing of the arithmetic processing unit 15 is also stored in the output register 18 by the format conversion unit 17 according to the pickup table regardless of the output format from the arithmetic processing unit 15. For this reason, the format of the data output after the arithmetic processing can be changed to an arbitrary format.

  As described above, the data processing apparatus 1 has an advantage that it can easily cope with various data formats, and can process data of any format efficiently and at high speed.

  In the above embodiment, the capacity of the memory areas 22a and 22b shown in FIG. 4 and the size of the data scr_1,..., Scr_n, dst_1, ..., dst_n stored in the memory areas 22a and 22b are arbitrarily changed. Is possible. Also, the data scr_1,..., Scr_n stored in the memory area 22a may be divided and processed multiple times. Furthermore, the input register 12 and the output register 18 can be implemented as one memory. In this case, the pickup tables stored in the input pickup table unit 13 and the output pickup table unit 16 store addresses in the same memory. Note that the address stored in the pickup table can be reduced by offsetting the address of the input register 12 or the address of the output register 18.

  Here, as a more specific example of the data processing apparatus 1 in the above embodiment, a case where the present invention is applied to video conversion processing for converting a video signal in YUV format into RGB format will be described as an example.

  FIG. 6 is a diagram showing a case where the data conversion apparatus 1 to which the present invention is applied executes a video conversion process for converting a YUV video signal into an RGB signal. In FIG. 6, the CPU 21 and the memory 22 are not shown.

In the example shown in FIG. 6, the data processing apparatus 1 executes processing for converting data in YUV444 (YUV4: 4: 4) format into data in RGB format.
In this process, RGB data for one pixel is obtained based on three data of Y (luminance signal), U (difference between luminance signal and red component), and V (difference between luminance signal and blue component) in the YUV444 format. Generate.
The arithmetic processing unit 15 performs arithmetic processing based on the three data of Y, U, and V to generate R, G, and B data, an YUV-RGB conversion processing unit 15d, an input interface 15e, and an output An interface 15f is provided.

In the first embodiment, a procedure for generating RGB data for four pixels from twelve pieces of Y, U, and V data will be described as an example.
The input register 12 stores 12 pieces of Y, U, V data in the order of U, V, Y according to the YUV format. On the other hand, the input format of the input interface 15e of the arithmetic processing unit 15 is such that data is arranged in the order of Y, U, and V.

Procedure 1. The sequence control unit 10 controls the input DMA device 11 to transfer 12 pieces of processing target data from the memory 22 (not shown) storing the processing target data to the input register 12.
Procedure 2. The format conversion unit 14 refers to the TBL0 in the pickup table 13b in the input pickup table unit 13 to obtain the addresses S1, S0, and S2 of each processing target data of Y, U, and V to be processed first. Data to be processed Y0, U0, V0 in the input register 12 is read according to the address and input to the input interface 15e.
Procedure 3. The YUV-RGB conversion processing unit 15d executes YUV → RGB conversion processing, generates output data R0, G0, and B0 and outputs them from the output interface 15f.
Procedure 4. The format conversion unit 17 refers to the TBL0 in the pickup table 16b in the output pickup table unit 16 to obtain the addresses D0, D1, and D2 of the R, G, and B output data that are output first, and this address Accordingly, the output data R0, G0, B0 output from the output interface 15f is stored in the output register 18.

Procedure 5. The format conversion unit 14 refers to the TBL1 in the pickup table 13b in the input pickup table unit 13 and acquires the addresses S4, S3, and S5 of the processing target data, and the processing target data Y1, in the input register 12 according to this address U1 and V1 are read out and input to the input interface 15e.
Procedure 6. The YUV-RGB conversion processing unit 15d executes YUV → RGB conversion processing, generates output data R1, G1, and B1 and outputs them from the output interface 15f.
Step 7. The format conversion unit 17 refers to the TBL1 in the pickup table 16b in the output pickup table unit 16 to obtain output data addresses D3, D4, and D5, and the output data R1 output from the output interface 15f according to this address. , G1, B1 are stored in the output register 18.

Procedure 8. The format conversion unit 14 refers to the TBL2 in the pickup table 13b in the input pickup table unit 13, acquires the addresses S7, S6, and S8 of the processing target data, and processes the processing target data Y2 in the input register 12 according to this address. , U2, V2 are read out and input to the input interface 15e.
Procedure 9. The YUV-RGB conversion processing unit 15d executes YUV → RGB conversion processing, generates output data R2, G2, and B2 and outputs them from the output interface 15f.
Procedure 10. The format conversion unit 17 refers to the TBL2 in the pickup table 16b in the output pickup table unit 16, acquires the output data addresses D6, D7, and D8, and outputs the output data output from the output interface 15f according to the addresses. R2, G2, and B2 are stored in the output register 18.

Procedure 11. The format conversion unit 14 refers to the TBL3 in the pickup table 13b in the input pickup table unit 13 to obtain the addresses S10, S9, and S11 of the processing target data, and the processing target data Y3 in the input register 12 according to this address. , U3, V3 are read out and input to the input interface 15e.
Procedure 12. YUV-RGB conversion processing is executed by the YUV-RGB conversion processing unit 15d, and output data R3, G3, B3 are generated and output from the output interface 15f.
Procedure 13. The format conversion unit 17 refers to the TBL3 in the pickup table 16b in the output pickup table unit 16 to obtain the output data addresses D9, D10, D11, and the output data output from the output interface 15f according to this address R3, G3, and B3 are stored in the output register 18.

Procedure 14. Under the control of the sequence control unit 10, the output data stored in the output register 18 is DMA-transferred to the memory 22 (not shown) by the output DMA device 19.
Procedure 15. The processes of steps 1 to 14 are repeatedly executed until all the processing target data in the memory 22 (not shown) is processed.

  As described above, in the first embodiment, the format conversion unit 14 converts the processing target data in the YUV format in which data is arranged in the order of U, Y, and V into a format in which the data is arranged in the order of Y, U, and V. Since the data is input to the arithmetic processing unit 15, YUV format data can be processed at high speed, and RGB format video data can be obtained.

  Further, since the processing target data arranged in the order of U, Y, V in the YUV format is rearranged in the order of Y, U, V, which is the input format of the input interface 15e, by the format conversion unit 14, all the processing target data is preliminarily arranged. It is not necessary to convert the data. Therefore, the input DMA device 11 may transfer the data in the YUV format as it is from the memory 22 (not shown) to the input register 12. Thereby, data can be processed without impairing the DMA transfer speed.

  FIG. 7 is a diagram showing a case where a video conversion process for converting a YUV video signal into an RGB signal is executed in the data processing apparatus 1 to which the present invention is applied, and a process for converting data in the YUV422 format into RGB format data. Indicates. In FIG. 7, the CPU 21 and the memory 22 are not shown.

  When converting data in YUV422 (YUV4: 2: 2) format to RGB format, RGB data of 2 pixels is generated from four data of Y × 2, U × 1, and V × 1. That is, the process of generating RGB data of one pixel using one U data and V data is executed twice, so that the U data and V data are used twice.

  In the second embodiment, a procedure for generating RGB data for four pixels from eight pieces of Y, U, and V data will be described as an example.

Procedure 1. The sequence control unit 10 controls the input DMA device 11 to transfer eight processing target data from the memory 22 (not shown) storing the processing target data to the input register 12.
Procedure 2. The format conversion unit 14 refers to the TBL0 in the pickup table 13c in the input pickup table unit 13 to obtain the addresses S1, S0, and S2 of each processing target data of Y, U, and V to be processed first. Data to be processed Y0, U0, V0 in the input register 12 is read according to the address and input to the input interface 15e.
Procedure 3. The YUV-RGB conversion processing unit 15d executes YUV → RGB conversion processing, generates output data R0, G0, and B0 and outputs them from the output interface 15f.
Procedure 4. The format conversion unit 17 refers to the TBL0 in the pickup table 16c in the output pickup table unit 16 to obtain the addresses D0, D1, and D2 of the R, G, and B output data that are output first, and this address Accordingly, the output data R0, G0, B0 output from the output interface 15f is stored in the output register 18.

Procedure 5. The format conversion unit 14 refers to the TBL1 in the pickup table 13c in the input pickup table unit 13 to obtain the addresses S3, S0, and S2 of the processing target data, and the processing target data Y1, in the input register 12 according to this address U0 and V0 are read out and input to the input interface 15e.
Procedure 6. The YUV-RGB conversion processing unit 15d executes YUV → RGB conversion processing, generates output data R1, G1, and B1 and outputs them from the output interface 15f.
Step 7. The format conversion unit 17 refers to the TBL1 in the pickup table 16c in the output pickup table unit 16 to obtain output data addresses D3, D4, and D5, and the output data R1 output from the output interface 15f according to this address. , G1, B1 are stored in the output register 18.

Procedure 8. The format conversion unit 14 refers to the TBL2 in the pickup table 13c in the input pickup table unit 13, and addresses S5, S4. S6 is acquired, and the processing target data Y2, U2, and V2 in the input register 12 are read according to this address and input to the input interface 15e.
Procedure 9. The YUV-RGB conversion processing unit 15d executes YUV → RGB conversion processing, generates output data R2, G2, and B2 and outputs them from the output interface 15f.
Procedure 10. The format conversion unit 17 refers to the TBL2 in the pickup table 16c in the output pickup table unit 16, acquires the output data addresses D6, D7, and D8, and outputs the output data output from the output interface 15f according to the addresses. R2, G2, and B2 are stored in the output register 18.

Procedure 11. The format conversion unit 14 refers to the TBL3 in the pickup table 13c in the input pickup table unit 13 to obtain the addresses S7, S4, and S6 of the processing target data, and the processing target data Y3 in the input register 12 according to this address , U2, V2 are read out and input to the input interface 15e.
Procedure 12. YUV-RGB conversion processing is executed by the YUV-RGB conversion processing unit 15d, and output data R3, G3, B3 are generated and output from the output interface 15f.
Procedure 13. The format conversion unit 17 refers to the TBL3 in the pickup table 16c in the output pickup table unit 16, acquires the output data addresses D9, D10, and D11, and outputs the output data output from the output interface 15f according to the addresses. R3, G3, and B3 are stored in the output register 18.

Procedure 14. Under the control of the sequence control unit 10, the output data stored in the output register 18 is DMA-transferred to the memory 22 (not shown) by the output DMA device 19.
Procedure 15. The processes of steps 1 to 14 are repeatedly executed until all the processing target data in the memory 22 (not shown) is processed.

As described above, in the data processing apparatus 1 according to the second embodiment, by appropriately setting the pickup table 13c, the eight data stored in the input register 12 are read out three by three, and the arithmetic processing unit 15 Can be processed four times. That is, in the above procedures 1 to 14, the processing target data U0, U2, Y0, Y2 in the input register 12 are read twice and input to the input interface 15e.
As described above, according to the data processing apparatus 1, when one piece of data is used in a plurality of processes, it is not necessary to perform a process of copying data in advance and aligning the number of data. Can be processed efficiently and at high speed.
Furthermore, the process for reading a single data in the input register 12 a plurality of times is exactly the same as the process for reading the data in the input register 12 once, only the contents of the pickup table are different. Therefore, the amount of data can be compressed without affecting the processing speed at all.

  In the first and second embodiments, the case of generating RGB data of 4 pixels has been described. However, the present invention is not limited to this, and the setting of one processing unit is based on the hardware specifications and the like. Can be changed as appropriate. Further, the input pickup table unit 13 and the output pickup table unit 16 can be mounted integrally, and other specific details such as the size of data stored in the input register 12 can be arbitrarily set. Of course, it can be changed.

It is a block diagram which shows the functional structure of the data processing apparatus 1 in embodiment of this invention. It is a figure which shows typically the structural example of the pickup table stored in the input pickup table part 13 shown in FIG. 2 is a flowchart showing an operation of processing data by a DMA system with arithmetic processing in the data processing apparatus 1 shown in FIG. It is a figure which shows a mode that several data stored in the memory 22 are processed by the data processor 1 shown in FIG. It is explanatory drawing which shows the specific structural example of the pick-up table stored in the input pick-up table part 13 and the output pick-up table part 16 shown in FIG. 1, and the process based on a pick-up table. FIG. 2 is a diagram showing a case where a video conversion process for converting a YUV video signal into an RGB signal is executed in the data processing apparatus 1 shown in FIG. 1 as an embodiment of the present invention. FIG. 2 is a diagram showing a case where a video conversion process for converting a YUV video signal into an RGB signal is executed in the data processing apparatus 1 shown in FIG. 1 as an embodiment of the present invention. It is a figure which shows the example of the conventional DMA system with arithmetic processing. It is a figure which shows the example of the conventional DMA system with arithmetic processing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data processing apparatus 10 Sequence control part 11 Input DMA apparatus 12 Input register 13 Input pickup table part 14 Format conversion part 15 Arithmetic processing part 16 Output pickup table part 17 Format conversion part 18 Output register 19 Output DMA apparatus 20 Bus 21 CPU
22 memory

Claims (5)

Arithmetic processing means for arithmetically processing the processing target data;
Processing target data transfer means for DMA transfer of processing target data in the memory;
First storage means for temporarily storing processing target data transferred by the processing target data transfer means;
The processing target data required for at least one process by the arithmetic processing unit is read from the first storage unit, and the read processing target data is transferred to the arithmetic processing unit in a state suitable for the input format of the arithmetic processing unit. Input format conversion means for input;
A data processing apparatus comprising: A setting table holding unit for holding a setting table for determining an arrangement order of the processing target data stored in the first storage unit;
The input format conversion means arranges the processing target data stored in the first storage means in accordance with an arrangement order defined in a setting table held by the setting table holding means, and inputs the data to the arithmetic processing means. ,
The data processing apparatus according to claim 1. The setting table held in the setting table holding means defines a plurality of specific data among a plurality of data stored in the first storage means, and an arrangement order of the plurality of specific data. There,
The input format conversion means refers to a setting table held in the setting table holding means, reads a plurality of specific data set in the setting table from the first storage means, and sets the setting table in the setting table. 3. The data processing apparatus according to claim 2, wherein the data processing devices are arranged in accordance with the arranged order and input to the arithmetic processing means. Output format conversion means for arranging the output data output from the arithmetic processing means according to a predetermined format;
Second storage means for temporarily storing the output data arranged by the output format conversion means;
Output data transfer means for DMA-transferring the output data stored in the second storage means to the memory;
The data processing apparatus according to claim 1, further comprising: A data processing method for performing DMA transfer of processing target data in a memory and performing arithmetic processing by arithmetic processing means,
Temporarily storing the processing target data transferred from the memory in the first storage means;
The processing target data required for at least one process by the arithmetic processing unit is read from the first storage unit, and the read processing target data is transferred to the arithmetic processing unit in a state suitable for the input format of the arithmetic processing unit. Typing,
A data processing method characterized by the above.

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