JP2005301607A - Information processor, information processing system, and information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor for efficiently operating a plurality of processors in parallel, and to provide an information processing system and an information processing method thereof. <P>SOLUTION: Respective sub-processors 24-1 to 24-n include compressing/extending apparatuses 24B-1 to 24B-n, so as to provide a function of compressing data to be transferred on a system bus 29 and extending data which is received from the bus. Through the use of the function, transfer data between a main memory 23 and local memories 14A-1 to 14A-n in the sub-processors 24-1 to 24-n is compressed. Then, the bottleneck problem in the whole system of data transfer time between the memories is solved. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus including a plurality of processors, an information processing system configured by connecting such an information processing apparatus to a network, and an information processing method applied to such an information processing apparatus.

Conventionally, a multiprocessor distributed parallel processing system (hereinafter referred to as a multiprocessor system) configured using a plurality of processors (arithmetic units) is known. Examples of such a system include Patent Document 1, Patent Document 2, and the like.
JP 7-152664 A JP 2002-351850 A

  In this multiprocessor system, processing is distributed to multiple processors connected to the system bus, and computation processing (signal processing) is performed in parallel. Compared with, a significant improvement in computing power can be expected. In this system, for example, each processor includes an arithmetic unit and a work memory (hereinafter referred to as a local memory), and each processor is configured to share a main memory via a system bus. An arithmetic unit in each processor executes an operation using data transferred from the main memory to the local memory. During the computation, the computing unit accesses only the local memory and does not directly refer to the main memory. When the calculation is completed, the calculation result in the local memory is written back to the main memory.

By taking such a configuration, the following problems are solved.
1. 1. Preventing access conflict by sharing main memory 2. Performance degradation due to low-speed main memory Prevention of system bus traffic increase

  In the multiprocessor system described above, access to the main memory occurs only when data is input / output before and after the calculation. At this time, if the data transfer rate is sufficiently high, the processing capability of the entire system improves as the parallelism of the processors increases.

  However, in the conventional system, the data transfer rate between the main memory and the local memory becomes a bottleneck for the following reasons, and there is a possibility that the processing capacity corresponding to the degree of parallelism of the arithmetic units cannot be extracted from the system.

1. Since the main memory is required to have a large capacity, a low-cost DRAM (dynamic random access memory) is often used, but the DRAM access speed is generally higher than the system bus speed. slow.
2. Since the system bus is also used to transfer transaction data from various peripheral devices, it is impossible for only data transfer between processors or data transfer between the processor and main memory to occupy the bus. As a result, a sufficient transfer rate cannot be secured.

  The present invention has been made in view of such problems, and an object thereof is to provide an information processing apparatus, an information processing system, and an information processing method capable of efficiently operating a plurality of processors in parallel.

  An information processing apparatus according to the present invention includes a bus and a plurality of arithmetic processors commonly connected to the bus. Each arithmetic processor includes an arithmetic unit, a function of compressing arithmetic result data by the arithmetic unit, and the bus. And a compression / decompression unit having a function of decompressing input data fetched through the network.

  The information processing method of the present invention is a method applied to an information processing apparatus including a bus and a plurality of arithmetic processors commonly connected to the bus, and each arithmetic processor takes in the data via the bus. Input data is selectively decompressed, arithmetic processing is performed based on the decompressed input data, arithmetic result data that is the result of the arithmetic processing is selectively compressed, and sent to the bus It is.

  The information processing system of the present invention is an information processing system in which a plurality of information processing devices are connected to a network, and each information processing device includes a bus and a plurality of arithmetic processors connected to the bus in common. And each arithmetic processor has an arithmetic unit, a compression / decompression unit having a function of compressing operation result data by the arithmetic unit, and a function of expanding input data taken in via the bus. .

  In the information processing apparatus, the information processing system, and the information processing method of the present invention, input data taken in via the bus is selectively expanded and arithmetic processing is performed based on the expanded input data. The calculation result data, which is the calculation result, is selectively compressed and sent to the bus. Since the data transmitted through the bus is compressed, the amount of data transferred between processors is reduced.

  According to the information processing apparatus, the information processing system, and the information processing method of the present invention, the data transferred on the bus between the plurality of processors is selectively compressed, so that the compression processing is not performed at all. Data amount can be reduced and transfer time can be shortened. As a result, in the case of a distributed processing system in which the data transfer time for each processor is a bottleneck in calculation performance, the bottleneck location can be changed from the transfer time to an operation processing time including compression / decompression processing. . Thereby, a plurality of processors can be efficiently operated in parallel to improve the processing capacity of the entire system.

  Hereinafter, the best mode for carrying out the present invention (hereinafter simply referred to as an embodiment) will be described in detail with reference to the drawings.

  FIG. 1 shows the overall configuration of an information processing system according to an embodiment of the present invention. Note that an information processing apparatus and an information processing method according to an embodiment of the present invention are embodied by the information processing system, and will be described below.

  This information processing system includes a network 1 and a plurality of information processing devices 2, 3, and 4. All of the information processing apparatuses 2 to 4 have the same configuration. In the following, the information processing apparatus 2 will be described on behalf of the information processing apparatus. In addition, although the information processing apparatus shown here is three, two may be sufficient, and four or more may be sufficient.

  Each of the information processing apparatuses 2 to 4 uses a software cell, which will be described later, and communicates with other information processing apparatuses via the network 1, various commands, apparatus information held by each information processing apparatus, necessary programs, and the like Has the function of transmitting and receiving. Here, the device information is, for example, the power status of each information processing device (whether the power is ON or OFF), what type of information processing device, what input / output interface, and the interface is This is information indicating which one is connected.

  The information processing apparatus 2 includes a main processor 21, a memory controller 22, a main memory 23, and a plurality of sub processors 24-1 to 24-n (n is a positive integer). These constitute one multiprocessor unit 20. The multiprocessor unit 20 can be configured as one integrated circuit chip. The multiprocessor unit 20 is assigned an information processing apparatus ID, which is an identifier that can uniquely identify the information processing apparatus 2 throughout the information processing system. In the following description, when the sub processors 24-1 to 24-n are collectively shown, they are collectively referred to as “sub processor 24” as appropriate.

  The information processing apparatus 2 also includes a disk controller 25, an external recording device 26, a bus arbiter 27, and a network connection unit 28. The blocks other than the main memory 23 and the external recording device 26 are connected to each other by a system bus 29. The main memory 23 is connected to the memory controller 22, and the external recording device 26 is connected to the disk controller 25.

  The main processor 21 is for performing schedule management of program execution (data processing) by the sub-processor 24 and general management of the multiprocessor unit 20. However, the main processor 21 may execute a program other than the management program. In that case, the main processor 21 functions in the same manner as the sub-processor 24. The main processor 21 has a local memory (local storage) 21A as a temporary work memory.

  The main memory 23 is shared by the main processor 21 and the sub processors 24-1 to 24-n, and various function programs that control the functions of the information processing apparatus 2 and data necessary for processing (related to each information processing apparatus). Including device information). As the main memory, for example, a relatively low-speed memory such as a DRAM (Dynamic Random Access Memory) can be used.

  The memory controller 22 is located between the system bus 29 and the main memory 23 and functions as a so-called DMAC (Direct Memory Access Controller). The sub-processors 24-1 to 24-n include programs stored in the main memory 23, It is possible to perform direct memory access (DMA) transfer by directly accessing the data (not via the main processor 21).

  Each of the sub-processors 24-1 to 24-n executes a program in parallel and independently under the control of the main processor 21 to process data. However, the program in the main processor 21 may operate in cooperation with the program in the sub processor 24 as necessary. A function program described later is also a program that operates in the main processor 21.

  The sub processor 24-1 includes a local memory (local storage) 24A-1, a compression / decompression unit 24B-1, and an arithmetic unit 24C-1. The local memory 24A-1 is used as a temporary work memory by the arithmetic unit 24C-1. The compression / decompression device 24B-1 performs decompression processing on the data transferred and input from the main memory 23 via the system bus 29 as necessary, and also sends the transmission target data (stored in the local memory 24A-1). The calculation result data by the calculator 24C-1 is compressed as necessary. The arithmetic unit 24C-1 performs predetermined arithmetic processing (signal processing) on the data input from the main memory 23 and stored in the local memory 24A-1. Examples of the arithmetic processing include scientific and technological calculation processing in addition to image processing and acoustic processing. In the sub-processor 24-1, timing control and the like when data is transferred to and from the main memory 23 after obtaining a bus use right (described later) from the bus arbiter 27 are performed by a control unit (not shown). . However, instead of this control unit, the computing unit 24C-1 may perform such control.

  The compression algorithm by the compression / decompression device 24B-1 is not limited as long as it is “one that ensures reversibility”. A typical example is an entropy code represented by a Huffman code. However, it is difficult to apply an encoding method that uses a deviation in signal generation frequency to arbitrary signal processing. In consideration of the cost and compression effect associated with compression / decompression processing, it is preferable to employ a compression algorithm based on differential prediction encoding. For example, image signal processing for a moving image can be considered as one of applications to which distributed parallel processing is applied. In this image signal processing, an image frame is usually divided into a plurality of small blocks called macroblocks, and signal processing is performed in units of macroblocks. When this is applied to distributed parallel processing, a macroblock is assigned to each processor to perform parallel operations. Since image signals have a relatively strong spatial and temporal correlation, data compression using prediction is effective.

  The number n of sub-processors is not particularly limited, but as will be described later, it is preferable to provide more sub-processors in order to improve the processing speed of the entire information processing apparatus. The other sub processors 24-2 to 24-n have the same configuration as that of the sub processor 24-1.

  The network connection unit 28 is a LAN interface unit called a so-called NIC (Network Interface Card), and connects the LAN cable constituting the network 1 and the system bus 29.

  The external recording device 26 stores an OS (operating system), which is basic software necessary for the operation of the information processing device 2, as well as application programs such as function programs and driver programs described later, and various data. Examples of the external recording device 26 include a hard disk device and a removable hard disk device, an optical disk device such as a DVD (Digital Versatile Disk) device, an MO (Magneto Optical) drive and a CD ± RW (Compact Disc ± ReWritable) drive, a memory disk, An SRAM (Static Random Access Memory) or the like is used. The disk controller 25 performs access control when the main processor 21 reads / writes data from / to the external recording device 26.

  The bus arbiter 27 is for performing arbitration processing for bus use rights by the main processor 21 and the sub processors 24-1 to 24-n. Specifically, the bus arbiter 27 receives a bus use request from each processor and gives a bus use right to only one processor according to a predetermined algorithm. As a result, data collision on the system 29 can be avoided.

  As described above, each of the sub processors 24-1 to 24-n in the multiprocessor unit 20 executes a program and processes data independently, but different sub processors are included in the main memory 23. If data is read from or written to the same area at the same time, data mismatch may occur. Therefore, the multiprocessor unit 20 performs the following exclusive control in order to avoid such data inconsistency.

  FIG. 2 is a diagram for explaining a data arrangement configuration in the main memory 23 and the local memories 24A-1 to 24A-N and an access control method thereof.

  As shown in FIG. 2A, the main memory 23 is configured by a plurality of memory locations MML0 to MMLm (m is a positive integer). Each of the memory locations MML0 to MMLm (hereinafter simply referred to as MML when collectively referred to) is a storage area specified by specifying an address. Each memory location MML is allocated with additional segments MSEG0 to MSEGm for storing information indicating the state of data stored therein. Each memory location MML is also assigned an access key AK0-AKm.

  Each additional segment MSEG0 to MSEGm (hereinafter collectively referred to simply as MSEG) includes an F / E bit, a sub processor ID, and a local memory address.

  The F / E bit is defined as follows. “F / E bit = 0” is the data being processed being read by the sub-processor 24 or invalid data that is not the latest data because it is empty, and the data is read out. Indicates that writing is possible. The F / E bit is set to “F / E bit = 1” after data writing.

  “F / E bit = 1” indicates that the data in the memory location MML is not read by the sub-processor 24 and is the latest unprocessed data. Data in the memory location MML in the state of “F / E bit = 1” can be read but cannot be written. The F / E bit is set to “F / E bit = 0” after being read by the sub-processor 24.

  When in the state of “F / E bit = 0 (unreadable / writable)”, it is possible to set a read reservation for the memory location MML. For the read reservation for the memory location MML with the “F / E bit = 0”, the sub-processor 24 adds the sub-processor ID of the sub-processor 24 and the local memory as read reservation information to the additional segment MSEG of the memory location MML for which the read reservation is made This is done by writing an address. Thereafter, the data is written to the memory location MML reserved for reading by the sub processor 24 on the data writing side, and when it is set to “F / E bit = 1 (readable / not writable)”, the data is written there. The data is read out to the local memory address of the sub processor 24 having the sub processor ID written in advance in the additional segment MSEG as read reservation information. Such control is effective when data needs to be processed in multiple stages by the plurality of sub-processors 24-1 to 24-n. Immediately after the sub-processor 24 performing the pre-stage processing writes the processed data to a predetermined address on the main memory 23, another sub-processor 24 performing the post-stage processing reads the pre-processed data immediately. This is because it becomes possible.

  The main memory 23 is provided with a plurality of sandboxes SB0, SB1,. Each sandbox defines an area in the main memory 23. Each sandbox is assigned to each sub-processor 24, and only the assigned sub-processor can be used exclusively. That is, each sub-processor 24 can use a sandbox assigned to itself in principle, but cannot access data beyond this area.

  As shown in FIG. 2B, the local memory 24A-1 in the sub-processor 24-1 is also configured by a plurality of memory locations SML. Additional segments SSEG0 to SSEGk (hereinafter simply referred to as SSEG when collectively referred to) are allocated to each memory location SML. Each additional segment SSEG includes a busy bit. When the sub-processor 24 reads the data in the main memory 23 to the memory location MML of its own local memory 24A, the corresponding busy bit is set to 1 and reserved. No other data can be stored in the memory location where the busy bit is 1. After reading to the memory location of the local memory 24A, the busy bit becomes 0 and can be used for any purpose.

  In order to realize exclusive control of the main memory 23, a key management table KMT as shown in FIG. 2C is used. The key management table KMT is stored in a relatively high-speed memory (not shown) such as an SRAM (Static Random Access Memory) provided in the memory controller 22, for example. Each entry in the key management table KMT includes PID1 to PIDn as subprocessor IDs, subprocessor keys PK1 to PKn (hereinafter simply referred to as PK when collectively referred to), and key masks KM1 to KMn ( Hereinafter, the term “KM” is used as a generic name.)

  The process when the sub processor 24 uses the main memory 23 is as follows. First, the sub processor 24 outputs a read or write command to the memory controller 22. This command includes its own sub processor ID and a use request destination address in the main memory 23. Before executing this command, the memory controller 22 refers to the key management table KMT and checks the sub processor key PK of the sub processor 24 that has requested use. Next, the memory controller 22 compares the examined sub-processor key PK of the use request source with the access key AK allocated to the memory location MML of the use request destination in the main memory 23 (FIG. 2A). The above command is executed only when the two keys match.

  In the key mask KM of the key management table KMT shown in FIG. 2C, when the arbitrary bit becomes 1, the corresponding bit of the sub processor key PK associated with the key mask KM is set to “0” or It can be changed to “1”. For example, if the sub-processor key PK is “1010”, in principle, only access to the sandbox SB having the same access key AK “1010” as the sub-processor key PK is permitted. However, if the key mask KM associated with the sub-processor key PK is set to “0001”, for example, only the digit in which the bit of the key mask KM is set to “1” The matching determination between the processor key PK and the access key AK is not masked, and as a result, not only “1010” but also the sandbox SB having the access key AK “1011” can be accessed.

  Next, a transfer data structure when each sub processor 24 performs data transfer with the main memory 23 via the system bus 29 will be described. The transfer data structure when the main processor 21 operates as a sub processor is the same.

  As shown in FIG. 3A, data transferred on the system bus 29 between the sub-processor 24 and the main memory 23 has a packet-type data structure. This packet data includes a packet header PH and a data part DP. The packet header PH includes a compression mode CM indicating a compression state, a data type DT indicating a data type (kind), and a transfer destination (not shown). The data part DP includes a command for instructing a process to be executed and data necessary for the process.

  As shown in FIG. 3B, the compression mode CM includes, for example, 4-bit information, and “compression off”, “A method compression”, “B method compression”, “C” are selected according to the bit string state. Information such as “system compression”,... Here, “compression off” indicates that the data in the data part DP is uncompressed data, and “A method compression” indicates that the data in the data part DP is data compressed by the A method. As shown in FIG. 3C, the data type DT is made up of, for example, 4-bit information, and the data in the data portion DP is “still image”, “moving image”, “audio”, Indicates “text”,...

  In the information processing system according to the present embodiment, data transmission / reception between the information processing apparatuses 2 to 5 is performed using software cells that are control packets having a predetermined format. Specifically, the main processor 21 included in the multiprocessor unit 20 in an information processing device generates a software cell composed of data including commands, programs, device information, and the like, and receives other information via the network. It is designed to send and receive with the processing device. Hereinafter, the software cell will be described.

  FIG. 4 shows a configuration example of the software cell. This software cell includes a transmission source ID 11, a transmission destination ID 12, a response destination ID 13, a cell interface 14, a DMA (Direct Memory Access) command 15, a sub processor program 16, and data 17.

  The transmission source ID 11 includes the IP address of the information processing device that is the transmission source of the software cell, the information processing device ID of the multiprocessor unit in the information processing device, and each sub-unit included in the multiprocessor unit in the information processing device. A processor identifier (sub-processor ID) is included.

  The transmission destination ID 12 and the response destination ID 13 have the same information as the information included in the transmission source ID 11 for the information processing device that is the transmission destination of the software cell and the information processing device that is the response destination of the execution result of the software cell, respectively. included.

  The cell interface 14 is information necessary for using the software cell, and includes a global ID 141, the number of sub-processors 142, a sandbox size 143, and the previous software cell ID 144. The global ID 141 can uniquely identify the software cell throughout the network, and is created based on the transmission source ID 11 and the date and time (date and time) of creation or transmission of the software cell. The number of sub processors 142 indicates the number of sub processors necessary for executing the software cell. The sandbox size 143 indicates the amount of memory in the main memory 23 and the amount of memory in the local memory 24 </ b> A of the sub processor 24 necessary for executing the software cell. The previous software cell ID 144 is an identifier of the previously transferred software cell in one group of software cells that require sequential execution of streaming data or the like.

  The DMA command 15, the sub processor program 16 and the data 17 constitute the execution section 18 of the software cell. The DMA command 15 includes a series of DMA commands necessary for starting the sub processor program 16, and the sub processor program 16 includes a sub processor program executed by the sub processor 24. Data 17 is data processed by a program including the sub processor program 16.

  The DMA command 805 includes a load command 151, a kick command 152, a status request command 153, a status return command 154, and a function program execution command 155.

  The load command 151 is a command for loading the information in the main memory 23 into the local memory 24A in the sub processor 24. In addition to the load command main body portion 151A, the main memory address 151B, the sub processor ID 151C, and the local memory address 151D are stored. Including. The main memory address 151B indicates the address of the information load source area in the main memory 23. The sub processor ID 151CH is an identifier of the sub processor 24 that is the information loading destination, and the local memory address 151D indicates the information loading destination address in the local memory 24A.

  The kick command 152 is a command for starting execution of the program, and includes a sub processor ID 152B and a program counter 152C in addition to the kick command main body 152A. The sub processor ID 152B is for identifying the sub processor to be kicked, and the program counter 152C is for giving an address for the program counter for program execution.

  The status request command 153 is a command for requesting transmission of the device information of the information processing device indicated by the transmission destination ID 12 to the information processing device indicated by the response destination ID 13. The status reply command 154 is a command for the information processing apparatus that has received the status request command 153 to return its own apparatus information to the information processing apparatus indicated by the response destination ID 13 included in the status request command 153. . When the DMA command 15 is the status return command 154, the device information is stored in the data 17 area of the execution section 18.

  The function program execution command 155 is a command in which a certain information processing apparatus requests another information processing apparatus to execute a function program. It includes a command main body 155A and a function program ID 155B. In the multiprocessor unit 20 in the information processing apparatus that has received the function program execution command 155, the main processor 21 identifies the function program to be activated based on the function program ID 155B and loads the function program into the main memory 23. The function program is executed.

  FIG. 5 shows a data configuration example of the status reply command 154. The status reply command 154 includes a command main body 154A and a data portion 154B. The data portion 154B indicates device information of the information processing device that has received the status request command 153. This device information includes information processing device ID 154B-1, information processing device type ID 154B-2, MS (master / slave) status 154B-3, main processor operating frequency 154B-4, main processor usage rate 154B-5, and number of sub-processors. 154B-6, sub processor ID 154B-7, sub processor status 154B-8, sub processor usage rate 154B-9, main memory total capacity 154B-10, main memory usage 154B-11, number of external recording copies 154B-12, external recording A set ID 154B-13, an external recording unit type ID 154B-14, an external recording unit total capacity 154B-15, and an external recording unit usage amount 154B-16. All of these pieces of device information are stored in the main memory 23 in an aggregated manner.

  The information processing apparatus ID 154B-1 is an identifier for identifying the multiprocessor unit 20 in the information processing apparatus, and indicates the information processing apparatus that transmits the status reply command 154. The information processing apparatus ID 154B-1 is generated by the main processor 21 included in the multiprocessor unit 20 in the information processing apparatus when the power is turned on. Specifically, for example, it is generated based on the date and time when the power is turned on, the IP address of the information processing apparatus, the number of sub-processors 24 included in the multiprocessor unit 20 in the information processing apparatus, and the like.

  The information processing apparatus type ID 154B-2 includes a value representing the characteristics of the information processing apparatus. The characteristics of the information processing apparatus are, for example, a TV apparatus, a DVD recorder, and a multiplayer in the case of this embodiment. Further, the information processing apparatus type ID 154B-2 may represent a function of the apparatus such as video / audio recording or video / audio reproduction. It is assumed that values representing the characteristics and functions of the information processing apparatus are determined in advance, and it is possible to grasp the characteristics and functions of the information processing apparatus based on the information processing apparatus type ID 154B-2.

  The MS status 154B-3 represents whether each information processing apparatus is operating as a master or a slave as will be described later. Specifically, for example, when the MS status 154B-8 is set to “0”, it indicates that it is operating as a master, and when it is set to “1”, it is operated as a slave device. Indicates that

  The main processor operating frequency 154B-4 represents the operating frequency of the main processor in the multiprocessor unit. The main processor usage rate 154B-5 represents the usage rate in the main processor for all programs currently being executed in the main processor. The main processor usage rate 154B-5 is a value representing the ratio of the processing capacity in use to the total processing capacity of the target main processor. For example, MIPS (Million Instructions Per Second) which is a unit for evaluating the processing capacity of the processor As a unit, or based on the processor usage time per unit time. The sub processor usage rate 154B-9, which will be described later, is calculated in the same manner.

  The number of sub processors 154B-6 represents the number of sub processors included in the multiprocessor unit, and the sub processor ID 154B-7 is an identifier for identifying each sub processor in the multi processor unit.

  The sub processor status 154B-8 represents the state of each sub processor, and includes states such as “unused”, “reserved”, and “busy”. unused indicates that the sub-processor is not currently used and reserved for use, reserved indicates that it is not currently used but reserved, busy is currently in use It is meant to represent something.

  The sub processor usage rate 154B-9 represents the usage rate in the sub processor for a program currently being executed in the sub processor or reserved for execution in the sub processor. That is, the sub processor usage rate 154B-9 indicates the current usage rate when the sub processor status is busy, and indicates the estimated usage rate to be used later when the sub processor status is reserved. Show.

  The sub processor ID 154B-7, the sub processor status 154B-8, and the sub processor usage rate 154B-9 are set for one sub processor 24, and the number of sub processors in one multiprocessor unit 20 is set. Only the set of is set.

  The main memory total capacity 154B-10 and the main memory usage 154B-11 represent the total capacity of the main memory 23 and the capacity currently in use, respectively.

  The number of external recording devices 154B-12 represents the number of external recording devices 26 connected to the multiprocessor unit 20. The external recording device ID 154B-13 is information for uniquely identifying the external recording device connected to the multiprocessor unit. The external recording device type ID 154B-14 represents the type of the external recording device (for example, hard disk, CD ± RW, DVD ± RW, memory disk, SRAM, ROM, etc.). The external recording device total capacity 154B-15 and the external recording device usage amount 154B-16 represent the total capacity of the external recording device 26 identified by the external recording device ID 154B-13 and the capacity currently in use, respectively.

  The external recording device ID 154B-13, the external recording device type ID 154B-14, the external recording device total capacity 154B-15, and the external recording device usage amount 154B-16 are set as one set for one external recording device 26. Yes, only the number of external recording devices connected to the multiprocessor unit 20 is set.

  Next, software owned by the information processing apparatus 2 will be described. Software held by the information processing apparatus 2 includes a control program, a function program, and a device driver. These softwares are recorded in advance in an external recording device 26 connected to the multiprocessor unit 20, and are read from the external recording device 26 when the information processing apparatus 2 is turned on. .

  The control program is software executed by the main processor 21 of the multiprocessor unit 20 having a function of controlling and managing the configuration of the entire information processing system. This control program includes an MS (master / slave) manager and a capability exchange program. The MS manager has a function of setting information as to whether each information processing apparatus is a master or a slave, as will be described later. The capability exchange program has a function of acquiring device information held by each information processing device.

  The function program is software executed by the main processor 21 and having a function responsible for application processing operations in the information processing apparatus 2. For example, a program according to the information processing apparatus such as a recording program, a reproduction program, and a material search program is included.

  The device driver is software for data input / output (transmission / reception) of the multiprocessor unit 20, and includes information processing such as a broadcast reception driver, a monitor output driver, a bitstream input / output driver, and a network input / output driver. Including those according to the device.

  Next, the operation of the information processing system configured as described above will be described.

  In this information processing system, the information processing apparatuses 2 to 4 transmit and receive apparatus information between each other using the software cell shown in FIG. Thereby, one of the information processing apparatuses is set as a master, and the other information processing apparatus is set as a slave. Each information processing device periodically monitors the status of other information processing devices by sending a software cell including a status request command as a DMA command to other information processing devices on the network and inquiring status information. To do. In the main memory 23 of the information processing apparatus set as the master, apparatus information of all information processing apparatuses including the self apparatus is collected. Each information processing apparatus can entrust a necessary process to another information processing apparatus using a software cell and execute it.

  In an information processing apparatus that is instructed to execute a command from another information processing apparatus or receives a processing instruction directly by a user operation, a plurality of sub-processors 24-1 to 24- n executes a given process in parallel. At this time, the multiprocessor unit 20 performs exclusive control related to the sandbox of the main memory 23. First, this exclusive control will be described.

  When it is necessary to process data in multiple stages by the sub-processors 24-1 to 24-n, the sub-processor 24 that performs the process in the previous stage by performing control based on the memory structure as described in FIG. Only the sub-processor 24 that performs the subsequent processing can access a predetermined address in the main memory 23 and can protect data.

  The process when the sub processor 24-1 uses the main memory 23 is as follows. First, the sub processor 24-1 outputs a read or write command to the memory controller 22. This command includes its own sub-processor ID and use request destination address in the main memory 23. Before executing this command, the memory controller 22 refers to the key management table KMT and checks the sub processor key PK of the requesting sub processor 24-1. Next, the memory controller 22 checks the sub-processor key PK of the requesting sub-processor 24-1 and the access key assigned to the use-requested memory location MML (FIG. 2A) in the main memory 23. The above command is executed only when two keys match with AK.

  In the multiprocessor unit 20, the following control is possible by using the key mask KM of the key management table KMT.

  That is, immediately after the information processing apparatus 2 is activated, the values of the key mask KM are all zero. Here, it is assumed that the program in the main processor 21 operates in cooperation with the program in the sub processor 24. Assume that the processing result data output from the sub processor 24-1 is temporarily stored in the main memory 23 and input to the sub processor 24-2. In this case, the storage area in the main memory 23 needs to be accessible from either of the sub processors 24-1 and 24-2. In such a case, the program in the main processor 21 appropriately changes the value of the key mask KM, and provides an area in the main memory 23 that can be accessed from the plurality of sub processors 24, thereby allowing the sub processor 24 to perform multiple stages. To enable automatic processing.

For example, a case where multistage processing is performed in the following procedure is assumed.
(1) Data input from other information processing apparatus (2) Processing by sub-processor 24-1 (3) Storage in memory location SML1 in main memory 23 (4) Processing by sub-processor 24-2 (5) Main Store to memory location SML2 in memory 23

  In this case, for example, the sub processor key PK = “0100” of the sub processor 24-1, the access key AK = “0100” of the memory location SML1 in the main memory 23, and the sub processor key PK = “0101” of the sub processor 24-2. If the access key AK of the memory location SML2 in the main memory 23 is set to “0101”, the sub-processor 24-2 cannot access the memory location SML1 in the main memory 23 as it is. Therefore, by setting the key mask KM2 of the sub processor 24-2 to “0001”, the sub processor 24-2 can access the memory location SML1 in the main memory 23.

  Next, parallel processing operations performed by the sub-processors 24 in the multiprocessor unit 20 will be described with reference to FIG. FIG. 6 shows a processing procedure when a certain sub processor 24 performs predetermined arithmetic processing on data read from the main memory 23 and then writes the processing result back to the main memory 23. Since the operations of the sub processors 24-1 to 24-n are all the same, only the sub processor 24-1 will be described here.

  In the sub-processor 24-1, a control unit (not shown) obtains the right to use the bus from the bus arbiter 27 and transfers data necessary for the arithmetic processing of the arithmetic unit 24C-1 from a predetermined memory location MML of the main memory 23 to the local memory 24A-. Transfer to one predetermined memory location SML (step S101). This data is transferred as packet data as shown in FIG.

  The compression / decompression unit 24B-1 of the sub processor 24-1 analyzes the packet header PH of the data stored in the local memory 24A-1, and determines whether or not data expansion is necessary (step S102). As a result, when this data is compressed, it is determined that the decompression process should be performed (step S103; Y), and the decompression process is performed by a method corresponding to the compression mode (FIG. 3B) ( Step S104). For example, if the compression mode CM of the packet header PH is “0001”, the compression / decompression unit 24B-1 determines that the data is compressed by the “A method”, and sets the “A method”. The decompression process is performed by the corresponding decompression method “a method”, and the decompressed data is written back to the local memory 24A-1. On the other hand, when the compression mode CM is “0000”, it is determined that the data is uncompressed data, and the decompression process is not performed (step S103; N), and the process directly proceeds to the operation process of step S105. In the present embodiment, the information of the data type DT of the packet header PH is not used and is unnecessary. This data type DT is used in a modification described later.

  The computing unit 24C-1 performs arithmetic processing on the data stored in the predetermined memory location SML of the local memory 24A-1 (Step S105). This arithmetic processing is assigned in advance to each of the sub processors 24-1 to 24-n by the main processor 21, and is, for example, image processing, acoustic processing, numerical calculation, or the like. The calculator 24C-1 stores the calculation result again in a predetermined memory location SML of the local memory 24A-1.

  Next, the compression / decompression unit 24B-1 determines the validity of performing the compression process on the operation result data stored in the local memory 24A-1 (step S106). If the data transfer amount is large and compression is necessary, it is determined that compression is appropriate (step S107; Y). If the data transfer amount is small and compression is not necessary, it is appropriate not to perform compression. (Step S107; N). This determination is made based on, for example, a comparison result between the data transfer required time Tt and the calculation required time Tp. Here, the data transfer required time Tt is a time required when data is directly sent to the system bus 29 and transferred to the main memory 23 without being compressed. The calculation required time Tp is a time required for calculation processing in the sub-processor 24 (for example, 24-2) that has acquired the bus use right next time. Since the relationship between the data transfer required time Tt and the calculation required time Tp can be estimated statically, the necessity of compression processing at the time of output is set at the time of starting the processor 24-1, and the effect cannot be obtained. It is possible to prevent the compression process from being performed. For example, if the amount of original data transfer is small, but the calculation takes a long time, even if one processor finishes the transfer process and the other processor is not ready to transfer, the data is compressed and transferred There is no effect of doing so, and outputting the data as it is does not affect the overall performance. Therefore, for example, when Tp <Tt, it is possible to avoid wasting energy by not performing the compression process.

  When the compression / decompression unit 24B-1 determines that the compression process is valid, the compression / decompression unit 24B-1 executes the compression process on the data in the local memory 24A-1, and temporarily writes the result back to the local memory 24A-1. (Step S108). On the other hand, when it is determined that the compression process is not valid, uncompressed data (raw data in the local memory) is selected without compression (step S112).

  When the compression process is executed, the compression / decompression unit 24B-1 further evaluates the compression result (step S109). This evaluation is performed, for example, by comparing the data amount before compression with the data amount after compression. Specifically, when the compression rate, which is the ratio of the amount of data after compression to the amount of data before compression, exceeds a predetermined threshold, it is determined that the compression effect is large (step S110; Y), and the compressed data is selected. (Step S111). On the other hand, if the compression rate is equal to or lower than the predetermined threshold value, it is determined that the compression effect is small (step S110; N), and uncompressed data is selected (step S112).

  At this time, the compression / decompression unit 24B-1 generates a data packet (FIG. 3A) by adding the packet header PH to the data part DP including the data selected above (step S113), and the system bus 29 Send it up. This packet header PH includes, as a compression mode, information on whether or not compression has been performed, and information on the compression method when compression is performed. The compression result can be notified to the transfer destination main memory 23 in this compression mode.

  In this way, the operation result data calculated by the arithmetic unit 24C-1 is transferred as it is or compressed and transferred from the local memory 24-1 to the main memory 23, and a predetermined memory location MML in the main memory 23 is obtained. (Step S114).

  Here, before describing the characteristic operation of the multiprocessor unit 20 of the present embodiment, a comparative example with respect to the present embodiment will be described with reference to FIG.

  FIG. 10 shows the timing of the parallel processing operation in the comparative example. This comparative example assumes the case where data transfer is performed without compression processing in each sub-processor. The horizontal axis represents time, and the vertical axis represents the degree of parallelism (that is, the number of sub-processors engaged in parallel processing).

  In this comparative example, it is assumed that three sub-processors A, B, and C perform parallel processing operations. At time t0, input data is transferred from the main memory to the local memory of the sub processor A connected to the system bus. At time t2, transfer of input data to the sub processor A is completed, and the sub processor A starts arithmetic processing. At the same time, data transfer (input) to the sub processor B starts. The sub processor A finishes the arithmetic processing at time t3. At this point, the sub processor A is in the middle of data transfer, so the sub processor A waits for the start of data transfer (output).

At time t4, data input to the sub processor B is completed, and the sub processor B starts arithmetic processing. At the same time, data transfer (input) to the sub processor C starts. The sub processor B finishes the arithmetic processing at the time t5. At this time, the sub processor C is in the middle of data transfer, so the sub processor B waits for the start of data transfer (output).

  At time t6, data input to the sub processor C is completed, and the sub processor C starts arithmetic processing. Since the bus is free at this time, the output result is transferred from the sub processor A. At time t7, the sub processor C finishes the arithmetic processing. When the output from the sub-processor A is completed at time t8, the sub-processor B starts data transfer (output) at this time. When the output from the sub processor B is completed at time t10, the sub processor C starts data transfer (output) at this time. The output from the sub processor C is completed at time t12.

  Since each sub-processor shares the main memory in this way, data transfer between the main memory and the local memory in the sub-processors A, B, and C occurs sequentially as shown in FIG. . In the comparative example shown here, the data transfer between the memories becomes a bottleneck (dominant) between t3 and t4 and between t5 and t6, and the sub processor is in a waiting state. Therefore, it can be seen that the processing capability does not improve even if the degree of parallelism of the sub processors is further increased.

  On the other hand, in the present embodiment, a compression / decompression unit 24B-1 is provided in each sub processor, thereby providing a function of compressing data transferred on the system bus 29 and decompressing data received from the bus. . With this function, the transfer data between the main memory 23 and the local memory 14A in the sub processor 24 is compressed, and it becomes possible to eliminate the fact that the data transfer time between the memories becomes a bottleneck of the entire system. Hereinafter, the parallel processing in the present embodiment will be described with reference to FIG.

  FIG. 7 shows the timing of the parallel processing operation in the multiprocessor unit 20 of the present embodiment. In this example, it is assumed that data that is always compressed in the sub-processors 24-1 to 24-4 is transferred. The horizontal axis represents time, and the vertical axis represents the degree of parallelism.

  In FIG. 7, at time t0, data transfer (input) is performed from the main memory to the sub-processor 24-1 connected to the system bus. When the data transfer to the sub-processor 24-1 is completed at the time t1, the sub-processor 24-1 starts data expansion, and at the same time, the data transfer to the sub-processor 24-2 is started.

  At time t2, the sub processor 24-2 completes data transfer and starts decompression processing. At this time, since the sub processor 24-1 is in the middle of signal processing and the system bus 29 is free, data transfer from the main memory 23 to the sub processor 24-3 is started.

  At time t3, the sub processor 24-3 completes data transfer and starts decompression processing. At this time, since the sub-processor 24-1 is in the middle of signal processing and the system bus 29 is free, data transfer from the main memory 23 to the sub-processor 24-4 is started.

  At time t4, the sub processor 24-4 completes the data transfer and starts the decompression process. At this time, since the sub processor 24-1 has finished the data compression processing, the operation result data is transferred from the sub processor 24-1 to the main memory 23.

  At time t5, the transfer output of the operation result data from the sub processor 24-1 to the main memory 23 is completed, and the transfer output of the operation result data from the sub processor 24-2 to the main memory 23 is started. At time t6, the transfer output of the operation result data from the sub processor 24-2 is completed, and the transfer output of the operation result data from the sub processor 24-3 starts. At time t7, the transfer output of the operation result data from the sub processor 24-3 is completed, and the transfer output of the operation result data from the sub processor 24-4 is started. At time t8, the transfer output of the operation result data from the sub processor 24-4 is completed.

  In the parallel processing of this embodiment, the transfer time is shortened because the data is transferred on the system bus in a compressed state. On the other hand, since data decompression processing is added as pre-processing of computation and data compression processing is added as post-processing of computation, the overall computation time is increased. As a result, the bottleneck portion of the multiprocessor unit 20 is converted from the data transfer time to the calculation time. However, the performance degradation due to the increase in computation time can be easily solved by increasing the parallelism of the sub processors. For this reason, the processing capability is improved when the multiprocessor unit 20 is viewed as a whole.

  By the way, it is assumed that various operations are performed in each sub-processor. Depending on the computation, the amount of data is small and the transfer time may not become a bottleneck. In addition, some data may not be very effective even when compressed, and in such a case, system resources are wasted as much as decompression processing is performed on the receiving side.

  FIG. 8 shows the operation timing when it is determined that data compression is not necessary in each of the sub processors 24-1 to 24-n of the multiprocessor unit 20 in the present embodiment.

  In this example, data transfer is performed from the main memory to the sub processor 24-1 at time t0. When the data transfer to the sub processor 24-1 is completed at the time t1, the sub processor 24-1 starts data expansion. At the same time, data transfer is started to the sub-processor 24-2. At time t2, the sub processor 24-2 completes the data transfer and starts the decompression process. At this time, since the sub-processor 24-1 is in the middle of signal processing and the system bus is free, data transfer to the sub-processor 24-3 is started. At time t3, the sub processor 24-3 completes data transfer and starts decompression processing. At this point, since the sub-processor 24-1 has finished the calculation, it determines in the compression necessity determination that data compression is not to be performed, and immediately starts the transfer of the calculation result. At time t4, data transfer from the sub-processor 24-1 has already been completed. For this reason, the sub-processor 24-2 determines not to compress data in the determination of whether or not compression is necessary, and immediately starts to transfer the calculation result. At time t5, data transfer from the sub-processor 24-2 has already been completed. For this reason, the sub-processor 24-3 determines that data compression is not performed in the determination of whether compression is necessary, and immediately starts to transfer the calculation result. At time t6, the data transfer from the sub processor 24-3 is completed.

  Thus, by determining whether the compression is effective in advance and determining whether or not the processing is necessary, it is possible to avoid the above-described problem (sub processor resource waste). That is, there is a case where the original data transfer amount is small, and even when one sub processor finishes the transfer process, another sub processor is not ready to perform the transfer (still being processed). In such a case, there is no effect of compressing and transferring the data, and output of the data as it is does not affect the overall performance. For example, in FIG. 8, when attention is paid to t4, the sub-processor 24-1 has finished the transfer at this point, and waits for the end of the calculation in order to start the next transfer. This means that there is no system bottleneck in the transfer process. Therefore, there is no need to perform compression processing. Since the relationship between the computation time and the data transfer time can be estimated statically, the processor resources are set by setting whether or not the output stage compression processing is performed at the time of starting the processor, and not performing the compression processing that is not effective. Can be avoided.

  In general, in data compression processing by predictive coding, the compression efficiency increases as the correlation between signals increases, and if the correlation is weak, the compression method that transmits the difference may not provide a sufficient compression effect. is there. In this regard, in this embodiment, the compression result is evaluated after the signal output to the system bus is compressed, and if the compression rate does not exceed a certain threshold value, the signal before compression is transmitted to the bus. ing. In this case, the data transfer amount does not decrease, and the transfer-source subprocessor consumes wasted energy for the compression processing, but on the other hand, the signal becomes an input to the other subprocessors. In this case, it is not necessary to perform the decompression process, so that it is possible to prevent further wasteful energy consumption in the sub processor.

  Note that the data compression / decompression algorithm and mounting method in the compression / decompression unit 24B-1 depend on the configuration of the multiprocessor unit 20, and can be realized by either hardware or software. In the case of hardware implementation, the time required for compression / decompression processing is short, so the number of processors to be added to conceal the compression / decompression processing (so as not to be affected by the compression / decompression processing) Degree) can be reduced. On the other hand, in the case of implementation by software, it is possible to appropriately select an optimal data compression method according to the characteristics of the transfer data, and it is possible to improve the calculation performance of the system without changing the hardware. .

As described above, the information processing apparatus according to the present embodiment has the following effects.
(1) Since sub-processors can be used efficiently, it is possible to improve the computing capacity per operating frequency without requiring hardware changes.
(2) Compared with the comparative example, the equivalent computing capability can be realized at a lower operating frequency, so that the operating voltage can be lowered and the computing capability per power consumption can be improved.
(3) Since there is no particular limitation on the method for mounting data compression / decompression, mounting by either hardware or software can be selected as appropriate according to system requirements.
(4) When the compression result is monitored and a sufficient compression result cannot be obtained, a mechanism is provided to transfer the uncompressed data to the bus so that the data is input to the sub processor at the next stage. Since the expansion process at the input stage in the sub-processor at the next stage is not necessary, useless energy consumption can be saved.

  While the present invention has been described with reference to the embodiment, the present invention is not limited to this embodiment, and various modifications can be made. For example, in the present embodiment, after the data compression is executed once, the compression processing result is evaluated, and depending on the result, the original data (uncompressed data) is transferred. Instead of the ex-post evaluation, for example, as shown in FIG. 9, the evaluation may be performed in advance (before compression). In FIG. 9, steps S201 to S207 and S212 to S215 are the same as steps S101 to S107 and S111 to S114 in the above-described embodiment (FIG. 6), respectively, and description thereof will be omitted as appropriate.

  In the modification shown in FIG. 9, after determining the validity of the data compression in step S207, the type of the data to be compressed is determined (step S208), and processing according to the determination result is performed. Specifically, based on the bit information read from the data type DT of the packet header PH at the time of data input, the type of the data (still image, moving image, voice, text, etc.) is determined. As a result of the setting, if the data is a kind of data having a small compression effect such as text data (step S209; Y), it is decided not to perform compression, and uncompressed data is selected (step S213). ). On the other hand, when the data is a kind of data having a large compression effect such as a still image, a moving image, and sound data (step S209; N), it is decided to perform compression, and further according to the kind of the data. A compression method is selected (step S210), and data compression by the compression method is executed (step S211). Then, the compressed data is selected as transfer data (step S212), the packet header PH is added to the data, and the packet data is transmitted to the system bus 29 (steps S214 and S215). At this time, the bit information shown in FIG. 3B is set in the compression mode CM of the packet header PH according to the compression method. Further, the bit information shown in FIG. 3C is set in the data type DT of the packet header PH according to the type of data.

  According to this modification, since the necessity of compression is determined in advance, it is possible to avoid a situation in which uncompressed data is eventually transferred although compression processing is performed once as in the case of the above embodiment. it can. For this reason, useless energy consumption in the transfer source sub-processor can be avoided.

  In the above embodiment, the case where the present invention is applied to the data transfer between the main memory and the local memory in the sub processor has been described. However, the present invention may be applied to the data transfer between the sub processors (between the local memories). Is possible.

It is a block diagram showing the structure of the information processing system which concerns on one embodiment of this invention. FIG. 2 is a block diagram illustrating a configuration of a storage area of a main memory and a local memory in a sub processor of FIG. 1 and a configuration of a key management table for realizing exclusive access control for the main memory. It is a figure showing the example of a format of the packet data transferred between the main memory and the local memory of a sub processor. It is a figure showing the structure of the software cell used for the exchange between information processing apparatuses of the information processing system of FIG. It is a figure showing an example of the status reply command transmitted using the software cell of FIG. 2 is a flowchart illustrating parallel processing of a plurality of sub processors illustrated in FIG. 1. FIG. 2 is a timing diagram illustrating a timing example in parallel processing operations of a plurality of sub processors illustrated in FIG. 1. FIG. 10 is a timing diagram illustrating another timing example in parallel processing operations of the plurality of sub processors illustrated in FIG. 1. 6 is a flowchart illustrating a modification example of the parallel processing operation of the plurality of sub processors illustrated in FIG. 1. It is a flowchart showing the example of a timing in the parallel processing operation | movement of the some processor in a comparative example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Network, 2, 3, 4 ... Information processing apparatus, 20 ... Multiprocessor unit, 21 ... Main processor, 22 ... Memory controller, 23 ... Main memory, 24-1 to 24-n ... Sub processor, 21A, 24A- 1-24A-N: Local memory, 24B-1-24B-N: Compression / decompression unit, 24C-1-24C-N: Operation unit, 27: Bus arbiter, 28 ... Network connection unit, 29 ... System bus, PH ... Packet Header, DP ... data part, CM ... compression mode, DT ... data type.

Claims (12)

A bus, and a plurality of arithmetic processors commonly connected to the bus,
Each arithmetic processor
An arithmetic unit;
An information processing apparatus comprising: a compression / decompression unit having a function of compressing operation result data by the arithmetic unit and a function of expanding input data taken in via the bus. The compression / decompression unit determines whether or not the compression processing is performed on the calculation result data by the calculation unit, and the calculation result data is used as it is or after the compression processing is performed according to the determination result. The information processing apparatus according to claim 1, wherein the information processing apparatus is sent upward. Whether the compression / decompression unit performs compression processing on the operation result data to be sent out on the bus based on the magnitude relationship between the operation required time of the arithmetic unit and the data transfer required time on the bus. The information processing apparatus according to claim 2, wherein: The compression / decompression unit determines whether or not to perform compression processing on the operation result data transmitted on the bus in consideration of the type of the operation result data. Information processing device. The compression / decompression unit temporarily compresses the operation result data, and based on the compression process result, sends either the operation result data that has been compressed or the operation result data before compression onto the bus. The information processing apparatus according to claim 2, wherein: The information processing apparatus according to claim 2, wherein the compression / decompression unit further selects a compression processing method when performing compression processing on the operation result data. The information processing apparatus according to claim 6, wherein the compression / decompression unit selects the compression processing method based on a type of the operation result data. The compression / decompression unit determines whether or not to perform decompression processing on the input data, and inputs the input data to the arithmetic unit as it is or after performing decompression processing according to the determination result. The information processing apparatus according to claim 1. The information processing apparatus according to claim 8, wherein the compression / decompression unit further selects a decompression processing method when performing decompression processing on the input data. The information processing apparatus according to claim 1, wherein the plurality of arithmetic processors include a main processor and a plurality of sub-processors. A method applied to an information processing apparatus including a bus and a plurality of arithmetic processors commonly connected to the bus,
In each arithmetic processor,
Selectively decompressing input data captured via the bus,
Perform arithmetic processing based on the expanded input data,
An information processing method comprising: selectively compressing operation result data that is a result of the operation processing and sending the result to the bus. An information processing system comprising a plurality of information processing devices connected to a network,
Each information processing apparatus includes a bus and a plurality of arithmetic processors commonly connected to the bus.
Each arithmetic processor
An arithmetic unit;
An information processing system comprising: a compression / decompression unit having a function of compressing operation result data by the arithmetic unit and a function of expanding input data taken in via the bus.

Images