JP2005295192A - Apparatus and method for turbo decoding - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable to reduce a processing time by improving the decoding capability in a turbo decoding and optimizing the number of times of repeating the turbo decoding. <P>SOLUTION: Two turbo decoders 101A, 101B repeatedly perform error correction decoding to input data (code blocks #1, #2) in parallel. Its decoding result is stored in a memory 103. An error detector 105 detects an error presence remaining in the decoding result based on the error detection code included in the decoding result stored in the memory 103. A repeating control circuit 106 continuously performs repeating decoding process continuously for the two turbo decoders 101A, 101B until no error is judged. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a turbo decoding device and a turbo decoding method for decoding a turbo code.

  The turbo code is a coded sequence obtained by performing error detection coding and error correction coding on information bits, and is a powerful error correction code that can obtain high error correction capability by repeatedly performing decoding processing. Although this specification will be described with application to mobile communication in mind, application to various fields such as satellite communication, magnetic recording, and optical communication is being studied not only for mobile communication but also for its excellent features.

  By the way, in turbo decoding, since a considerable number of iterations are required to realize high error correction capability, there is a problem that processing time increases. For example, Patent Document 1 discloses a technique for optimizing the number of repetitions of turbo decoding processing. Hereinafter, the outline will be described with reference to FIG.

  FIG. 5 is a block diagram illustrating a configuration example of a conventional turbo decoding device. The conventional turbo decoding apparatus shown in FIG. 5 includes a turbo decoder 501 that performs turbo decoding on received data, and a hard decision that converts a soft value output from the turbo decoder 501 into a hard value of “0” or “1”. Unit 502, a data buffer 503 for storing the hard value determined by hard decision unit 502, and the number of repetitions of decoding processing in turbo decoder 501, and when a predetermined maximum number of repetitions is reached, a control signal or An iterative counter 504 that outputs a trigger signal and whether or not there is an error in the decoded information bits stored in the data buffer 503 are checked in units of data frames. If an error is detected, a control signal is fed back to the turbo decoder 501. CRC (Cyclic Redundancy Check) tester 505 and the control signal or trigger signal output from repetition counter 504 And a data extractor 506 for extracting and outputting data from the data frame stored in the data buffer 503, which has been checked by the CRC checker 505, by removing the CRC bits added to the data frame. ing.

  The turbo decoder 501 is provided with a trigger circuit or a control circuit. This trigger circuit or control circuit operates to control the turbo decoder 501 itself in accordance with the control signal output from the CRC checker 505 and to execute further decoding processing.

  In addition, the turbo decoder 501 supplies a signal indicating completion of one decoding process in the turbo decoder 501 to the iteration counter 504 in a decoding process that is repeated. The iteration counter 504 counts the number of iterations of the decoding process processed by the turbo decoder 501 based on this completion signal. The iterative counter 504 resets the count value when a new code block is received by the turbo decoder 501 and the processed code block is output from the turbo decoder 501.

  A code block is a data unit when turbo decoding is performed on an encoded sequence obtained by performing error detection coding and error correction coding on information bits. The processed code block is output from the turbo decoder 501 either when no error is detected by the CRC checker 505 or when the decoding process by the turbo decoder 501 is repeated a predetermined number of times. .

As described above, the conventional turbo decoding device is configured to inspect the decoded information bits every time the decoding process is repeated and to determine whether or not to perform further decoding processing based on the result of the inspection. The processing time can be reduced without degrading the error correction capability.
JP 2000-183758 A

  However, in the iterative control method implemented in the conventional turbo decoding apparatus described above, the optimum repetition is performed when the CRC bits are not located at the boundary between the code blocks or when the CRC bits are not included in the code block. There is a problem that control cannot be performed. Hereinafter, a specific description will be given with reference to FIGS.

  FIGS. 6A to 6C show configuration examples of data input to the turbo decoding device. 6A to 6C show a case where two code blocks # 1 and # 2 are formed from input data. 6A to 6C, a transport block is an information bit to be transmitted on the transmission side, and is a data unit to which a CRC bit is added on the transmission side.

  In FIG. 6A, the input data to the turbo decoder is “transport block # 1, CRC bit # 1, transport block # 2, CRC bit # 2, transport block # 3, CRC bit # 3, transport. A case of a configuration of “block # 4, CRC bit # 4” is shown. In this case, the code block # 1 has a configuration of “transport block # 1, CRC bit # 1, transport block # 2, CRC bit # 2”, and code block # 2 includes “transport block # 3, CRC bit # 2. Since the configuration is “bit # 3, transport block # 4, CRC bit # 4”, each code block is formed such that the CRC bit is located at the boundary.

  When the input data to the turbo decoding device is data as shown in FIG. 6A, the CRC bit is located at the boundary between the code blocks. Therefore, in the conventional turbo decoding device described above, the code block # 1 When data is turbo-decoded, every time one decoding process is completed, an error is caused in transport block # 1 and transport block # 2 that are decoded information bits using CRC bit # 1 and CRC bit # 2. If there is no error, the decoding process is terminated, and if an error is detected, the decoding process can be repeated.

  In FIG. 6B, the input data to the turbo decoding device is “transport block # 1, CRC bit # 1, transport block # 2, CRC bit # 2, transport block # 3, CRC bit # 3”. The case of configuration is shown. In this case, the code block # 1 has a configuration of “transport block # 1, CRC bit # 1, most of transport block # 2,” and code block # 2 includes “remaining portion of transport block # 2, CRC. Since the configuration is “bit # 2, transport block # 3, CRC bit # 3”, each code block has a configuration in which no CRC bit is located at the boundary.

  As described above, when the input data to the turbo decoding device is data as shown in FIG. 6B, the CRC bit is not located at the boundary between the code blocks. Even if error detection is performed using CRC bit # 1 every time decoding processing is completed, it cannot be detected whether or not there is an error in the information bits of transport block # 2. Therefore, in decoding of code block # 1, if no error is detected at the time when decoding processing is performed a certain number of iterations, the decoding process of code block # 1 is terminated, and then the decoding process is performed on code block # 2. Will be performed. However, if all the errors of the transport block # 2 are not corrected in the decoding process of the code block # 1, the error will not be corrected even if the decoding process of the code block # 2 is repeated. It happens that the quality is degraded.

  FIG. 6C shows a case where the input data to the turbo decoding device has a configuration of “transport block # 1, CRC bit # 1”. In this case, the code block # 1 has a configuration of “slightly more than half of the transport block # 1”, and the code block # 2 has a configuration of “the remaining half of the transport block # 1, CRC bit # 1”. A code block that does not include CRC bits is formed.

  In this way, when the input data to the turbo decoding device is data as shown in FIG. 6 (c), there is no CRC bit in the code block # 1, so the conventional turbo decoding device described above has an error. Detection cannot be performed, and repetitive control by error detection cannot be performed. Therefore, in the conventional turbo decoding device, the decoding process is repeatedly performed a predetermined number of times, and there is a problem that the processing time is increased by performing the extra decoding process even though the error is sufficiently corrected. .

  The present invention has been made in view of the above point, and has improved the decoding capability in turbo decoding, optimized the number of times of turbo decoding, and reduced the processing time, and turbo decoding. It aims to provide a method.

  In order to solve such a problem, a turbo decoding device according to the present invention is a turbo decoding device that repeatedly performs error correction decoding on a coded sequence obtained by performing error detection coding and error correction coding on information bits. In a case where an error detection code is included in at least one code block of n (n ≧ 2) code blocks that are data units, n code blocks that perform iterative decoding processing of each of the n code blocks in parallel A turbo decoding means, a detection means for detecting the presence or absence of an error remaining in the decoding result based on an error detection code included in a decoding result of error correction decoding in the n turbo decoding means, and an error detection result of the detection means In response, iterative control means for controlling whether the n turbo decoding means continuously perform or stop the iterative decoding process; A configuration that includes.

  According to this configuration, since transport blocks straddling between code blocks can also be decoded simultaneously, transport blocks straddling between code blocks even when no error detection code is located at the boundary between code blocks As a result, it is possible to improve the correction capability and improve the signal quality. In addition, since any one of the n code blocks has an error detection code, even if there is a code block that does not include the error detection code, iterative control using error detection can be performed. Therefore, it is possible to optimize the number of repetitions of the decoding process, and to reduce the processing time without degrading the signal quality.

  The turbo decoding device according to the present invention is the above-described invention, wherein in the above invention, the memory for storing the decoding results of the n turbo decoding means and the control for giving the decoding results stored in the memory to the detecting means to perform error detection Means.

  According to this configuration, iterative decoding processing for n code blocks can be stably performed.

  The turbo decoding device according to the present invention is turbo decoding means for repeatedly performing error correction decoding on a coded sequence obtained by performing error detection coding and error correction coding on information bits, and is a code block 2 which is a decoding data unit. In the case where an error detection code is included in at least one code block, two turbo decoding means for performing iterative decoding processing of each of the two code blocks in parallel, and one of the two turbo decoding means A memory for storing a decoding result of error correction decoding, and a selection unit for selecting one of the decoding result of the error correction decoding in the other of the two turbo decoding units and the decoding result output from the memory And detecting the presence / absence of errors remaining in the decoding result based on the error detection code included in the decoding result output by the selection means Output means, iterative control means for controlling whether the two turbo decoding means continue or stop the iterative decoding process according to the error detection result of the detecting means, and the two turbo decoding means During the period when the other of the means is performing the iterative decoding process, the selection means selects the decoding result of the error correction decoding in the other of the two turbo decoding means, and then the decoding means outputs from the memory to the selection means And a control means for selecting a result.

  According to this configuration, iterative decoding processing is performed for two code blocks, the decoding result is stored in a memory, error detection is performed on the stored decoding result, and iterative decoding processing is continued for two code blocks. The processing time can be reduced as compared with the case of controlling whether to stop.

  According to the turbo decoding method of the present invention, n (n ≧ 2) code blocks that are data units of turbo decoding in which error correction decoding is repeatedly performed on a coded sequence in which error detection coding and error correction coding are performed on information bits. When an error detection code is included in at least one of the code blocks, a step of performing the iterative decoding process for each of the n code blocks in parallel, and a decoding result of the iterative decoding process for each of the n code blocks Detecting whether there is an error remaining in the decoding result based on the error detection code included in the error detection code, and whether to repeatedly perform or stop the iterative decoding process for each of the n code blocks according to the error detection result And a step of performing the control.

  According to this method, transport blocks straddling between code blocks can be decoded simultaneously, so that transport blocks straddling between code blocks even when no error detection code is located at the boundary between code blocks. As a result, it is possible to improve the correction capability and improve the signal quality. In addition, since any one of the n code blocks has an error detection code, even if there is a code block that does not include the error detection code, iterative control using error detection can be performed. Therefore, it is possible to optimize the number of repetitions of the decoding process, and to reduce the processing time without degrading the signal quality.

  In the turbo decoding method according to the present invention, in the above invention, the decoding result of the iterative decoding process for each of the n code blocks is temporarily stored in a memory, and then the error detection is performed on the decoding result stored in the memory. The process of making it include.

  According to this method, iterative decoding processing for n code blocks can be stably performed.

  According to the turbo decoding method of the present invention, at least one code of two code blocks that are data units of turbo decoding that repeatedly performs error correction decoding on an encoded sequence in which error detection coding and error correction coding are performed on information bits. When an error detection code is included in a block, the decoding result is obtained in a step in which the iterative decoding process for each of the two code blocks is performed in parallel and a period in which the iterative decoding process is performed for one of the two code blocks. Performing error detection for the two code blocks in parallel, storing the decoding result of error correction decoding in the other of the two code blocks in a memory, and when the iterative decoding process for one of the two code blocks is completed, A step of performing error detection on a decoding result stored in the memory; and the two code blocks. A step of controlling whether to repeatedly perform or stop the iterative decoding process for each of the two code blocks according to the error detection result of the decoding result of error correction decoding in a block. I made it.

  According to this method, iterative decoding processing is performed on two code blocks, the decoding result is stored in a memory, error detection is performed on the stored decoding result, and iterative decoding processing is continued for two code blocks. Compared to controlling whether to stop, the processing time can be reduced, and the memory capacity can be reduced.

  According to the present invention, it is possible to improve the decoding capability in turbo decoding, optimize the number of times turbo decoding is repeated, and reduce the processing time.

  The essence of the present invention is that a plurality of turbo decoders are provided in parallel so that each code block can be decoded simultaneously, and transport blocks straddling code blocks even when no CRC bit is located at the code block boundary. In addition, it is possible to optimize the number of repetitions of decoding processing by using error detection in a code block having CRC bits even when a code block having no CRC bits is included. is there.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a turbo decoding apparatus according to Embodiment 1 of the present invention. In the first embodiment, a configuration example is shown in which two turbo decoders are provided in parallel, assuming that input data is divided into two code blocks as shown in FIGS. Has been.

  That is, the turbo decoding device shown in FIG. 1 includes a turbo decoder 101A that performs turbo decoding on input data that is code block # 1, a turbo decoder 101B that performs turbo decoding on input data that is code block # 2, and a turbo decoder A hard decision unit 102A that converts a soft value output from the decoder 101A into a hard value of “0” or “1”, and a soft value output from the turbo decoder 101B is a hard value of “0” or “1”. A hard discriminator 102B for converting the data into the memory 103, a memory 103 for storing the decoded information bits, and a memory control for controlling access to the memory 103 when the hard values output from the hard discriminators 102A and 102B are stored in the memory 103. Circuit 104, error detector 105 for performing error detection using CRC for the decoded information bits stored in memory 103, and error detector Based on the detection result of 05, the iterative control circuit 106 controls whether the turbo decoders 101A and 101B continuously perform the iterative decoding process, the turbo decoders 101A and 101B, the memory control circuit 104, and the error detector 105. And a control circuit 107 for controlling.

  Next, the operation of the turbo decoding device configured as described above will be described with reference to FIGS. FIG. 2 is a flowchart for explaining the operation of the turbo decoding device shown in FIG. In FIG. 2, when received data is input (step ST201), the turbo decoding device is activated (step ST202), and the turbo decoders 101A and 101B start decoding processing in parallel (step ST203).

  As a decoding algorithm in the turbo decoders 101A and 101B, a SOVA (Soft Output Viterbi Algorithm), a MAP (Maximum A Posteriori Probability decoding) algorithm, or the like is used.

  The soft values sequentially output while the turbo decoders 101A and 101B perform the decoding process are converted into hard values by the hard discriminators 102A and 102B and input to the memory control circuit 104, respectively. In parallel, the control circuit 107 generates a control signal from the data length of the input data and supplies it to the memory control circuit 104. The memory control circuit 104 writes each hard value output from the hard decision devices 102A and 102B to a predetermined address of the memory 103 generated based on the control signal from the control circuit 107 while controlling the write timing to the memory 103 ( Step ST204).

  The control circuit 107 determines whether or not the turbo decoders 101A and 101B have finished the decoding process by using a counter included therein (step ST205). If the decoding process has not been finished (step ST205: NO) Returning to step ST204, control is performed to continue writing hard values obtained by decoding code block # 1 and code block # 2 into the memory 103.

  When the turbo decoders 101A and 101B complete the decoding process (step ST205: YES), the control circuit 107 indicates that all the hard values obtained by decoding the code block # 1 and the code block # 2 are stored in the memory 103. Recognize and activate the error detector 105 (step ST206). At the same time, the memory control circuit 104 generates a read address of the memory 103 based on the control signal output from the control circuit 107, performs reading, and inputs the read address to the error detector 105.

  Thus, the error detector 105 performs error detection on the hard values obtained by decoding the code block # 1 and the code block # 2 stored in the memory 103. When the error detector 105 ends the error detection process (step ST207: YES), the error detector 105 repeatedly outputs a signal indicating whether or not an error is detected to the control circuit 106.

  The iterative control circuit 106 monitors whether or not an error is detected by the error detector 105 (step ST208). If an error is detected (step ST208: NO), the two turbo decoders 101A and 101B are detected. Is activated to resume the decoding process (step ST209). As a result, the decoding process (steps ST204 to ST208) is repeated again.

  If no error is detected in all the transport blocks included in code block # 1 and code block # 2 (step ST208: YES), repetition control circuit 106 stops the processes of turbo decoding apparatuses 101A and 101B. (Step ST210). At that time, the hard value stored in the memory 103 is the final decoding result.

  As described above, according to the first embodiment, since the code block is decoded by the two turbo decoders, in the input data to the turbo decoding device, as shown in FIG. Even when the CRC bit is not located at the boundary between the code blocks, the correction capability for the transport block straddling the code blocks can be improved, and the signal quality can be improved.

  Further, in the input data to the turbo decoding apparatus, as shown in FIG. 6C, even when there is a code block that does not include CRC bits, error detection using a code block that includes CRC bits is used. Since iterative control can be performed, the number of repetitions of the decoding process can be optimized, and the processing time can be reduced without degrading the signal quality. This point will be specifically described with reference to FIGS. 3 (a) and 3 (b).

  FIG. 3A: In the conventional turbo decoding device, when the CRC block is not included in the code block, the decoding process cannot be repeatedly controlled using error detection, so that the code block does not include the CRC bit. For # 1, it was necessary to perform iterative decoding processing n times, which is a predetermined maximum number of iterations.

  FIG. 3B: In the turbo decoding device according to the first embodiment, CRC bits of data input to the turbo decoder 101A are included in the input data of the turbo decoder 101B (see FIG. 6C). Therefore, the processing of the code block # 1 that does not include the CRC bits can be terminated when no error is detected, and the number of repetitions of the decoding processing can be optimized, thereby reducing processing time. Is possible.

  In the case of input data as shown in FIG. 6A in which CRC bits are located at the boundary between code blocks, the turbo decoder 101A and the turbo decoder 101B may be used to perform processing in parallel. Alternatively, the decoding process may be sequentially performed on each code block using only the turbo decoder 101A or the turbo decoder 101B.

  Here, in the first embodiment, the input data in which the code block is divided into two and the CRC bit is present in at least one of the code blocks is assumed. Therefore, the configuration has two turbo decoders. In the case of input data in which n blocks are divided and CRC bits are present in any code block, the same iterative control can be performed if the configuration has n turbo decoders.

(Embodiment 2)
FIG. 4 is a block diagram showing the configuration of the turbo decoding apparatus according to Embodiment 2 of the present invention. In FIG. 4, the same or equivalent components as those shown in FIG. 1 are denoted by the same reference numerals. Here, the description will focus on the parts related to the second embodiment.

  As shown in FIG. 4, in the turbo decoding device according to the second embodiment, in the configuration shown in FIG. 1, a memory control circuit 401 is provided instead of the memory control circuit 104, and error detection is performed instead of the error detector 105. 402, a control circuit 403 is provided instead of the control circuit 107, and a selector 404 is added between the memory 103 and the error detector 402.

  The output of the hard discriminator 102A is input to the memory control circuit 401 and is one input of the selector 404. The other input of the selector 404 is a hard value read from the memory 103 (an output of the hard discriminator 102B).

  That is, the memory control circuit 401 performs control to write the output of the hard decision unit 102A and the hard decision unit 102B into the memory 103 and control to read and output the output to the selector 404. The error detector 402 performs error detection on the hard value output from the selector 404. The control circuit 403 controls the selector 404 in addition to the turbo decoders 101A and 101B, the memory control circuit 401, and the error detector 402.

  Next, the operation of the turbo decoding device according to Embodiment 2 configured as described above will be described. In FIG. 4, turbo decoder 101A and turbo decoder 101B start decoding processing in parallel as in the first embodiment.

  The hard value for the code block # 1 output from the hard discriminator 102A is stored in the memory 103 via the memory control circuit 401 and is given to the selector 404. On the other hand, the hard value for the code block # 2 output from the hard discriminator 102 B is stored in the memory 103 via the memory control circuit 401.

  The selector 404 selects the hard value output from the hard decision unit 102A while the turbo decoder 101A is performing the decoding process according to the selection signal output from the control circuit 403, and the turbo decoder 101A ends the decoding process. Then, control is performed to select the hard value read from the memory 103.

  That is, the hard value output from the hard discriminator 102A is buffered in the memory 103, and sequentially input to the error detector 402 via the selector 404, and error detection processing is performed. If the input data is data as shown in FIGS. 3B and 3C, the error detection process cannot be completed with only the hard value obtained by decoding the code block # 1, and therefore the control circuit 403 Interrupts the process of the error detector 402 during the error detection process. The error detector 402 performs error detection calculation to the point where it can be calculated.

  Next, the control circuit 403 completes the hard error detection process for the code block # 1 decoded and output by the turbo decoder 101A, the turbo decoder 101B ends the decoding process, and stores the code block # 2 in the memory 103. When all the hard values are stored, the error detector 402 is activated, and the error detection process for the last transport block of the code block # 1 is performed halfway. Restart the detection process. When the error detection process ends, the error detector 402 repeatedly outputs a signal indicating whether or not an error has been detected to the control circuit 106.

  The iterative control circuit 106 stops the processing of the turbo decoders 101A and 101B if no error is detected for all the transport blocks included in the code block # 1 and the code block # 2. At that time, the hard value stored in the memory 103 is the final decoding result.

  Further, when an error is detected, the iterative control circuit 106 controls the turbo decoders 101A and 101B to continue the decoding process, and the iterative decoding process is performed subsequently. Thus, if no error is detected for all the transport blocks included in code block # 1 and code block # 2, the processes of turbo decoders 101A and 101B are similarly stopped.

  Note that even if the decoding process of the turbo decoder 101B is not completed and the hard values of the code block # 2 are not all stored in the memory 103, the hard error detection process for the code block # 1 is completed. In this case, the control circuit 403 may control the operation timing of the error detector 402 and the memory control circuit 401 to perform hard value error detection processing on the code block # 2.

  In addition, the error detection of the code block # 1 is performed in parallel with the decoding process of the code block # 1, and after the error detection process for the code block # 1 is completed, the hard value for the code block # 2 is continuously used for the code block # 2. Although the case of performing error detection is shown, conversely, error detection of code block # 2 is performed in parallel with the decoding processing of code block # 2, and after the error detection processing for code block # 2 is completed, code block # 1 is detected. It is also possible to configure such that error detection is continued for code block # 1 using the hard value.

  As described above, according to the second embodiment, error detection for a hard value obtained by decoding code block # 1 (or code block # 2) is not performed after being stored once in the memory. Since the decoding is performed in parallel with the decoding process of the decoder 101A (or the turbo decoder 101B), the following effects can be obtained in addition to the effects of the first embodiment.

  That is, since the hard-value error detection process for code block # 1 (or code block # 2) is performed in parallel with the decoding process for code block # 1 (or code block # 2), compared to the first embodiment. Processing time can be further reduced.

  The present invention performs processing time while ensuring a desired signal quality by performing an appropriate number of repetitions of decoding processing when CRC bits are not located at the boundaries between code blocks or when code blocks without CRC bits are included. It is suitable as a turbo decoding device that reduces

FIG. 1 is a block diagram showing a configuration of a turbo decoding device according to Embodiment 1 of the present invention. Flowchart for explaining the operation of the turbo decoding device shown in FIG. (A) is a figure explaining the processing time obtained with the conventional turbo decoding apparatus shown in FIG. 5, (b) is a figure explaining the processing time reduction effect obtained with the turbo decoding apparatus shown in FIG. Block diagram showing the configuration of a turbo decoding device according to Embodiment 2 of the present invention Block diagram showing a configuration example of a conventional turbo decoding device (A) is a configuration example (part 1) of data input to the turbo decoding device, (b) is a configuration example (part 2) of data input to the turbo decoding device, and (c) is a turbo decoding device. Of the data input to the (3)

Explanation of symbols

101A, 101B Turbo decoder 102A, 102B Hard decision unit 103 Memory 104, 401 Memory control circuit 105, 402 Error detector 106 Repetition control circuit 107, 403 Control circuit 404 Selector

Claims (6)

A turbo decoding device that repeatedly performs error correction decoding on a coded sequence obtained by performing error detection coding and error correction coding on information bits,
When an error detection code is included in at least any one of n (n ≧ 2) code blocks of a code block that is a decoding data unit, the iterative decoding process of each of the n code blocks is performed in parallel n Turbo decoding means,
Detecting means for detecting the presence or absence of an error remaining in the decoding result based on an error detecting code included in a decoding result of error correction decoding in the n turbo decoding means;
Turbo decoding comprising: iterative control means for controlling whether the n turbo decoding means continuously perform or stop the iterative decoding process according to an error detection result of the detecting means. apparatus.   2. A memory for storing the decoding results of the n turbo decoding means, and a control means for performing error detection by supplying the decoding results stored in the memory to the detecting means. The turbo decoding device according to 1. A turbo decoding device that repeatedly performs error correction decoding on a coded sequence obtained by performing error detection coding and error correction coding on information bits,
In the case where an error detection code is included in at least one code block of two code blocks that are decoding data units, two turbo decoding means for performing iterative decoding processing of each of the two code blocks in parallel;
A memory for storing a decoding result of error correction decoding in one of the two turbo decoding means;
Selecting means for selecting one of the decoding results of the error correction decoding in the other of the two turbo decoding means and the decoding result output from the memory;
Detecting means for detecting the presence or absence of errors remaining in the decoding result based on an error detecting code included in the decoding result output by the selecting means;
Repetitive control means for controlling whether the two turbo decoding means continue or stop the iterative decoding process according to the error detection result of the detecting means;
In a period in which the other of the two turbo decoding units is performing the iterative decoding process, the selection unit selects a decoding result of error correction decoding in the other of the two turbo decoding units, and then the selection unit A turbo decoding apparatus comprising: control means for selecting a decoding result output from the memory. At least one code block of n (n ≧ 2) code blocks that are data units of turbo decoding in which error correction decoding is repeatedly performed on a coded sequence in which error detection coding and error correction coding are performed on information bits When an error detection code is included in
Performing the iterative decoding process of each of the n code blocks in parallel;
Detecting the presence or absence of an error remaining in the decoding result based on an error detection code included in the decoding result of the iterative decoding process of each of the n code blocks;
And a step of controlling whether to repeatedly perform or stop the iterative decoding process for each of the n code blocks according to the error detection result.   5. The method according to claim 4, further comprising a step of temporarily storing a decoding result of the iterative decoding process for each of the n code blocks in a memory and then performing the error detection on the decoding result stored in the memory. The described turbo decoding method. An error detection code is included in at least one code block of two code blocks that are data units of turbo decoding in which error correction decoding is repeatedly performed on a coded sequence in which error detection coding and error correction coding are performed on information bits. In case
Performing iterative decoding of each of the two code blocks in parallel;
During the period when iterative decoding processing is performed on one of the two code blocks, error detection is performed on the decoding result in parallel, and the decoding result of error correction decoding on the other of the two code blocks is stored in the memory. Storing and performing error detection on the decoding result stored in the memory when the iterative decoding process for one of the two code blocks is completed;
A step of controlling whether the iterative decoding process of each of the two code blocks is continuously performed or stopped according to the result of the error detection of the decoding result of the error correction decoding in the two code blocks; The turbo decoding method characterized by including.

Images