JP2005294755A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of fully protecting a semiconductor chip laid on a wiring substrate and increasing a part mounting area on the wiring substrate. <P>SOLUTION: A wiring substrate 12 is provided with a semiconductor chip 11. The substrate has a pad electrically connected with the semiconductor chip 11. With a mold resin 13, the semiconductor chip 11 on the wiring substrate 12 is sealed. The resin is in a state in which a portion of the side surface thereof coincides with the side surface of the wiring substrate 12 and the other portion of the side surface thereof is formed inside the side surface of the wiring substrate 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a substrate, and is used, for example, in a semiconductor memory card.

  In recent years, a semiconductor memory card (hereinafter referred to as a memory card) has attracted attention as one of storage devices that record information using a semiconductor memory built in a card case, for example, a nonvolatile memory (for example, Patent Document 1).

  Some of these memory cards have a structure in which a wiring board (hereinafter referred to as a semiconductor device) on which a semiconductor chip is mounted is built in a card case. In a wiring board used for this structure, a mold resin is usually formed at the center of the wiring board. FIG. 4 shows the external shape of a conventional semiconductor device. 4A is a top view of the semiconductor device, FIG. 4B is a side view of the semiconductor device viewed from the side, and FIG. 4C is a side view of the semiconductor device viewed from the bottom.

  As shown in FIGS. 4A to 4C, the semiconductor device 100 includes a wiring board (interposer) 101 and a mold resin 102 formed at the center of the wiring board. A semiconductor chip (not shown) is placed on the wiring substrate 101 in the mold resin 102. Further, the wiring board 101 is formed with a notch 101R for direction identification.

  A layout of the frame substrate in the manufacturing process of the semiconductor device 100 is shown in FIG. In the manufacturing process of the semiconductor device 100, as shown in FIG. 5, a plurality (eight in this case) of semiconductor devices 100 are arranged on the frame substrate 103. Each semiconductor device 100 is supported by four support portions 104, and the other periphery is a slit 105. A resin injection gate 106 used when molding the mold resin 102 is formed on one support portion that supports the semiconductor device 100.

However, as shown in FIG. 4A, in the semiconductor device in which the mold resin 102 is formed only in the center of the wiring substrate 101, there is a problem that the semiconductor chip cannot be sufficiently protected, There may be a problem that the component mounting area is small.
JP 2003-108967 A

  The present invention has been made in view of the above circumstances, and provides a semiconductor device capable of sufficiently protecting a semiconductor chip mounted on a wiring board and further increasing the component mounting area on the wiring board. The purpose is to do.

  According to an embodiment of the present invention, a semiconductor chip, a wiring board on which the semiconductor chip is mounted and having a pad electrically connected to the semiconductor chip, and the semiconductor chip on the wiring board are sealed Then, a semiconductor device is provided that includes a mold resin in which a part of the side surface coincides with the side surface of the wiring board and the other part of the side surface is formed inside the side surface of the wiring board.

  According to the present invention, it is possible to provide a semiconductor device that can sufficiently protect a semiconductor chip mounted on a wiring board and can further increase a component mounting area on the wiring board.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  FIG. 1 shows an outline of a semiconductor device according to an embodiment of the present invention. 1A is a top view of the semiconductor device, FIG. 1B is a side view of the semiconductor device viewed from the side, and FIG. 1C is a side view of the semiconductor device viewed from the bottom.

  As shown in FIGS. 1A to 1C, the semiconductor device 10 includes a semiconductor chip 11 including a semiconductor memory (for example, a nonvolatile memory), a wiring substrate (interposer) 12, and a mold resin 13. The One (or a plurality) of semiconductor chips 11 are placed on one surface of the wiring board 12. The wiring board 12 has pads that are electrically connected to the semiconductor chip 11. Further, the wiring substrate 12 has a notch 12R for direction identification. In the top view shown in FIG. 1A, the semiconductor device 10 has a shape different from a rectangle (two corners adjacent to the rectangle are Cut shape). The mold resin 13 is formed on the wiring substrate 12 on which the semiconductor chip 11 is placed, and seals and protects the semiconductor chip 11.

  As shown in FIG. 1B, the side surface of the mold resin 13 coincides with the side surface of the wiring substrate 12 in two opposing sides of the semiconductor device 10. In other words, the side surface of the mold resin 13 and the side surface of the wiring substrate 12 are flush with each other in a pair of opposing sides. On the other hand, on the other side of the semiconductor device 10, the side surface of the mold resin 13 is disposed more inside than the side surface of the wiring substrate 12. As described above, in order to make the side surfaces of the mold resin 13 and the wiring substrate 12 coincide with each other, it is preferable to cut the mold resin and the wiring substrate at a time.

  A plating lead 14 is formed on the wiring board 12. The plating lead 14 is drawn from the wiring on the wiring board 12 and is used for performing electrolytic gold plating on a pad or a terminal on the wiring board 12. The wiring on the wiring board 12 from which the plating lead 14 is drawn out includes wiring connected to a pad electrically connected to the semiconductor chip 11. The plating lead 14 is disposed so as to avoid the notch 12R. In other words, the plating lead 14 is pulled out to the outer edge of the substrate other than the notch 12R without being cut at the notch 12R.

  In the semiconductor device having the above-described configuration, the end surface of the mold resin 13 is formed so as to coincide with the end surface of the wiring substrate 12 in a pair of opposing sides of the semiconductor device 10. The area covering the wiring substrate 12 is increased, the protection function of the semiconductor chip 11 can be improved, and the area on the wiring substrate 12 on which components such as the semiconductor chip can be mounted can be increased. The semiconductor device shown in FIG. 1 is incorporated into a substrate housing recess provided in a card case to constitute a memory card.

  FIG. 2 is a view showing a layout of the frame substrate in the manufacturing process of the semiconductor device of the embodiment. In this example, 12 semiconductor devices are obtained from one frame substrate 21. A total of twelve wiring boards 12 are arranged on the frame board 21, four in the row direction and three in the column direction. The notch 12R is formed by previously making a substrate slit (hole) 22 in the frame substrate 21.

  A plating lead 14 is drawn out from the wiring formed on the wiring board 12. The plating lead 14 is used for performing electrolytic gold plating on a pad or a terminal connected to the wiring on the wiring board 12. The plating lead 14 is disposed avoiding the substrate slit 22 (notch portion 12R). Further, the plating lead 14 is connected to the continuity test pad 24 through the plating lead wiring 23 formed so as to surround the twelve wiring boards 12.

  With this configuration, as shown in FIG. 2, all the plating leads 14 are connected to the continuity test pad 24 in the state of the frame substrate 21. Thereby, when the pads of the semiconductor chip 11 and the pads of the wiring substrate 12 are connected by wire bonding, the conductivity between these pads can be confirmed, and a connection failure in wire bonding can be detected. As a result, for example, in a manufacturing process of a multi-chip package including a plurality of semiconductor chips, it is possible to proceed to the next process without detecting a defect, such as mounting another semiconductor chip on a defective product without detecting a defective bonding of wire bonding. Sometimes. Yield loss in such a case can be reduced. In the conventional example shown in FIG. 5, since the slit 105 is formed in the frame substrate 103 except for the support portion 104, all the plating leads are connected to the continuity test pad in the state of the frame substrate even if the plating leads are provided. Can not be connected to.

  FIG. 3 shows a state in which the mold resin is formed on the frame substrate 21 shown in FIG. The plating lead 14 and the substrate slit 22 are omitted. Mold resin 13 is continuously formed on three wiring boards 12 arranged in the column direction. A resin injection gate 13 </ b> A used when the mold resin 13 is molded is formed at the tip of the mold resin 13. In this way, after the mold resin 13 is molded with a mold, the cut line 25 is cut by the blade device. Thereby, twelve semiconductor devices 10 are formed.

  A method for manufacturing the semiconductor device according to the embodiment will be described below.

  First, the semiconductor chip 11 is placed on the wiring board 12. Subsequently, the pads on the semiconductor chip 11 and the pads on the wiring substrate 12 are connected by wire bonding. Next, using the continuity test pad 24, it is inspected whether the pad on the semiconductor chip 11 and the pad on the wiring substrate 12 are electrically connected. After confirming that the pads are conducting, a mold resin 13 is formed on the wiring board 12 as shown in FIG. Thereafter, the cut line 25 on the frame substrate 21 is cut by a blade device. Thus, the semiconductor device 10 is manufactured.

  When the molding resin is formed only at the center of the wiring substrate as in the conventional example shown in FIG. 5, it is necessary to increase the distance between the individual semiconductor devices when arranging a plurality of semiconductor devices on the frame substrate in the manufacturing process. There is. For this reason, the problem that manufacturing efficiency was bad and it became disadvantageous on the cost side had arisen. In this embodiment, since the side surface position of the mold resin 13 and the side surface position of the wiring board 12 are made to coincide with each other in a pair of opposing sides, it is not necessary to increase the distance between individual semiconductor devices. A semiconductor device can be placed without leaving any space. Thereby, manufacturing efficiency can be improved and product cost can be reduced. That is, in the conventional example, since a space between mold dies is required, only eight semiconductor devices can be obtained from one frame substrate. In this embodiment, as shown in FIG. Since no space between the molds is required, 12 semiconductor devices can be obtained from one frame substrate. Therefore, the number of frames per frame substrate is increased, the manufacturing efficiency can be improved as compared with the conventional example shown in FIG. 5, and the product cost can be reduced.

  In addition, as in the conventional example, in a semiconductor device in which a mold resin is formed only in the center of the wiring substrate, the wire substrate cannot be subjected to electrical inspection (pass bonding inspection) on the frame substrate, and particularly a multi-chip package including a plurality of semiconductor chips. In this case, there was a problem that the yield decreased. In this embodiment, since all the plating leads can be connected to the continuity inspection pad, a pass bonding inspection can be performed, and a decrease in yield in the multichip package can be suppressed.

  The embodiment described above can be applied to, for example, an SD (Secure Digital) card, a mini SD (Secure Digital) card, a multimedia card, or an XD card.

  In addition, each of the above-described embodiments can be implemented not only independently but also in an appropriate combination. Furthermore, the above-described embodiments include inventions at various stages, and the inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in the embodiments.

(A) is a top view of the semiconductor device according to the first embodiment of the present invention, (b) is a side view of the semiconductor device viewed from the side, and (c) is a side view of the semiconductor device viewed from below. It is a figure which shows the layout of the frame board | substrate in the manufacturing process of the semiconductor device of the said embodiment. It is a figure which shows the state after mold resin formation in the manufacturing process of the semiconductor device of the said embodiment. (A) is a top view of a conventional semiconductor device, (b) is a side view of the semiconductor device viewed from the side, and (c) is a side view of the semiconductor device viewed from below. It is a figure which shows the state after mold resin formation in the manufacturing process of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Semiconductor chip, 12 ... Wiring board, 12R ... Notch part, 13 ... Mold resin, 14 ... Plating lead.

Claims (5)

A semiconductor chip;
A wiring board having a pad on which the semiconductor chip is mounted and electrically connected to the semiconductor chip;
Sealing the semiconductor chip on the wiring substrate, a part of the side surface thereof coincides with the side surface of the wiring substrate and the other part of the side surface is formed inside the side surface of the wiring substrate; and
A semiconductor device comprising: A semiconductor chip;
A wiring board having a pad on which the semiconductor chip is mounted and electrically connected to the semiconductor chip;
A mold formed on the semiconductor chip and on the wiring substrate, the side surfaces of the two opposing sides coincide with the side surfaces of the wiring substrate, and the other side surfaces of the mold are disposed on the inner side of the side surfaces of the wiring substrate. Resin,
A semiconductor device comprising:   A cutout portion is formed in the exposed wiring board where the side surface of the mold resin is formed inside the side surface of the wiring board, and the lead connected to the pad of the wiring board is at the cutout portion. 2. The semiconductor device according to claim 1, wherein the semiconductor device is pulled out to an outer edge of the substrate excluding the notched portion without being cut.   4. The semiconductor device according to claim 3, wherein the lead connected to the pad is a plating lead for applying electrolytic gold plating to the pad.   The semiconductor device according to claim 1, wherein the semiconductor chip includes a nonvolatile memory.

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