JP2005287063A - Digital video encoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital video encoder whose power consumption is reduced by improving its D/A converter part. <P>SOLUTION: D/A converters 21Y, 21U, 21V in the D/A converter part 2 convert a digital luminance signal Y<SB>D</SB>, a digital chroma signal C<SB>D</SB>and a digital composite signal V<SB>D</SB>generated by an encoder part 1 into an analog luminance signal Y<SB>A</SB>, an analog chroma signal C<SB>A</SB>and an analog composite signal V<SB>A</SB>, respectively. In the D/A converters 21Y, 21U, 21V, a constant current source is on/off-controlled depending on the input digital signals to output currents. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video encoder that generates an analog television signal from a digital primary color signal, and in particular, generates a digital television signal by digital signal processing and converts the generated digital television signal into an analog signal. The present invention relates to a digital video encoder.

A block diagram of the digital video encoder is shown in FIG. In the figure, an encoder unit 1 converts digital primary color signals R, G, and B into digital television signals (in this example, a luminance signal Y _D , a chroma signal (carrier color signal) C _D ), and a composite signal V _D. Three signals). The D / A converter 2 converts the luminance signal Y _D , chroma signal C _D , and composite signal V _D generated by the encoder unit 1 into an analog luminance signal Y _A , chroma signal C _A , and composite signal V _A , respectively. Output.

The D / A converter 2 is composed of three D / A converters, each of which converts a digital luminance signal Y _D , a chroma signal C _D , and a composite signal V _D (each 8 bits) into an analog luminance signal Y _A. , Converted into a chroma signal C _A and a composite signal V _A.

FIG. 7 shows the configuration of three D / A converters included in the D / A converter 2 in the conventional digital video encoder. In the _{figure, IN 7, IN 6, ...} , IN 0 is input, OUT is an output terminal, H is inverted _{circuit, CC 70, CC 60, ...} , CC 00 is a constant current source, T _71, T _72, T ₆₁ , T ₆₂ ,..., T ₀₁ , T ₀₂ are p-channel MOS type FETs (insulated gate type field effect transistors).

The connection relationship will be described. The input terminals IN ₇ , IN ₆ ,..., IN ₀ are connected to the gates of the transistors T ₇₁ , T ₆₁ ,..., T ₀₁ via the inverting circuit H, respectively, and the transistors T ₇₂ , T ₆₂ ,. , Connected to the gate of _T02 . A constant current source CC _70, CC _60, ..., the current input side of the CC ₀₀ are respectively connected to the power line L, whereas, the transistors T ₇₁ is the current output side, T _61, ..., the drain of T ₀₁ - together through the source they are connected in common to the output terminal OUT, and the transistors T _72, T _62, ..., the drain of T ₀₂ - is grounded through the source.

With the above configuration, the transistor _{T K1 (K = 7,6, ...} , 0, hereinafter the same) each pair and the transistor T _K2 includes an input terminal IN _7, IN _6, ..., the digital input to the IN ₀ television signals (luminance signal Y _D, the chroma signal C _D or composite signal V _D) in response to the transistor T _K1 is oN, to that transistor T _K2 is OFF, the transistor T _K1 is OFF, the transistor T _K2 If the output current of the constant current source CC _K0 is weighted, that is, depending on the bit position of the digital signal input to the input terminal IN _K , the constant current source CC _K0 If the current flowing through is appropriately set, a current corresponding to the digital television signal flows into the output terminal OUT. The current flowing out from the output terminal OUT is converted into a voltage by an external resistor R and supplied to the next stage circuit.

  Here, normally, the D / A converter 2 is designed to correspond to an amplitude of 1.25 V with a total load of 37.5Ω. That is, a current of 1.25 / 37.5≈33.3 mA is required for one D / A converter constituting the D / A converter 2. In the D / A converter, the current flowing out from each constant current source is switched between the outside and the inside. All constant current sources are always ON, and a current of 33.3 mA is supplied. It keeps flowing all the time. As a result, in the conventional digital video encoder, a current of 33.3 × 3≈100 mA was constantly consumed only by the D / A converter 2. For this reason, when the digital video encoder is used for a portable device, the portable device is required to have low power consumption, which is a very big problem.

  Accordingly, an object of the present invention is to provide a digital video encoder with reduced power consumption by improving the D / A converter.

  In order to achieve the above object, in the digital video encoder of the present invention, an encoder unit that generates a digital television signal from a digital primary color signal, and a D / A conversion unit that converts the digital television signal into an analog signal In a digital video encoder that generates a television signal by performing digital signal processing, the constant current source is ON / OFF controlled in accordance with the digital signal input by the D / A converter to output a current. It has a D / A converter to perform.

  As a specific example of such a D / A converter, a configuration in which a constant current source is connected only to an output terminal via a switching element, and the switching element is ON / OFF controlled in accordance with an input digital signal can be considered. .

  With the above configuration, a large current does not always flow. Further, the circuit configuration is simplified by reducing the number of transistors.

  The encoder unit generates three signals, a luminance signal, a chroma signal, and a composite signal, and the D / A conversion unit converts each of the luminance signal, the chroma signal, and the composite signal from a digital signal to an analog signal. When three D / A converters are provided, a switch circuit may be provided that switches to a mode in which a predetermined one of the three D / A converters is set to a non-operating state according to an external input.

  With the above configuration, in a certain mode, there is a D / A converter that is not operating in the D / A converter, that is, does not consume power, thus greatly contributing to the reduction of power consumption. become.

  According to the digital video encoder of the present invention, a large current does not always flow in the D / A converter, and power consumption is greatly reduced. In addition, since the circuit configuration is simplified in the D / A converter, the chip size is reduced and the cost is reduced.

  In addition, according to the digital video encoder of the present invention, there is a mode in which a D / A converter that consumes more power than the encoder unit is in a non-operating state, so that power consumption can be further greatly reduced. Can do.

  Therefore, the digital video encoder of the present invention is very effective when used for a portable device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram of a digital video encoder according to the first embodiment of the present invention. First, the encoder unit 1 will be described. Reference numeral 11 denotes a digital luminance signal Y _D , an RY signal (V signal), and a BY signal (U signal) based on the three digital primary color signals R, G, and B inputted to the digital video encoder. Is a luminance signal and color difference signal forming circuit. 12 is an addition that adds a composite synchronization signal SYNC composed of various synchronization signals such as horizontal / vertical synchronization signals that are externally input or generated internally to the luminance signal Y _D output from the luminance signal and color difference signal forming circuit 11. It is a vessel.

Reference numeral 14 denotes a color carrier (color subcarrier) SC that is externally input or internally generated based on the RY signal and BY signal output from the luminance signal and color difference signal forming circuit 11 and then output. Modulation circuit. Note that the frequency f _SC of the color carrier SC, in the NTSC system in the f _SC ≒ 3.58 MHz, PAL system is f _SC ≒ 4.43 MHz.

15 is an adder for inserting a color carrier SC to the color burst position of the signal output from the modulation circuit 14 as a color burst signal, to form a chroma signal C _D digital. 16 denotes an adder for forming a digital composite signal V _D by adding the luminance signal Y _D and a chroma signal C _D to the adder 13 outputs.

Next, the D / A conversion unit 2 will be described. The D / A converter 2 includes three D / A converters 21Y, 21C, and 21V. The digital luminance signal Y _D , the chroma signal C _D , and the composite signal V _D that are respectively input are converted into an analog luminance signal Y. _A , chroma signal C _A , and composite signal V _A are converted.

The configuration of the D / A converters 21Y, 21C, and 21V is shown in FIG. In the figure, T, T ₇ , T ₆ ,..., T ₀ and T _C7 , T _C6 ,..., T _C0 are p-channel MOS type FETs, CC is a constant current source, C is a capacitor, and H is inverted. Circuit.

Referring to the connection relation, the transistor T is with has a is connected to a gate and a drain diode-connected, transistor T and the transistor T _7, T _6, ..., gates of the respective T ₀ is connected . The drain of the transistor T is connected to the current inflow side of the constant current source CC, and the current outflow side of the constant current source CC is grounded. The sources of the transistors T and T ₇ , T ₆ ,..., T ₀ are connected to the power supply line L. That is, the transistors T and the transistor T _7, T _6, ..., the constant current source and each of _{T 0 CC 7, CC 6,} ..., to form a CC _0.

The currents flowing through the constant current sources CC ₇ , CC ₆ , CC ₅ , CC ₄ , CC ₃ , CC ₂ , CC ₁ , CC ₀ are 128 times, 64 times, 32 times the reference current flowing through the constant current source CC, respectively. , 16 times, 8 times, 4 times, 2 times, and 1 time, the characteristics of the transistor T and the transistors T ₇ , T ₆ ,..., T ₀ are set. The constant current source CC _7, CC _6, ..., the transistor T and the transistor T _7, T ₆ constituting a CC _0, ..., a connection point of the gates of the respective T ₀ is connected to the terminal N, Terminal N is grounded via capacitor C.

A constant current source CC _7, CC _6, ..., the current output side of the CC _0, i.e., the transistor T _7, T _6, ..., respectively drains of T ₀ is the transistor T _C7, T _C6, ..., the drain of T _C0 - Source It is commonly connected only to the output terminal OUT via the gap. Input terminal _{IN 7, IN 6, ...,} IN 0 respectively through the inverting circuit H transistors T _C7, T _C6, ..., it is connected to the gate of T _C0.

In this embodiment, the high level of the digital signal input to the input terminals IN ₇ , IN ₆ ,..., IN ₀ is 5.0V, the low level is 0V, and the high level of the inverting circuit H The output is 5.0V and the low level output is 3.0V. The transistors T _C7 , T _C6 ,..., T _C0 are turned on when the low level output of the inverting circuit H is applied to the gate, and turned off when the high level output of the inverting circuit H is applied to the gate. It is set to be.

With the above configuration, transistors _{T C7, T C6, ...,} T C0 is the input terminal IN _7, IN _6, ..., so each ON / OFF is switched in response to the digital signal inputted to IN _0, the constant current source CC _7, CC _6, ..., since the weighting have been made as described above in CC _0, digital television signals (luminance signal Y _D, the chroma signal C _D or composite signal V _D) the top-level By sequentially inputting from the bits to the input terminals IN ₇ , IN ₆ ,..., IN ₀ , a current corresponding to the digital television signal flows into the output terminal OUT. The current flowing out from the output terminal OUT is converted into a voltage by an external resistor R and supplied to the next stage circuit.

Here, D / A converter 21Y in the D / A converter 2 having the digital video encoder of the present embodiment, 21C, the 21V, the constant current sources CC _7, CC _6, ..., current flowing out of CC ₀ There one transistor T _C7 respectively, T _C6, ..., is controlled by T _C0, each in response to an input digital signal constant current source CC _7, CC _6, ..., so switches are oN / OFF of the CC _0, A large current does not always flow and power consumption is greatly reduced. Specifically, the black output is 20% of the current (about 7 mA), the white output is 70% of the current (about 23 mA), and the average power consumption is about 50% of the conventional. Experimental results have been obtained.

  Conventionally, two transistors are provided for one constant current source. In the present embodiment, one transistor is provided for one constant current source, and the number of transistors is reduced. Since the circuit configuration is simplified, the chip size is reduced and the cost is reduced.

Incidentally, the constant current sources CC _7, CC _6, ..., becomes to be a CC ₀ ON / OFF operation, the constant current sources CC _7, CC _6, ..., the transistor T and a transistor T _C7 constituting the CC ₀ , T _C6 ,..., T _C0 are grounded at the connection point between the gates through a capacitor C to absorb transient distortion such as overshoot and undershoot, and the output signal is changed when the input signal changes. Prevents noise from entering.

  In the D / A converter shown in FIG. 2, the ON / OFF control of the constant current source is performed by controlling the current flowing out from the constant current source. Instead of doing this, the constant current source is controlled. This may be done by controlling the current flowing into the source.

An example of the configuration of the D / A converter thus configured is shown in FIG. In this figure, T ′, T ₇ ′, T ₆ ′,..., T ₀ ′, and T _C7 ′, T _C6 ′,..., T _C0 ′ are n-channel MOS type FETs, and T ₁₀ and T ₂₀ are A p-channel MOS FET, CC ′, is a constant current source. The parts corresponding to those of the D / A converter shown in FIG.

A reference current is supplied from a constant current source CC ′ to the drain of the diode-connected transistor T ′. Transistor T 'and the transistor _{T 7', T 6 ',} ..., T 0' respectively in the constant current source CC ₇ of ', CC _6', ..., form a CC ₀ '. The constant current source _{CC 7 ', CC 6',} ..., ' the current input side of, i.e., the transistor _{T 7' CC 0, T 6} ', ..., T 0' drain of each transistor T _C7 ', T _C6 ,..., T _C0 ′ via the drain-source, the input side of the current-flow-type current mirror circuit CM formed by the diode-connected transistor T ₁₀ and the transistor T ₂₀ , that is, the transistor T ₁₀ Commonly connected only to the drain. Input terminal _{IN 7, IN 6, ...,} IN 0 each transistor _{T C7 ', T C6',} ..., is connected to the gate of T _C0 '. Output terminal an output side of the current mirror circuit CM, i.e., is connected to the drain of the transistor T _20.

With the above configuration, similarly to the D / A converter shown in FIG. 2, the constant current source _{CC 7 ', CC 6',} ..., if by weighting the CC ₀ ', the input from the most significant bit first A current corresponding to the digital television signal input to the terminals IN ₇ , IN ₆ ,..., IN ₀ flows into the output terminal OUT. The current flowing out from the output terminal OUT is converted into a voltage by an external resistor R and supplied to the next stage circuit.

  In this D / A converter, the current flowing into the constant current source is controlled so that the constant current source is ON / OFF controlled, so that the control can be performed with an n-channel transistor. Therefore, in order to realize the same operation speed, if an n-channel transistor is used, a smaller current and a smaller transistor size are required than when a p-channel transistor is used, and thus the D / A converter 2 is configured. In the D / A converter, the power consumption can be further reduced, and the current mirror circuit CM is added, but the size of the transistor required by the number of bits of the input digital signal can be reduced. Therefore, the power consumption and size of the D / A converter 2 can be further reduced.

In addition, by increasing the emitter area of the transistor T ₂₀ on the output side of the current mirror circuit CM, a current that is n times (n> 1) the current that flows out from the input side flows out from the output side. If set appropriately, the output current can be maintained at a predetermined level even if the current flowing through the constant current sources CC ₇ ′, CC ₆ ′,..., CC ₀ ′ is reduced. The required amplitude can be obtained without modification.

  Next, FIG. 4 shows a circuit block diagram of a digital video encoder according to the second embodiment of the present invention. In the figure, SW1 is a switch circuit composed of semiconductor switches. In addition, the same code | symbol is attached | subjected to the part same as the said embodiment, and description is abbreviate | omitted.

The switch circuit SW1 is turned on / off in response to a signal externally input to the mode switching terminal K. In the D / A converter 2, the drive voltage V _CC is directly supplied to the power line L of the D / A converter 21V, but the switch circuit is connected to the power lines L of the D / A converters 21Y and 21C. A drive voltage V _CC is supplied via SW1.

  With the above configuration, by supplying a signal for turning off the switch circuit SW1 to the mode switching terminal K, the D / A converters 21Y and 21C are turned off (non-operating state) in the D / A converter 2. In this way, the D / A converter 2 is turned off, that is, it is possible to switch to a mode in which there is a D / A converter that does not consume power, whereby each D / A converter has low power consumption. Although the power consumption is higher, the power consumption is still larger than that of the encoder unit 1, so that the power consumption of the digital video encoder is further greatly reduced.

An apparatus that inputs an analog television signal may process a luminance signal Y _A and a chroma signal C _A , or may process a composite signal V _A, and an apparatus that inputs all three signals above. , is selected or not to process either the signal according to the function, the composite signal V _a, since one of the luminance signal Y _a and the chroma signal C _a is in the rejection, the signal to be processed by apparatus If the mode is appropriately switched accordingly, there is no problem even if the above mode is set.

As shown in FIG. 5, instead of the switch circuit SW1, a switch circuit SW2 having three terminals a, b and c is provided, and the terminal a is used as a drive voltage V _CC for the D / A converters 21Y, 21C and 21V. In addition, the terminal b may be connected to the power supply line L of the D / A converter 21Y and the D / A converter 21C, and the terminal c may be connected to the power supply line L of the D / A converter 21V.

In this way, if either the terminal ab or the terminal ac is brought into conduction according to the signal externally input to the mode switching terminal K, the luminance signal Y _A and the chroma signal C _A And a mode for outputting the composite signal _VA . In this case, since one or two of the three D / A converters are always OFF in the D / A conversion unit 2, a further significant reduction in power consumption can be reliably realized. Is done.

These are the block diagrams of the digital video encoder which is 1st Embodiment of this invention. These are figures which show the structure of the D / A converter which a D / A conversion part has in the digital video encoder which is 1st Embodiment of this invention. These are figures which show another structure of the D / A converter which a D / A conversion part has. These are the circuit block diagrams of the digital video encoder which is 2nd Embodiment of this invention. These are figures which show the example different from what was shown as 2nd Embodiment about the switching of operation | movement / non-operation of three D / A converters which a D / A conversion part has. FIG. 3 is a block diagram of a digital video encoder. These are figures which show the structure of the D / A converter which a D / A conversion part has in the conventional digital video encoder.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Encoder part 2 D / A conversion part 11 Luminance signal and color difference signal formation circuit 12 Adder 14 Modulation circuit 15 Adder 16 Adder 21Y, 21C, 21V D / A converter SW1, SW2 Switch circuit

Claims (8)

In a D / A converter for inputting a digital signal having n digits (n is a natural number) and converting the inputted digital signal into an analog signal,
A constant current source for reference current to which a first DC voltage is applied to one end;
A second DC voltage having a voltage value different from the first DC voltage is applied to the first electrode, the second electrode is connected to the other end of the constant current source for reference current, and the second electrode and the control electrode are A reference-current MOS FET that is electrically connected to form a diode connection;
Each control electrode is connected to a connection point between the control electrode and the second electrode of the reference current MOS FET, and the second DC voltage is applied to each first electrode. First to m-th constant current MOS type FETs having the same polarity as m (m is a natural number),
The first DC voltage is applied to one end, and the other end is connected to the control electrode and the second electrode of the reference current MOS type FET, and the control electrodes of the first to m-th constant current MOS type FETs. A capacitor connected to the point;
The first electrodes are connected to the second electrodes of the first to m-th constant current MOS type FETs, and have the same polarity as the reference current MOS type FETs to which the second electrodes are electrically connected. First to m-th switching MOS FETs;
An output terminal connected to a connection point of each second electrode of the first to m-th switch MOS type FETs,
In the first to mth constant current MOS type FETs, the current value flowing through the kth (k is a natural number less than or equal to m) constant current MOS type FET is set to 2k− of the current value flowing through the reference current MOS type FET. 1x and
Inputting the k-th digit signal of the digital signal from the control electrode of the k-th switch MOS type FET among the first to m-th switch MOS type FETs is performed for all digits. D / A converter. The D / A converter according to claim 1, further comprising a resistor having one end connected to the output terminal and the other DC voltage applied to the other end. The reference current MOS FET having the first DC voltage applied to the first electrode and the second electrode connected to a connection point of the second electrodes of the first to m-th switching MOS FETs. A first current mirror MOS type FET having the same polarity as
A first electrode connected to a first electrode of the first current mirror MOS type FET, and a control electrode connected to a control electrode of the first current mirror MOS type FET; A second current mirror MOS FET of the same polarity,
The control electrode and the second electrode of the first current mirror MOS type FET are electrically connected,
2. The D / A converter according to claim 1, wherein a second electrode of the second current mirror MOS type FET is connected to the output terminal. 3. 4. The D / A converter according to claim 3, further comprising a resistor having one end connected to the output terminal and the other DC voltage applied to the other end. Comprising first to m-th inverters connected to the control electrodes of the first to m-th switch MOS type FETs,
The reference current MOS type FET is a p-channel MOS type FET,
The k-th switch MOS is supplied to the k-th digit signal (k is a natural number equal to or less than m) of the digital signal divided for each digit via the k-th inverter among the first to m-th inverters. 5. The D / A converter according to claim 1, wherein the D / A converter is input to a control electrode of a type FET. 5. The D / A converter according to claim 1, wherein the reference current MOS type FET is an n-channel MOS type FET. An encoder unit that generates a digital television signal from a digital primary color signal; and a D / A conversion unit that converts the digital television signal into an analog signal. In the digital video encoder to generate,
A digital video encoder, wherein the D / A converter is constituted by the D / A converter according to any one of claims 1 to 6. The encoder unit generates three signals: a luminance signal, a chroma signal, and a composite signal,
The D / A conversion unit is composed of three D / A converters for converting each of the luminance signal, chroma signal, and composite signal from a digital signal to an analog signal,
8. The digital video encoder according to claim 7, further comprising a switch circuit that switches to a mode in which a predetermined one of the three D / A converters is set to a non-operating state according to an external input.

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