JP2005286952A - Semiconductor testing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost of a semiconductor testing device, by simplifying data control when a lot of data is transmitted by using two or more serial transmission devices. <P>SOLUTION: In the semiconductor testing device, transmission control units 2<SB>1</SB>, 2<SB>2</SB>, receive control units 5<SB>1</SB>, 5<SB>2</SB>constitute a data transfer device. A transmission path control line 14 generated from the receive control unit 5<SB>1</SB>is concentrated to the receive control unit 5<SB>2</SB>as a master receive control unit and turned, along with a result of self control unit at the response signal transmission control circuit 12<SB>2</SB>of the receive control unit 5<SB>2</SB>, to the master control unit 2<SB>2</SB>on the transmission side through a two way response control signal line 6. From a response signal receive control circuit 9<SB>2</SB>on the transmission side, it is distributed to two or more control units on the transmission side by using a transfer path control line 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transmission technique, and more particularly to a technique effective when applied to transmission of image data in a semiconductor inspection apparatus.

  In general, in the inspection of a pattern formed on a semiconductor wafer, an optical microscope or an electron microscope is applied to detect pattern images, and these images are processed to detect defects on the surface. The method is used.

  With the high integration of today's semiconductor integrated circuit devices, circuit patterns formed on semiconductor wafers are rapidly miniaturized. In semiconductor inspection devices such as semiconductor wafer appearance inspection devices and scanning electron microscopes, the required image processing capacity has been increasing year by year due to the miniaturization of semiconductors and the increased density of substrate wiring. The transmission capacity of acquired image data is increased, and a higher transmission speed is desired.

  In accordance with this, the technology used for the transmission path has also changed from parallel transmission to serial transmission (see, for example, Patent Document 1). Further, the acquired image data of the semiconductor inspection apparatus is characterized by flowing a large amount of data in one direction, and is described in Japanese Patent Application Laid-Open No. 8-251146 as a unidirectional serial transmission technique (Patent Document 2). .

There is also a technology called Camera Link, which describes that a large amount of data transmission is performed by using a plurality of serial data lines at once in the unidirectional serial data transmission technology (for example, non-patent). Reference 1).
JP 2002-223203 A JP-A-8-251146 “Camera Link Interface Standard Specification”, PULNiX America, Inc.

  However, the present inventor has found that the image data transfer technique in the appearance inspection apparatus as described above has the following problems.

  In order to transmit high-speed and large-capacity image data, it is common to use a method in which high-speed data transmission is performed using a serial transmission device, and at the same time, a plurality of serial transmission devices are used to increase the transmission path capacity. is there.

  When high-speed and large-capacity data transmission is performed using a large amount of serial transmission devices, transmission data loss due to noise or the like, and a shift in transmission timing due to the use of a large amount of serial transmission devices become problems.

  In order to solve this problem, the serial transmission device is provided with a high-speed data transmission line, and a control signal for controlling the transmission data is provided on each of the transmission side and the reception side.

  However, when data transmission is performed by combining a plurality of serial transmission devices, a large amount of the high-speed serial transmission lines and data control lines are wired, which complicates data control and reduces the cost of semiconductor inspection equipment. I will raise it.

  The object of the present invention is to solve the problems of increasing the number of transmission lines and control lines when transmitting a large amount of data using a plurality of serial transmission devices, and to realize efficient data transmission and data control. Thus, it is an object of the present invention to provide a technique that can simplify data control and keep the apparatus cost low.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor inspection apparatus according to the present invention includes first and second transmission control units that convert image data of parallel signals into serial signals, and parallel signals that are converted by the first and second transmission control units. A first and second reception control units for converting the received parallel signal image data into frame data, and a first transmission control unit for converting the input parallel signal image data into frame data; A transmission circuit that converts the frame data converted by the transmission data control unit into a serial signal and outputs the serial signal; and a response signal reception control unit that determines whether the image data is normally received based on the response signal. The first and second reception control units analyze a serial signal output from the transmission circuit into a parallel signal and a parallel signal converted by the reception circuit; Each of the first reception control units includes a reception data control response unit that analyzes whether or not the serial signal has been normally received and outputs a response signal generated based on the analysis result. The response signal output from the reception control unit is output to the first transmission control unit together with the response signal generated by the first reception control unit, and the first transmission control unit distributes the received response signal. , To the corresponding one or more second transmission / reception control units.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the semiconductor inspection apparatus according to the present invention, the response signal generated by the first and second reception control units is a throughput adjustment request for temporarily stopping transfer of serial signals by the first and second transmission control units. When the serial signals transferred from the first and second transmission control units overflow in the first and second reception control units, the first and second reception control units include a signal. The throughput adjustment request signal is output.

  In the semiconductor inspection apparatus according to the present invention, the response signals generated by the first and second reception control units include a synchronization control signal, and are transferred from the first and second transmission control units. Are output in synchronization with each other.

  Furthermore, in the semiconductor inspection apparatus according to the present invention, the response signal generated by the first and second reception control units includes a retransmission request signal, and the first and second reception control units receive the received data. Is determined to be normal, a retransmission request signal is output in the event of an abnormality, and a retransmission request is made to retransmit the data to the first and second transmission control units.

  The semiconductor inspection apparatus according to the present invention further includes setting signal storage means for storing the setting signal, and the first reception control section and the second reception control section based on the setting signal stored in the setting signal storage means. And switching between the first transmission control unit and the second reception control unit.

  The semiconductor inspection apparatus according to the present invention further includes a first printed wiring board on which the first and second transmission control units are mounted, and a second print on which the first and second reception control units are mounted. The first and second transmission control units and the first and second reception control units via a data transmission path provided between the first and second printed wiring boards. Connected.

  In addition, a semiconductor inspection apparatus according to the present invention includes a printed wiring board on which the first and second transmission control units and the first and second reception control units are mounted. The transmission control unit and the first and second reception control units are connected via a data transmission path formed on the printed wiring board.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since the control line between transmission and reception can be simplified to one system, data transmission and data control can be performed efficiently.

  (2) According to the above (1), it is possible to transmit a large amount of data at high speed while simplifying the configuration of the semiconductor inspection apparatus, and the cost of the semiconductor inspection apparatus can be greatly reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 is a block diagram of a semiconductor inspection apparatus according to an embodiment of the present invention, FIG. 2 is a flowchart showing an example of the operation of the semiconductor inspection apparatus of FIG. 1, and FIG. 3 is provided in the semiconductor inspection apparatus of FIG. 4 is a block diagram of the transmission control unit and the reception control unit, FIG. 4 is a flowchart showing an example of operations in the transmission control unit 2 and the reception control unit in FIG. 3, and FIG. 5 is provided in the semiconductor inspection apparatus in FIG. FIG. 6 is a flowchart showing an example of the operation of the data transfer apparatus shown in FIG. 5, FIG. 7 is a flowchart showing an example of control by a throughput adjustment instruction in the data transfer apparatus of FIG. 5, and FIG. FIG. 9 is a flowchart showing an example of data synchronization control in the data transfer apparatus of FIG. 5, and FIG. 9 is a control operation by a retransmission request in the data transfer apparatus of FIG. FIG. 10 is a block diagram showing an example of a master / slave combination in the data transfer apparatus of FIG. 5, and FIG. 11 shows another example of a master / slave combination in the data transfer apparatus of FIG. FIG. 12 is a block diagram, FIG. 12 is an explanatory diagram showing a configuration example of frame data used for data transfer of the semiconductor inspection apparatus of FIG. 1, and FIG. 13 is an example of transmission data encoding and reception data encoding in the data transfer apparatus of FIG. FIG. 14 is a block diagram showing an example in which a decoding circuit for performing error correction is provided, and FIG. 14 is a block diagram showing an example in which a failure control display unit for detecting a reception abnormality is provided in the data transfer apparatus of FIG.

  In the present embodiment, the semiconductor inspection apparatus includes, for example, an SEM (Scanning Electron Microscope) type visual inspection apparatus. As shown in FIG. 1, the semiconductor inspection apparatus includes a mirror body 71, an A / D converter 72, an image data distribution control unit 73, an image processing device 74, and a defect image display device 79.

The image data distribution control unit 73 includes transmission-side transmission control units 700 _{1 to} 700 _n, and the image processing device 74 includes an image data distribution control unit 75, image data processing units 78 _{1 to} 78 _n , and An overall control unit 780 and the like are included.

Image data distribution control unit 75, the receiving-side transmission control unit 710 ₁ ~710 _n, and is composed of a transmitting-side control unit 720 ₁ to 720 _n, the image data processing unit 78 ₁ to 78 _n, the receiving device controller Portions 730 _{1 to} 730 _n are provided.

  The operation of this semiconductor inspection apparatus will be described using the flowchart of FIG.

  First, in the mirror body 71, light (step S920) such as UV (Ultraviolet Radiation) light and DUV (Deep UV) light emitted from a light source installed on the upper surface of the inner surface is condensed into a slit shape by an aggregation lens (step S920). In step S921, the semiconductor wafer moving in a predetermined direction through the objective lens is irradiated (step S922).

  The light reflected from the circuit pattern formed on the semiconductor wafer is collected by the objective lens (step S923), and the image of the formed circuit pattern is captured by an image sensor such as a TDI sensor (step S924). Output image information.

  The A / D converter 72 takes in the image data from the optical system 71 (step S925), converts the analog amount into digital information (step S926), and stores the image data in the image memory (step S926). Step S927).

The digitized image data is divided and parallelized by the image data distribution control unit 73 (step S928), and from the transmission side transmission control units 700 _{1 to} 700 _n via the high-speed serial transmission path, the reception side transmission control unit 710 _1. Image data is transmitted to ˜710 _n and sent to the image processing device 74 (step S929).

In this case, the response signal of the receiving-side transmission control unit 710 ₁ ~710 _n goes through the receiving side control circuit between the response signal transmission path 760, it is aggregated to the master receiver-side transmission controller 710 _n, transmission and reception between the response signal therefrom The data is transmitted to the master transmission side transmission control unit 700 _n via the transmission line 740.

Response signal, from the transmission side transmission control unit 700 _n, via the transmitting-side control circuit between the response signal transmission line 750, is distributed to the transmission side transmission control unit 700 ₁ to 700 _n. The image processing device 74 distributes the divided image data to the image data processing units 78 _{1 to} 78 _n by the image data distribution control unit 75.

At this time, the image data distribution control unit 75 distributes the image data using the high-speed serial transmission lines 76 _{1 to} 76 _n , and the image data processing unit uses the response signal transmission lines 77 _{1 to} 77 _n to control the transmission result to the image data distribution control. Return it to the department.

The overall control unit 770 controls the A / D converter 72 based on the image information obtained from the mirror 71, further controls the image data distribution control unit 75, and further controls each of the image information data processing units 78 _{1 to} 78 _n. The image processing result obtained from the above is controlled to perform image integration processing (step S930), a defect image is output, and the defect image display device 79 displays the defect image (step S931). Here, regarding the image data distribution unit, the division starts from 1.

Figure 3 is a block diagram of a transmitting side control section 720 _1-720 transmission control section 2 provided on _n, and the reception side control section 730 _1-730 reception control section 5 provided in the _n.

  The transmission control unit 2 includes a transmission data control unit 7, a transmission circuit 8, and a response signal reception control unit 9. The reception control unit 5 includes a reception circuit 10, a data reception control unit 11, and a response signal transmission control unit 12.

  The operation processes of the transmission control unit 2 and the reception control unit 5 will be described with reference to the flowchart of FIG.

  First, transmission data 1 arrives at the transmission control unit 2 (step S901). The transmission data control unit 7 converts the data into frames, and passes the data to the transmission circuit 8 (step S902).

The transmission circuit performs parallel and serial conversion of data (step S903), and transmits data to the receiving unit 5 using the high-speed serial transmission path 3 (high-speed serial transmission path 76 ₁ in FIG. ₁ ) (step S904). At this time, the transmission data counter in the transmission control unit 2 is incremented by one (step S912).

  Subsequently, when receiving the serial signal, the receiving circuit 10 in the receiving unit converts it into parallel data (step S905), and outputs data from the received data output unit 4 (step S906).

  At the same time, the data received by the receiving circuit is sent to the reception data control unit 11, where the received data is analyzed (step S907), and when the data can be normally received, the response signal transmission control unit 12 is responded. Ask to output a signal.

The response signal transmission control unit 12 uses the response signal transmission path 6 (response signal transmission path 77 _{1 in} FIG. ₁ ) extending from the reception side apparatus to the transmission side apparatus, and transmits normal data reception to the transmission side (steps S908 and S909). ). The response signal reception control unit 9 counts up one reception data counter by the response signal sent from the receiving side (step S910).

  Here, the difference value between the transmission data counter and the reception data counter is inspected (step S911), and if it is equal to or greater than a certain value, an error is displayed (step S918) and the data transmission / reception is terminated (step S919).

  In the process of step S907, if the data is not normally received, there is no response signal from the receiving side, and the difference value between the transmission data counter and the reception data counter is checked (step S911). Then, error display is performed (step S918), and the data transmission / reception is terminated (step S919).

  FIG. 5 is a block diagram of a data transfer apparatus provided in the semiconductor inspection apparatus.

This data transfer apparatus is composed of transmission control units 2 ₁ to 2 _n and reception control units 5 _{1 to} 5 _n . The transmission control units 2 _{1 to} 2 _n are provided in the transmission side transmission control units 700 _{1 to} 700 _n , respectively, and the reception control units 5 _{1 to} 5 _n are provided in the reception side transmission control units 710 _{1 to} 710 _n , respectively. It has been.

FIG. 5 shows a data transfer apparatus including two transmission control units 2 ₁ and 2 ₂ and reception control units 5 ₁ and 5 ₂ for simplification.

This case, the reception control unit 5 ₁ a reception control section 5 ₂ and are connected at the receiving side between the signal transmission line 14, the transmission control unit 2 ₁ and the transmission control unit 2 ₂ and the transmitting side control signal transmission line 15 It is connected. As a result, the transmission path capacity is double that of FIG.

The basic operation of each part is the same as FIG. 3, the response signal generated from the reception control unit 5 ₁ is sent to the reception control section 5 _2, wherein the response signal and waiting processing line in the control unit Is called.

When data reception is confirmed by both reception control units 5 ₁ and 5 _{2 as} a result of the waiting process, a response signal is returned to the transmission control unit 2 ₂ using the inter-transmission / reception control signal transmission line 77 ₁ . The transmission control unit 2 _second response signal reception controller 9 ₂ provided in the response signals received, performs distribution to other transmission control section 2 ₁ using a transmission-side control signal transmission line 15.

Here, the transmission control unit only receives only the response signal at the second transmission control section ₂ (second transmission control section) 2 ₁ slave transmission control unit, transmission control unit that performs processing of distributing the response signal received ( The first transmission control unit) 2 ₂ is defined as a master transmission control unit.

These functions are switched by a slave instruction signal 16 ₁ and a master instruction signal 16 ₂ input to the control unit. Each input is a fixed value, which is, for example, switching between signals '0' and '1'.

  The master transmission control unit and the slave transmission control unit can be switched by setting a value in a register (signal setting storage unit) provided in each control unit in addition to the above unit.

Here, also in the receiving side control section, the reception control unit only transmits a response signal (second reception control unit) 5 ₁ slave reception control section, waiting for a response signal from another control unit, the self-control defining respectively a reception control unit that returns the signal to the transmitting side control section with a response signal of the portion unit (second reception control unit) 5 ₂ master reception control unit.

These functions can be switched by a master instruction input and a slave instruction input (reception-side master-slave selection signals 13 ₁ and 13 ₂ ) as in the transmission side, and can also be switched by setting a value for a register existing in each control unit. .

Operations in the transmission control units 2 ₁ and 2 ₂ and the reception control units 5 ₁ and 5 ₂ will be described with reference to the flowchart of FIG.

First, the transmission data 1 arrives to the transmission control unit 2 ₁ (step S933). Perform such transmission data control unit ₇₁ in the frame of data and passes the data to the transmission circuit ₈₁ (step S934).

Transmitting circuit 8 ₁ In the data parallel, performs serial conversion (step S935), using a high-speed serial transmission line 3 _1, to transmit the data to the receiving unit 5 ₁ (step S936). At this time, the transmission data counter in the transmission control unit is incremented by one (step S937).

Receiving circuit 10 ₁ performs conversion into parallel data upon receiving the serial signal (step S938), and outputs the data from the received data output section 4 ₁ (step S939). At the same time, the data received by the reception circuit 10 ₁ is sent to the reception data control unit 11 ₁ , where the reception data is analyzed (step S940), and when the data can be normally received, the response transmission control unit 12 ₁ On the other hand, a response signal is requested to be output (step S941).

Response signal reception control unit 5 ₁ is sent through the reception side between the signal transmission line 14 to the response signal transmission control unit 12 _2. Here, until the flow of the transmission control unit 2 _1, a transmission sequence between the reception control unit 5 _1, there is a flow of transmission and reception of the same data is also in the same time the transmission control unit 2 _2, between the reception control section 5 ₂ It shall be assumed (steps S947 to S954).

Incidentally, to generate a response signal in the response signal transmission control unit 12 ₂ (step S955). In response signal transmission control unit 12 ₂ performs the queuing processing of response signals of the response signal and the response signal reception control unit 5 in ₁ from the reception control unit 5 _1.

The result is output to the inter-transmission / reception response signal transmission path 6 (step S956). Waiting result response signal from the reception control section 5 ₂ is sent to the transmission control unit 2 ₂ through the transmission and reception between the response signal transmission line 6 (step S957).

In response signal reception controller 9 ₂ receives the response signal, to one received data counter in the own circuit adds (+1). Further, to the transmission control unit 2 _1, a control signal is partitioned with a transmission-side control signal transmission line 15 (step S958).

Response signal reception controller 9 ₁ receives the response signal from the transmission control unit 2 _2, the reception data counter in the own circuit to +1 (step S942).

Here, check the difference of the transmission data counter and receiving data counter of the response signal reception controller 9 _1, to determine whether more than a predetermined value (step S943). The case of equal to or more than a predetermined value, an error status than the response signal reception controller 9 ₁ (step S945), and ends the data reception (step S946). If the difference value between the transmission data counter and the reception data counter is within a certain value, no error is displayed and data reception is terminated (step S944).

The operation to check the difference of the received data counter and transmitting data counter in return signal reception control portion, it is carried out the same processing even transmission control unit 2 within ₂ (step S959~S962).

Definition Here, the transmission control unit 2 ₁ only receives only the response signal at the transmission side control unit, the slave transmission control unit, the transmission control unit 2 ₂ which performs processing for distributing the response signal received with the master transmission control unit To do.

Switching of these functions are switched by the slave indication signal 16 ₁ and the master instruction signal 16 ₂ to be inputted to the control unit. Each input is a fixed value, which is, for example, switching between signals '0' and '1'.

  In addition to the above means, the master and slave control units can be switched by setting a value for a register provided in each control unit. A master control unit and a slave control unit are also defined in the reception side control unit.

The reception control unit 5 _first only transmits a response signal at the receiving side control unit, the receiving-side slave control unit, waiting for a response signal from another control unit, the signal to the transmission side control unit with its own control unit inside of the response signal the reception side control section 5 ₂ return is defined as the master reception control unit.

The switching of these functions is performed by the master instruction input and slave instruction input (reception-side master-slave selection signals 13 ₁ and 13 ₂ ) as in the transmission side, and the values for the registers provided in the reception control units 5 ₁ and 5 _2. Switch according to the setting.

Further, the transmission control units 2 ₁ and 2 ₂ and the reception control units 5 ₁ and 5 ₂ determine the throughput state on the reception side, and when data exceeding the set throughput is sent, the transmission side is instructed to adjust the throughput. Control for issuing a throughput adjustment request signal is performed.

  Control based on this throughput adjustment instruction will be described with reference to the flowchart of FIG.

First, the transmission data 1 arrives to the transmission control unit 2 ₁ (step S963). The transmission data control unit 7 ₁ performs data framing and the like, and passes the data to the transmission circuit 8 ₁ (step S964).

Transmitting circuit 8 _1, the data parallel, performs serial conversion (step S965), performs transmission of data to the receiving unit 5 ₁ via the high speed serial transmission line 3 ₁ (step S966).

Receiving circuit 10 ₁ receives the serial signal subjected to conversion into parallel data (step S967), and outputs the data from the received data output section 4 ₁ (step S968). Here, the data received by the receiving circuit receives data transmitted to the reception data control unit 11 ₁ is analyzed (step S969), it is determined whether prescribed throughput or more data flows.

If provisions throughput or more data flows, compared response transmitting transmission control circuit 12 ₁ calculates to output the throughput adjustment request signal (wait signal) (step S970). Waiting signal reception control unit 5 ₁ is sent through the reception side between the signal transmission line 14 of the reception control section 5 ₂ to the response signal transmission control unit 12 _2.

The flow up to this point is a transmission sequence between the transmission control unit 2 ₁ and the reception control unit 5 ₁ , and the same data transmission / reception flow exists between the transmission control unit 2 ₂ and the reception control unit 5 ₂ at the same time. It is assumed (steps S974 to S980). Incidentally, to generate the wait signal in response signal transmission control unit 12 ₂ (step S981). In response signal transmission control unit 12 ₂ performs the OR combination of the standby signal and the standby signal reception control unit 5 in ₁ from the reception control unit 5 _1.

The result is output to the inter-transmission / reception response signal transmission path 6 (step S982). OR combination result response signal from the reception control section 5 ₂ is sent to the transmission control unit 2 ₂ through the transmission and reception between the response signal transmission line 6 (step S 983).

Response signal reception controller 9 ₂ receives the response signal, and sends the transmission standby instruction to the transmission data control section 7 _2. Further, to the transmission control unit 2 _1, it distributes the wait signal using the transmission-side control control signal transmission line 15 (step S984).

Response signal reception controller 9 ₁ receives the response signal from the transmission control unit 2 ₂ sends a transmission standby instruction to the transmission data control unit ₇₁ (step S971). The transmission of data in the transmission data control unit ₇₁ for a predetermined period of time waiting (step S972). Thereafter, the data reception process is terminated (step S973).

Incidentally, a period of time waiting and data reception termination process of the transmission data is carried out the same processing even transmission control unit 2 within ₂ (step S985, S 986).

The difference from FIG. 6 described above are (1) that the received data counter process is not present, (2) data received by the receiving circuit is sent to the reception data control unit 11 _1, here analyzes the received data (step S969), to determine whether prescribed throughput or more data flows, and (3) if specified throughput more data is flowing, to the response signal transmission control unit _121, the throughput adjustment request signal (wait signal) be determined to output (step S970), (4) generating a wait signal in response signal transmission control unit 12 ₂ of the reception control unit 5 in ₂ (step S981), (5) the response of the reception control section 5 within ₂ the signal transmission control unit 12 _2, performing the oR combination of the standby signal and the standby signal reception control unit 5 in ₁ from the reception control section 5 ₁ (step S 982), and (6) transmit In response signal reception controller 9 ₂ in the control unit 2 ₂ receives the response signal, it sends a transmission standby instruction to the transmission data control section 7 _2, also with respect to (7) the transmission control unit 2 _1, the transmission side distributing the wait signal using a controller control signal transmission line 15 (step S984), (8) the response signal reception controller 9 ₁ receives the response signal from the transmission control unit 2 _2, transmission data transmission standby instruction it is to send to the control unit ₇₁ (step S971), and (9) for a certain period of time waiting for transmission of data in the transmission data control unit 7 within ₁ (step S972).

Further, the transmission control units 2 ₁ and 2 ₂ and the reception control units 5 ₁ and 5 ₂ have a function of determining data reception timing on the reception side and performing data synchronization control.

  The operation of this data synchronization control will be described using the flowchart of FIG.

First, the transmission data 1 arrives to the transmission control unit 2 ₁ (step S987). The transmission data control unit 7 ₁ performs data framing and the like, and passes the data to the transmission circuit 8 ₁ (step S988).

Parallel data in the transmission circuit performs serial conversion (step S989), performs transmission of data to the receiving unit 5 ₁ using a high-speed serial transmission line 3 ₁ (step S990). When receiving the serial signal, the receiving circuit 10 ₁ inside the receiving unit converts it into parallel data (step S991), and outputs data from the received data output unit 4 ₁ (step S992). At the same time, with respect to the response signal transmission control unit 12 ₁ obtains to output the received timing signal of the data (step S993).

Reception timing signal of the reception control unit 5 ₁ is sent through the reception side between the signal transmission line 14 to the response signal transmission control unit 12 ₂ of the reception control section 5 _2. Here, until the flow of the transmission control unit 2 _1, a transmission sequence between the reception control unit 5 _1, there is a flow of transmission and reception of the same data is also in the same time the transmission control unit 2 _2, between the reception control section 5 ₂ It shall be assumed (steps S999 to S1004).

Incidentally, to generate the received timing signal in the response signal transmission control unit 12 ₂ of the reception control unit 5 in ₂ (step S1005). In response signal transmission control unit 12 _2, the reception timing signal of the reception timing signal and the reception control section 5 within ₂ from the reception control unit 5 ₁ binding processing, the results, sending and receiving between the response signal transmission path as a synchronization control signal 6 (Step S1006).

Binding result response signal from the reception control section 5 ₂ (synchronizing control signals) are sent to the transmission control unit 2 ₂ through the transmission and reception between the response signal transmission line 6 (step S1007).

In response signal reception controller 9 ₂ in the transmission control unit 2 ₂ receives the response signal and decodes. Further, to the transmission control unit 2 _1, it distributes the timing signals for each slave transmission control unit using the transmission-side control signal transmission line 15 (step S1008).

Response signal reception controller 9 ₁ receives the response signal from the transmission control unit 2 _2, the decoding (step S994). Send this decoding result to the transmission data control unit ₇₁ (step S995).

Here, the transmission data control unit 7 within ₁ determines whether required data transmission timing adjustment (step S996). If there was a need to adjust the data transmission timing by the transmission data control unit 7 within ₁ (step S997). Then, the data reception ends (step S998).

Incidentally, it sends the decoded result to the transmission data control unit ₇₁ by the transmission control unit 2 within ₁ (step S995) after the operation is performed the same processing even transmission control unit 2 within ₂ (step S1009~S1012). The difference from FIG. 7, (1) the received data counter process is not present, (2) with respect to the response signal transmission control unit _121, determining to output the received timing signal of the data (step S993), (3 ) the response signal transmission control unit 12 ₂ to generate a reception timing signal (step S1005), (4) the response signal transmission control unit 12, _2, the reception control unit 5 receives a timing signal from the ₁ and the receiving control section 5 ₁ The reception timing signal is combined, and the result is output to the inter-transmission / reception response signal transmission path 6 (step S1006), and (5) the response signal reception control unit 9 ₂ in the transmission control unit 2 ₂ receives the signal, it is decoded, also (7) to the transmission control unit 2 _1, distributes the timing signals for each slave transmission control unit using the transmission-side control signal transmission line 15 (Step S1008), (8) The response signal reception control section 9 ₁ receives the response signal from the transmission control section 2 ₂ and decodes it (Step S994), (9) The decoding result is transmitted to the transmission data control section 7 sending to ₁ (step S995), where the transmission data control unit 7 within _1, to determine whether required data transmission timing adjustment (step S996), if it was necessary, the transmission data control unit 7 ₁ Is to adjust the data transmission timing (step S997).

In addition, the reception control units 5 ₁ and 5 ₂ have a function of determining received data and making a retransmission request to the transmitting side when wrong data is transmitted.

  The control operation based on this retransmission request will be described with reference to the flowchart of FIG.

Here, the frame data transmitted and received between the transmission control units 2 ₁ and 2 ₂ and between the reception control units 5 ₁ and 5 ₂ is assumed to have a frame structure shown in FIG.

First, the transmission data 1 arrives to the transmission control unit 2 ₁ (step S1013). Perform such transmission data control unit ₇₁ in the frame of data and passes the data to the transmission circuit ₈₁ (step S1014).

Transmitting circuit 8 ₁ In the data parallel, performs serial conversion (step S1015), using a high-speed serial transmission line 3 _1, to transmit the data to the receiving unit 5 ₁ (step S1016).

In the receiving circuit 10 ₁ in the receiving part, performs conversion into parallel data upon receiving the serial signal (step S1017), and outputs the data from the received data output section 4 ₁ (step S1018).

At the same time, the data received by the receiving circuit is sent to the reception data control unit 11 ₁ . Here, analyzes the received data (step S1019), checks the unique value with respect to the response signal transmission control unit 12 ₁ when it was found that the expected frame is not sent, the retransmission request signal output (Step S1020).

Response signal reception control unit 5 ₁ is sent through the reception side between the signal transmission line 14 to the response signal transmission control unit 12 _2. Here, until the flow of the transmission control unit 2 _1, a transmission sequence between the reception control unit 5 _1, there is a flow of transmission and reception of the same data is also in the same time the transmission control unit 2 _2, between the reception control section 5 ₂ It shall be (steps S1024 to S1030). Incidentally, the response signal transmission control unit 12 ₂ generates a retransmission request signal (step S1031).

In response signal transmission control unit 12 ₂ performs the process of combining retransmission request signal and the retransmission request signal reception control section 5 within ₂ from the reception control unit 5 _1. The result is output to the inter-transmission / reception response signal transmission path 6 (step S1032).

Binding result response signal from the reception control section 5 ₂ is sent to the transmission control unit 2 ₂ through the transmission and reception between the response signal transmission line 6 (step S 1033). In response signal reception controller 9 ₂ receives the response signal.

Further, to the transmission control unit 2 _1, it distributes the retransmission request signal using the transmission-side control signal transmission line 15 (step S1034). Response signal reception controller 9 ₁ receives the response signal from the transmission control unit 2 ₂ (step S1021), if it was a retransmission request to itself (step S1022), to the transmission data control unit _71, a data retransmission instruction put out.

Then, the transmission data control unit ₇₁ performs retransmission processing of the data (step S1022). Then, the data reception ends (step S1023). Note that receives a retransmission request in response the signal reception control portion, the flow of performing retransmission instruction, and retransmission processing, processing is carried out similarly even transmission controller 2 within ₂ (step S1035, S1036).

The difference from FIG. 6, (1) the received data counter process is not present, (2) data received by the receiving circuit is sent to the reception data control unit 11 _1, wherein analyzing the received data (step S1019 ), (3) checks the unique value with respect to the response signal transmission control unit 12 ₁ when it was found that the expected frame is not sent, determining to output a retransmission request signal (step S1020) , (4) generating a retransmission request signal in the response signal transmission control unit 12 ₂ of the reception control unit 5 in ₂ (step S1031), (5) the response signal transmission control unit 12 _2, from the reception control unit 5 ₁ performs binding processing of the retransmission request signal and the retransmission request signal reception control section 5 within _2, the result is to be output to the transmission and reception between the response signal transmission line 6 (step S1032), (6) the response signal received Control section 9 ₁ receives the response signal from the transmission control unit 2 _2, if it was a retransmission request to itself to (step S1022), the transmission data control unit _71, to issue data retransmission instruction (step S1022), (7) the transmission data control unit ₇₁ is to perform the retransmission processing of the data (step S1022).

  10 and 11 are block diagrams illustrating examples of combinations of the master control unit and the slave control unit in the data transmission apparatus.

First, in FIG. 10, the same number exists for the transmission side control units 36 _{1 to} 36 _n and the reception side control units 35 _{1 to} 35 _n , and high-speed serial transmission lines 31 _{1 to} 31 _m are respectively connected therebetween. .

The transmission side control units 36 _{1 to} 36 _n are connected by a control line transmission line 34 between transmission side control units, respectively, and the reception side control units 35 _{1 to} 35 _n are connected by a control line transmission line 32 between reception side control units. Each is connected.

Further, the transmission side control unit 36 _{n serving as} the transmission side master control unit and the reception side control unit 35 _{n serving as the} reception side master control unit are connected by the inter-transmission / reception control line transmission path 33.

  FIG. 11 shows a case where the numbers of the transmission side control unit and the reception side control unit are different.

Even in this case, transmission and reception are connected by high-speed serial transmission lines 31 _{1 to} 31 _m , respectively, and the transmission side control units 36 _{1 to} 36 _n are connected by transmission line control line transmission lines 34 between the transmission side controllers. . The reception side control units 35 _{1 to} 35 _n are connected by a control line transmission line 32 between the reception side control units.

Further, the transmission side control unit 36 _{n serving as} the transmission side master control unit and the reception side control unit 35 _{n serving as the} reception side master control unit are connected by the inter-transmission / reception control line transmission path 33.

  Next, a data transmission method having the above connection form will be described with reference to FIG.

A huge amount of image data obtained from the image data acquisition means of the semiconductor inspection apparatus is sent to the transmission controllers 36 _{1 to} 36 _n . The transmission controllers 36 _{1 to} 36 _n send these data to the high-speed serial transmission lines 31 _{1 to} 31 _m .

This serial signal is received by the reception control units 35 _{1 to} 35 _n and sent backward as original image data. When the reception control unit determines that this transmission data and performs some control, each of the reception control units 35 _{1 to} 35 _n uses the inter-reception control unit control signal 32 to transfer the control contents to the reception side master control unit. Send to 35 _n .

  Note that the control signal is aggregated by the receiving master control unit in either case, whether it is sent from all reception control units at the same time or from some reception control units, and is handled as one system signal. Is called.

The reception-side control unit 35 _{n serving as} the reception-side master control unit transmits the control contents to the transmission-side control unit 36 _{n serving as} the transmission-side master control unit using the transmission / reception control signal line 33. The transmission side master control unit determines this control content and distributes the control content to each of the transmission side control units 36 _{1 to} 36 _n−1 using the inter-transmission control unit control signal line 34.

  In the configuration using a plurality of transmission control units / reception control units shown in FIG. 10 and FIG. 11, the transmission data input unit, the high-speed serial transmission path, the reception data output unit, etc. are used or unused. It is also possible to provide a means for switching by a register.

  In addition, although the response signal transmission control circuit in each of the above-described configurations has been used for confirmation of normal data arrival, other control details include, for example, determining the status of the high-speed serial transmission path from the received data and automatically connecting A means for returning a confirmation signal to the transmission side may be provided.

  FIG. 12 is an explanatory diagram illustrating an example of frame data transmitted and received in the data transmission apparatus.

  As shown in the figure, the frame data has a frame configuration including frame start identification data (SOF) 51, frame number 52, image data 53 to be transmitted, and frame data end identification data (EOF) 54.

  The frame start identification data 51 is data for identifying the start of frame data, and the frame number 52 is a unique value set for each frame to be transmitted. The frame data end identification data 54 is data for identifying the end of the frame data.

  The reception data control unit 11 checks the frame number 52 which is this unique value, and when it is determined that the expected frame is not transmitted, the frame data retransmission request is sent to the transmission side through the response signal transmission control unit 12. multiply.

  FIG. 13 is a block diagram illustrating an example when the data transmission apparatus includes a decoding circuit that performs encoding of transmission data and error correction of reception data.

  In this case, the transmission data control unit 18 in the transmission control unit 2 is provided with a data encoding circuit for encoding transmission data, and the data is encoded by the data encoding circuit.

  The reception control unit 5 is provided with a decoding circuit 17 that decodes the data output from the receiving circuit 10. Even if an error occurs in data between transmission and reception by this decoding circuit 17, if the error is correctable by the decoding circuit, the error is corrected and normal data is output from the received data output unit 4.

  When the decoding circuit 17 determines that the data cannot be decoded and cannot be corrected, the data is transmitted to the transmitting side control unit 2 via the reception data control unit 11 and the response signal transmission control unit 12. A configuration is provided in which means for issuing a retransmission request is provided.

  FIG. 14 shows an example of a configuration in which, in the data transmission apparatus, the master reception control unit can confirm that the data transmission cannot be performed due to a failure without confirming all the reception control units. It is the block diagram shown.

In this case, the reception control unit 35n serving as the master reception control unit, the reception control units 35 _{1 to} 35 _{n-1 serving} as the slave reception control unit, the transmission control unit 36n serving as the master transmission control unit, and the transmission serving as the slave transmission control unit It comprises control units 36 _{1 to} 36 _n−1 , and a failure control display unit 37 is provided in the reception control unit 35 _n .

Image data and control data are received from the transmission control units 36 _{1 to} 36 _n by the reception side control units 35 _{1 to} 35 _n through the high-speed serial lines 31 _{1 to} 31 _n . At this time, it is assumed that some failure occurs in which data is not normally received by a certain reception control unit.

  Here, the failure includes, for example, disconnection of the high-speed serial line, and the transmission side control unit and the reception control unit stop its operation, for example, a decrease in power supply voltage. In addition, when the data is not normally received on the receiving side, for example, the receiving side control unit always calculates a certain eigenvalue from the received data and stores the received data when the eigenvalue indicates an abnormal value. List buffer overflow conditions.

At this time, the reception-side control unit in which the failure has occurred notifies the master reception control unit 35 _n of the abnormal state by a response signal. For example, an error occurs in the reception control unit and the response signal is changed from a value 1 to a value 0.

The master reception control unit 35 _n includes a failure control display unit 37 for monitoring response signals returned from all reception control units, and always monitors the status of response signals returned from all reception control units. doing. The failure control display unit 37 is composed of a register, for example.

  An error has occurred in a certain reception control unit because, for example, when a normal reception control unit state is set to 1 in the failure control display unit 37, a certain value in the failure control display unit 37 changes to 0. It is confirmed. It can be confirmed that some failure has occurred in a certain reception control unit corresponding to the change of this value from “1” to “0”.

As processing by this, for example, the transmission side control unit is notified that some failure has occurred in the reception side control unit using the inter-transmission / reception response signal transmission path 33, and is transmitted to the transmission side control units 36 _{1 to} 36 _n . To stop the transmission or to stop using the part of the transmission line where the failure occurred.

  Thereby, according to the present embodiment, a large amount of data can be efficiently transmitted in the semiconductor inspection apparatus. Moreover, since the control line between transmission and reception can be simplified to one system, the apparatus cost can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Furthermore, in the above-described embodiment, the response signal transmission path for the transmission side is given as the output of the response signal transmission control circuit in each configuration. However, as another transmission method, means using a non-wired transmission method such as wireless communication is provided. It is good also as a structure to provide.

  The data transmission technique of the present invention is suitable for a technique for efficiently transmitting a large amount of image data at a low cost, such as a semiconductor inspection apparatus.

1 is a block diagram of a semiconductor inspection apparatus according to an embodiment of the present invention. 3 is a flowchart showing an example of operation in the semiconductor inspection apparatus of FIG. 1. FIG. 2 is a block diagram of a transmission control unit and a reception control unit provided in the semiconductor inspection apparatus of FIG. 1. 4 is a flowchart illustrating an example of operations in a transmission control unit and a reception control unit in FIG. 3. FIG. 2 is a block diagram of a data transfer device provided in the semiconductor inspection device of FIG. 1. It is a flowchart which shows an example of operation | movement in the data transfer apparatus of FIG. 6 is a flowchart illustrating a control example according to a throughput adjustment instruction in the data transfer apparatus of FIG. 5. It is a flowchart which shows an example of the data synchronization control in the data transfer apparatus of FIG. 6 is a flowchart showing an example of a control operation by a retransmission request in the data transfer apparatus of FIG. FIG. 6 is a block diagram illustrating an example of a master / slave combination in the data transfer apparatus of FIG. 5. FIG. 6 is a block diagram illustrating another example of a master / slave combination in the data transfer apparatus of FIG. 5. It is explanatory drawing which shows the structural example of the frame data used for the data transfer of the semiconductor inspection apparatus of FIG. FIG. 6 is a block diagram illustrating an example when the data transfer apparatus of FIG. 5 includes a decoding circuit that performs encoding of transmission data and error correction of reception data. FIG. 6 is a block diagram illustrating an example in which a failure control display unit that detects a reception abnormality is provided in the data transfer apparatus of FIG. 5.

Explanation of symbols

1 ... Transmission data, 2 _{1 to} 2 _n ... Transmission control unit, 3 ₁ , 3 ₂ ... High-speed serial transmission path, 4 ₁ ... Reception data output unit, 5,5 _{1 to} 5 _n ... Reception control unit, 6 ... Transmission and reception during the response signal transmission path, 7,7 _1, 7 ₂ ... transmission data control unit, 8, 8 _1, 8 ₂ ... transmission circuit, 9,9 _1, 9 ₂ ... response signal reception control unit, 10, 10 _1, 10 ₂ ... reception circuit, 11, 11 ₁ , 11 ₂ ... reception data control unit, 12, 12 ₁ , 12 ₂ ... response signal transmission control unit, reception side master slave selection signal 13 ₁ , 13 ₂ , 14 ... reception side signal Transmission path 15... Transmission side control signal transmission path 16 ₁ ... Slave instruction signal 16 _2. Master instruction signal 17. Decoding circuit 18 Transmission data control section 31 _{1 to} 31 _m High-speed serial transmission path 32 ... Control line transmission line between reception side control units, 33 ... Control line transmission line between transmission and reception, 34 ... Transmission side control During control line transmission line, 35 ₁ to 35 _n ... receiving device controller, 36 ₁ ~ 36 _n ... transmitting side control section 3,37 ... failure control display unit 37, 51 ... frame start identification data, 52 ... frame number, 53 ... image data, 54 ... frame data end identification data, 71 ... mirror, 72 ... A / D converter, 73 ... image data distribution controller, 74 ... image processing device, 75 ... image data distribution controller, 76 ₁ to 76 _n ... high-speed serial transmission line, 77 _{1 to} 77 _n ... control signal transmission line between transmission and reception, 78 _{1 to} 78 _n ... image data processing unit, 79 ... defective image display device, 700 _{1 to} 700 _n ... transmission side transmission control unit , 710 _{1 to} 710 _n ... Reception side transmission control unit, 720 _{1 to} 720 _n ... Transmission side control unit, 730 _{1 to} 730 _n ... Reception side control unit, 780.

Claims (7)

First and second transmission control units for converting parallel image data into serial signals;
A first and second reception control unit for converting the serial signal converted by the first and second transmission control units into parallel data;
The first and second transmission control units are:
A transmission data control unit that converts the image data of the input parallel signal into frame data;
A transmission circuit that converts the frame data converted by the transmission data control unit into a serial signal and outputs the serial signal;
A response signal reception control unit that determines whether the image data has been normally received based on the response signal, and
The first and second reception control units are:
A receiving circuit for converting a serial signal output from the transmitting circuit into a parallel signal;
Analyzing whether or not the serial signal was successfully received by analyzing the parallel signal converted by the receiving circuit, each including a reception data control response unit that outputs a response signal generated based on the analysis result,
The first reception control unit includes:
One or more response signals output from the second reception control unit are received, and the response signal generated by the first reception control unit is output to the first transmission control unit,
The first transmission control unit distributes the received response signal and transmits the response signal to one or more corresponding second transmission / reception control units. The semiconductor inspection apparatus according to claim 1,
The response signals generated by the first and second reception control units include a throughput adjustment request signal for temporarily stopping transfer of serial signals by the first and second transmission control units,
The first and second reception control units have a throughput when serial signals transferred from the first and second transmission control units overflow in the first and second reception control units. A semiconductor inspection apparatus that outputs an adjustment request signal. The semiconductor inspection apparatus according to claim 1 or 2,
The response signals generated by the first and second reception control units include a synchronization control signal, and the serial signals transferred from the first and second transmission control units are output in synchronization with each other. Semiconductor inspection equipment. In the semiconductor inspection apparatus according to any one of claims 1 to 3,
The response signals generated by the first and second reception control units include a retransmission request signal,
The first and second reception control units are:
It is determined whether or not received data is normal, outputs a retransmission request signal in the event of an abnormality, and makes a retransmission request for causing the first and second transmission control units to retransmit the data. Semiconductor inspection equipment. In the semiconductor inspection device according to any one of claims 1 to 4,
Setting signal storage means for storing the setting signal is provided,
Switching between the first reception control unit and the second reception control unit, and between the first transmission control unit and the second reception control unit based on the setting signal stored in the setting signal storage means A semiconductor inspection apparatus characterized in that each is performed. In the semiconductor inspection apparatus according to any one of claims 1 to 5,
A first printed wiring board on which the first and second transmission control units are mounted;
A second printed wiring board on which the first and second reception control units are mounted;
The first and second transmission control units and the first and second reception control units are connected via a data transmission path provided between the first and second printed wiring boards. A semiconductor inspection apparatus. In the semiconductor inspection apparatus according to any one of claims 1 to 5,
A printed wiring board on which the first and second transmission control units and the first and second reception control units are mounted;
The semiconductor inspection characterized in that the first and second transmission control units and the first and second reception control units are connected via a data transmission path formed on the printed wiring board. apparatus.

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