JP2005286931A - Power on resetting instrument and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power on resetting instrument where resetting of a load circuit when a battery is charged is surely released and an initialization of a system can surely be performed. <P>SOLUTION: The instrument is provided with a first detecting means detecting battery voltage that a power control means controls and supplies to the load circuit, a second detecting means detecting battery voltage and a resetting control means resetting the load circuit when the battery is charged and releasing resetting of the load circuit when a detection value of the first detecting means reaches a first prescribed value in a resetting state and a detection value of the second detecting means reaches a second prescribed value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power-on reset device that controls a reset operation of a load circuit such as a CPU in an electronic device that uses a battery such as a portable terminal, and an electronic device including the power-on reset device.

  In a portable terminal such as a cellular phone, the voltage Vbat (for example, 4V) of the battery 1 is input to the power supply control circuit 3 including a DC / DC regulator or the like via the power switch 2 as shown in FIG. The voltage Vin is converted and supplied to the CPU 4 of the terminal system, and the input voltage Vin is monitored by the power-on reset circuit 5. The power-on reset circuit 5 is supplied with a power supply voltage from the battery 1. When the battery voltage Vbat decreases as the battery 1 is discharged and becomes approximately equal to or lower than the input voltage Vin to the CPU 4, the power-on reset circuit 5 outputs a reset signal RESET / to put the CPU 4 in a reset state. Here, the reset state refers to a state in which the CPU 4 stops supplying clocks and does not operate at all. Although there is a sleep state with respect to the reset state, the sleep state is executed when the battery voltage Vbat is normal and a predetermined input voltage Vin is supplied to the CPU 4 and a clock is supplied, but the operation is temporarily stopped. The state where it can operate anytime if there is a command.

Next, when the battery voltage Vbat decreases with discharge and becomes equal to or lower than the input voltage Vin to the CPU 4 of the system, the battery 1 is charged by the AC battery charger. At this time, charging is initially started in a precharge mode with a small constant current value. In FIG. 7, the reset signal RESET / has been in a “Low” level reset state from the start of charging. When the battery voltage Vbat and the input voltage Vin gradually increase with charging and Vin reaches a predetermined reset reference voltage Vreset +, the power-on reset circuit 5 sets the reset signal RESET / to “High” after a predetermined delay time td1. The level is released and the reset state is released, and the CPU 4 starts the initial operation. At this time, in the conventional system, the initial operating current is not particularly large. Therefore, the voltage drop due to this current is small, and Vin is not lower than the reset reference voltage Vreset−. There will be no problem of occurrence. The reset reference voltage Vreset + has a hysteresis characteristic, and after reset, Vreset + is changed to Vreset-.
Note that the following patent document is known as a related art relating to the reset circuit.
JP 7-244916 A

  In recent years, mobile terminals have increased system operation current due to higher functionality, and therefore the equivalent series resistance of the battery has increased, and the voltage drop due to this equivalent series resistance value has also increased. For this reason, after the reset is released in FIG. 7, when the battery voltage Vbat and the input voltage Vin once fall and the Vin falls below the reset reference value Vreset−, the reset signal RESET / becomes “Low” level again and is reset again. May end up.

In FIG. 7, charging is resumed in a reset state, and Vbat and Vin rise. After Vin reaches the reset reference value Vreset + again, when the time td2 elapses, the reset signal RESET / becomes “High” level again, the reset is released and current flows, but at this time Vin drops below Vreset- and It will be reset. After that, Vin rises, and when Vreset + is reached and the delay time elapses, the reset is released and the CPU 4 operates. As a result, the reset release, CPU operation, reset state, and reset release operation are repeatedly performed from the reset state as shown in the figure, and there is a problem that the terminal system cannot be normally started up.
Accordingly, it is an object of the present invention to solve the above-described problems and to reliably release resetting of a load circuit such as a CPU when charging a battery so that the initial operation of the system is reliably performed.

  A power-on reset device according to the present invention includes a first detection unit that detects a voltage supplied to a load circuit by a power supply control unit that controls a battery voltage, a second detection unit that detects the battery voltage, The load circuit is reset during charging, and in this reset state, the detection value of the first detection means reaches a first predetermined value, and the detection value of the second detection means reaches a second predetermined value And a reset control means for canceling resetting of the load circuit.

  An electronic apparatus according to the present invention includes a power supply control unit that controls a battery voltage and supplies the load circuit to a load circuit, a first detection unit that detects a voltage supplied to the load circuit, and a second unit that detects the battery voltage. The load circuit is reset when the battery is charged with the detection means, and in this reset state, the detection value of the first detection means reaches a first predetermined value, and the detection value of the second detection means is the first value. And a reset control means for releasing the reset of the load circuit when a predetermined value of 2 is reached.

  According to the present invention, when the battery is charged and a predetermined battery voltage is reached, the reset is surely canceled and the load circuit is operated, so that the system can be reliably started up normally.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit configuration diagram of a power supply circuit of a portable terminal including a power-on reset device according to an embodiment of the present invention.
In FIG. 1, a power-on reset device 100 is configured on an IC chip and has chip terminals 101 to 106.
The voltage Vbat of the battery 1 is supplied to a power control circuit 3 including a DC / DC regulator through a power switch 2, where it is converted to an input voltage Vin (constant voltage, for example, 4V) and supplied to a CPU 4 as a load circuit. Is done. A reset signal RESET / is output from the chip terminal 104 of the apparatus 100 to the CPU 4 to control reset and reset release of the CPU 4.

The comparator COMP1 monitors the input voltage Vin input via the chip terminal 101. This voltage Vin is also used as a power supply voltage for the apparatus 100. The constant current power supply 11 and the reference voltage source 12 set the reference voltage Vref1 of the comparator COMP1. The resistors R1, R2, and R3 are divided resistors that divide the input voltage Vin and supply it to the negative (−) terminal of the comparator COMP1.
The transistor Q2 controls the hysteresis characteristic of the comparator COMP1 by connecting / disconnecting the resistor R3. The integrating circuit 13 determines the delay time of the reset signal RESET /, and includes a transistor Q1, a resistor Rd1, and an external capacitor Cd. The inverter GATE1 is an inverter composed of a Schmitt trigger circuit that shapes the integration signal of the integration circuit 13.
The inverter GATE1 and the integration circuit 13 constitute an AND circuit 14, and the transistors Q3 and Q4 constitute an output buffer circuit 15. A reset signal RESET / is output from the AND circuit 14 to the chip terminal 104 via the output buffer circuit 15.

  The comparator COMP2 monitors the battery voltage Vbat input via the chip terminal 105. The constant current source 16 and the reference voltage source 17 set the reference voltage Vref2 of the comparator COMP2. The resistors R7 and R8 set the reference voltage Vref2 of the comparator COMP2. The resistor R8 is externally connected to the chip terminal 105. The resistors R4, R5, and R6 are divided resistors that divide the battery voltage Vbat and supply it to the negative (−) terminal of the comparator COMP2. The transistor Q5 controls the hysteresis characteristic of the comparator COMP2 by connecting / disconnecting the resistor R6. The transistors Q6 and Q7 control the output of the comparator COMP2 and supply it to the transistor Q1 via the resistor Rd1.

Next, the operation will be described with reference to FIG. 1, FIG. 2, FIG. 3, and FIG.
As described above, when the battery voltage Vbat decreases as the battery discharges, it is about the same as or lower than the input voltage Vin to the CPU 4 of the system, and when the battery 1 is charged with the AC battery charger, the charger is initially set to a low constant. Charging is started in the current value precharge mode. The battery voltage Vbat gradually increases, and when the reset release voltage is reached, the CPU 4 transitions to the operating state. At this time, if the initial operating current value of the system is larger than the small constant current value, the reset occurs again exceeding the power-on reset threshold. The present embodiment avoids this phenomenon.

When the battery 1 is charged, the input voltage Vin generated by the power supply control circuit 3 from the battery voltage Vbat to the CPU 4 gradually increases with Vbat. At this time, the output of the comparator COMP1 is at “High” level, the transistor Q2 is turned on, the resistor R3 is disconnected, and the transistor Q1 is turned on. Further, the output of the inverter GATE1 is at the “High” level, the transistor Q3 is turned off, the transistor Q4 is turned on, the reset signal RESET / becomes the “Low” level, and the CPU 4 is in the reset state. The output of the comparator COMP2 is “High” level, the transistor Q5 is turned on, the resistor R6 is disconnected, the transistor Q7 is turned on, and the transistor Q6 is turned off. The input voltage Vin is divided by resistors R1 and R2, and the voltage of R2 / (R1 + R2)) * Vin is input to the negative (−) terminal of the comparator COMP1.
The battery voltage Vbat is divided by resistors R4 and R5, and the voltage of the input voltage R5 / (R4 + R5) * Vbat is input to the negative (−) terminal of the comparator COMP2.

  In FIG. 2, when Vin exceeds the reset reference voltage Vreset +, the voltage at the negative (−) terminal of the comparator COMP1 exceeds the reference voltage Vref1, the output of the comparator COMP1 becomes “Low” level, and the transistor Q1 is turned off. At this time, the reference voltage Vref2 of the comparator COMP2 that monitors Vbat is set higher than the minimum input voltage required to generate a constant voltage (for example, 3V) of the input voltage Vin. Therefore, at the above time point, the output of the comparator COMP2 is still at “High” level, and no voltage is supplied to the integration circuit 13 that determines the delay time of the reset signal RESET /, so the reset signal RESET / is “Low”. Remain level.

  After that, the battery voltage Vbat gradually increases with Vin. When the voltage exceeds the threshold Vbat + in Fig. 2, the voltage at the negative (-) terminal of the comparator COMP2 exceeds the reference voltage Vref2, so the output of the comparator COMP2 is at "Low" level. Thus, the transistor Q7 is turned off, the transistor Q6 is turned on, and a voltage is supplied to the integrating resistor Rd1 of the integrating circuit 13. Since this voltage exceeds the threshold value of the inverter GATE1 after the integration time constants Rd1 and Cd have elapsed, the output of the inverter GATE1 becomes “Low” level, the transistor Q3 is turned on, and the transistor Q4 is turned off. Accordingly, the reset signal RESET / becomes “High” level, the reset is released, and the CPU 4 starts the initial operation. At this time, even if the operating current of the system is large and a voltage drop occurs, the threshold Vbat− at the time of reset release is set high, so that there is no problem in the initial operation of the CPU 4. In this initial operation routine, the AC battery charger is immediately set to the quick charge mode to supply a current value more than necessary for operation so that charging can be performed.

Further, when the operating current is larger, the input voltage Vbat + and Vbat− of the negative (−) terminal of the comparator COMP2 can be adjusted by adjusting the external resistor R8, so that it can be applied to any system.
In the state where the reset is released, the transistors Q2 and Q5 are off, and the resistors R3 and R6 are connected. Therefore, the divided voltages input to the negative (-) terminals of the comparators COMP1 and COMP2 are {(R2 + R3) / (R1 + R2 + R3)} * Vin, {(R6R7) / (R5 + R6, respectively. + R7)} * Vbat will be changed to have hysteresis characteristics. 2 and 3, Vreset + is changed to Vreset-, and Vbat + is changed to Vbat-.

  4 shows the hysteresis voltage value of the reset signal RESET /, and Table 2 shows the hysteresis voltage value for monitoring the battery voltage Vbat. Vreset +, Vreset- with respect to the input voltage Vin, the output of each comparator COMP1, COMP2, the input voltage of the negative (-) terminal, the state of each transistor Q1, Q2, Q5, Q6, Q7, the state transition of the reset signal RESET /, etc. The situation is shown.

FIG. 3 is a detailed enlarged view of the vicinity of the reset release in FIG.
In FIG. 3, first, Vin exceeds Vreset +, and after Vbat exceeds Vbat +, the reset signal RESET / becomes “High” level after the time constant td1 of the integration circuit 13 has elapsed, and the reset is released. After that, Vin and Vbat fall once, but as shown in the figure,
ΔV = (Vbat-)-(Vreset +)
Vin−ΔV ＝ Vreset-
Therefore, Vin and Vbat will not fall below Vreset- and will not be reset again.

  When the battery voltage Vbat gradually decreases as the terminal is normally operated after charging is completed, the reset signal RESET / becomes “Low” level if the voltage of each negative (−) terminal falls below the threshold value. The CPU 4 enters a reset state.

  When the remaining capacity of the battery 1 is large, that is, when the power is turned on when Vbat is sufficiently high, the output voltage Vin of the power control circuit 3 is turned on as shown in FIG. −) The reset is released when the divided voltage ((R2 + R3) / (R1 + R2 + R3)) * Vin exceeds Vreset +. When the power off key is input when the remaining capacity of the battery 1 is large, the output voltage Vin of the power supply control circuit 3 is turned off, and the negative (−) terminal voltage ((R2 + R3) / (R1 +) of the comparator COMP1. R2 + R3)) * Reset state when Vin falls below the reference voltage Vref1.

According to the present embodiment, the system can be normally started up without repeating the reset sequence. In addition, the threshold value of the battery voltage Vbat can be arbitrarily set according to the current value required for the initial operation of the terminal, and it is possible to cope with the increase in current consumption due to the higher functionality of the mobile terminal, and also for system LSI implementation. A suitable method can be realized.
For this reason, in a portable information communication system in which power consumption is increasing in the future due to higher functionality of terminals, particularly in mobile phone systems, a battery that has been discharged to a state where the capacity of the installed battery is nearly empty When charging, it is possible to provide a power-on reset device that ensures that the system cancels the reset during charging so that the initial operation of the terminal system moves without any problem.

It is a circuit block diagram of the power-on reset apparatus by embodiment of this invention. It is a reset timing chart explaining operation. It is a reset timing chart explaining the details of operation. It is a block diagram which shows the table 1 which shows the hysteresis voltage value which monitors the battery voltage, and the table 1 which shows the hysteresis voltage value of a reset signal. It is a reset timing chart at the time of battery high capacity. It is a block diagram which shows the power supply circuit which performs the conventional power-on reset. It is a reset timing chart explaining the conventional power-on reset operation.

Explanation of symbols

1 ... Battery 3 ... Power control circuit 4 ... CPU
DESCRIPTION OF SYMBOLS 13 ... Integration circuit 14 ... AND circuit 15 ... Output buffer circuit 101-106 ... Chip terminal

Claims (8)

First detection means for detecting the voltage supplied to the load circuit by the power supply control means for controlling the battery voltage;
Second detection means for detecting the battery voltage;
The load circuit is reset when the battery is charged, and in this reset state, the detection value of the first detection means reaches a first predetermined value, and the detection value of the second detection means is a second predetermined value. And a reset control means for canceling resetting of the load circuit when the load reaches the value.   2. The power-on reset device according to claim 1, wherein the reset control unit releases the reset after a lapse of a predetermined time after the output of the second detection unit reaches the second predetermined value.   3. The power-on reset device according to claim 1, wherein the second predetermined value> the first predetermined value.   4. The power-on reset device according to claim 1, further comprising changing means for changing the second predetermined value. Power control means for controlling the battery voltage and supplying it to the load circuit;
First detection means for detecting a voltage supplied from the power supply control means to the load circuit;
Second detection means for detecting the battery voltage;
The load circuit is reset when the battery is charged, and in this reset state, the detection value of the first detection means reaches a first predetermined value, and the detection value of the second detection means is a second predetermined value. An electronic device comprising: reset control means for canceling resetting of the load circuit when reaching the value.   6. The electronic apparatus according to claim 5, wherein the reset control unit releases the reset after a predetermined time has elapsed after the output of the second detection unit reaches the second predetermined value.   7. The electronic device according to claim 5, wherein the second predetermined value> the first predetermined value. 8. The electronic apparatus according to claim 5, 6 or 7, further comprising changing means for changing the second predetermined value.

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