JP2005286090A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of the conventional manufacturing process consuming much time for the formation of an oxide film to serve as an alignment mark because the epitaxial layer needs to be removed from the alignment forming region for exposure every time an epitaxial layer is deposited. <P>SOLUTION: In the scribe line region 2 on a substrate 3, an alignment mark 5 having a clear initial difference in level t1 is formed by forming a LOCOS oxide film 4 on the surface of a substrate 3, and then by removing the LOCOS oxide film 4. Reduction in the difference in level of an alignment mark 9 formed on the surface of an epitaxial layer 8 is alleviated in this way even when the epitaxial layer 8 is deposited thick on the surface of the substrate 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device for manufacturing a suitable alignment mark used in an exposure process.

In a conventional method for manufacturing an alignment mark, a pattern oxide film for an alignment mark is selectively formed on the surface of a silicon substrate. An epitaxial layer was deposited on the upper surface of the silicon substrate including the upper surface of the pattern oxide film. Then, the epitaxial layer in the polycrystalline region on the upper surface of the pattern oxide film is partially removed to expose the pattern oxide film as an alignment mark. Thereafter, there was a manufacturing method in which an element was formed using an alignment mark and the pattern oxide film was removed (see, for example, Patent Document 1).
Japanese Unexamined Patent Publication No. 03-40415 (pages 7-9, FIG. 5)

  As described above, in the conventional method for manufacturing an alignment mark, the pattern oxide film used as the alignment mark formed on the substrate surface needs to be exposed by removing the epitaxial layer deposited on the upper surface thereof. Therefore, in the case where a plurality of epitaxial layers are deposited, there is a problem that a process of removing the epitaxial layer and exposing the pattern oxide film is required every time the epitaxial layers are stacked, resulting in a high manufacturing cost. .

  In addition, when a thick epitaxial layer is deposited on the substrate surface or when a plurality of epitaxial layers are deposited, it is necessary to increase the opening for exposing the pattern oxide film without fail, There was a problem that miniaturization processing was difficult.

  The present invention has been made in view of the above-described circumstances. In the method for manufacturing a semiconductor device of the present invention, a semiconductor substrate is prepared, an oxide film is selectively formed on the substrate surface, and then the oxidation is performed. By removing the film, an initial step of a concave alignment mark is formed on the substrate surface, and at least one epitaxial layer is deposited on the substrate surface including the upper surface of the initial step, and the epitaxial layer surface is formed. A step of the alignment mark is formed using the initial step. Therefore, in the method for manufacturing a semiconductor device of the present invention, an oxide film is selectively grown on the substrate surface, and the oxide film is removed to form the initial step of the alignment mark. Then, by forming the oxide film so as to erode the substrate, an initial step consisting of a deep recess is formed on the substrate surface. As a result, even when a thick epitaxial layer is stacked on the upper surface of the alignment mark, the amount of reduction in the level difference of the alignment mark formed in the epitaxial layer can be reduced.

  In the method for manufacturing a semiconductor device according to the present invention, a LOCOS oxide film is used as the oxide film. Therefore, in the semiconductor device of the present invention, the deep initial step of the alignment mark can be formed on the substrate surface by forming the LOCOS oxide film in the region for forming the alignment mark on the substrate surface.

  Further, in the method for manufacturing a semiconductor device of the present invention, a silicon single crystal substrate having a main surface inclined with respect to the crystal axis of the silicon surface whose plane orientation is substantially represented by (100) is prepared, Impurities are implanted from the main surface and diffused to form a diffusion layer, an initial step of a concave alignment mark is formed on the main surface on which the diffusion layer is formed, including the upper surface of the initial step, At least one epitaxial layer is deposited on the surface of the substrate, and an alignment mark using the initial step is formed on the surface of the epitaxial layer. Therefore, in the method for manufacturing a semiconductor device of the present invention, the epitaxial layer is grown so as to be inclined in a certain direction with respect to the crystal axis of the silicon surface whose plane orientation is substantially represented by (100). As a result, the amount of reduction in the level difference of the alignment mark formed on the epitaxial layer surface can be mitigated.

  In the method for manufacturing a semiconductor device of the present invention, the main surface of the silicon single crystal substrate is tilted by 0.5 ° with respect to the crystal axis of the silicon surface whose plane orientation is represented by approximately (100). It is characterized by. Therefore, in the method for manufacturing a semiconductor device of the present invention, the epitaxial layer is laminated on the upper surface of the alignment make so as to incline in a certain direction, and the inclination is reduced. As a result, the amount of reduction in the level difference of the alignment mark formed on the epitaxial layer surface can be mitigated. Further, since the pattern design rule can be reduced, high integration of elements can be realized.

  In the method for manufacturing a semiconductor device of the present invention, a LOCOS oxide film is used when forming an initial step of an alignment mark formed on the substrate surface. As a result, a deep initial step of the alignment mark can be formed. Even when a thick epitaxial layer is stacked on the upper surface of the substrate, the amount of reduction in the level difference of the alignment mark formed on the surface of the epitaxial layer can be alleviated.

  Further, in the method of manufacturing a semiconductor device of the present invention, the plane orientation of the main surface is represented by approximately (100), and the crystal axis is 0. 0 relative to the crystal axis of the silicon plane whose plane orientation is represented by (100). Prepare a substrate tilted 5 °. As a result, the epitaxial layer on the upper surface of the substrate is laminated while being inclined in a certain direction, so that the amount of reduction in the level difference of the alignment mark formed in the epitaxial layer can be mitigated.

  Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 9 are diagrams used to explain the first embodiment, and FIGS. 10 to 12 are diagrams used to explain the second embodiment. 1 to 12 are cross-sectional views for explaining the semiconductor device manufacturing method of the present embodiment.

  In the following description, for example, an N-channel MOS transistor is formed in the element formation region 1, but the present invention is not limited to this case. For example, an NPN transistor, a lateral PNP transistor, or the like may be formed in another element formation region to form a semiconductor integrated circuit device. 1 to 12 show the element formation region 1 on the left half of the single crystal silicon substrate, and the scribe line region 2 for forming alignment marks on the right half of the substrate.

  The first embodiment of the present invention will be described below.

  First, as shown in FIG. 1, a P-type single crystal silicon substrate 3 is prepared, and the surface of the substrate 3 is thermally oxidized to form a silicon oxide film of, for example, about 0.03 to 0.05 μm. Thereafter, a silicon nitride film (not shown) is formed on the silicon oxide film, for example, about 0.05 to 0.2 μm. Then, the silicon nitride film is selectively removed so that an opening is provided in a portion where a LOCOS (Local Oxidation of Silicon) oxide film 4 is formed.

  Then, using the silicon nitride film as a mask, an oxide film is formed on the silicon oxide film by, for example, steam oxidation at about 800 to 1200 ° C. At the same time, heat treatment is applied to the entire substrate 3 to form the LOCOS oxide film 4. At this time, the LOCOS oxide film 4 is formed to have a thickness of, for example, about 1.2 to 1.8 μm in the flat portion.

  Next, as shown in FIG. 2, the silicon oxide film and the LOCOS oxide film 4 on the upper surface of the substrate 3 are removed by, for example, wet etching. In the scribe line region 2, a recess is formed from the substrate surface in the region where the LOCOS oxide film 4 was formed, and becomes an alignment mark 5. As described above, the thickness of the LOCOS oxide film 4 is about 1.2 to 1.8 μm, and the initial step t1 of the alignment mark 5 is about 0.54 to 0.81 μm.

Then, the surface of the substrate 3 is thermally oxidized to form a silicon oxide film on the entire surface, for example, about 0.03 to 0.05 μm. Thereafter, by using a known photolithographic technique, the initial step t1 of the alignment mark 5 is used to form a photoresist having an opening in a portion where the N type buried diffusion layer 6 is formed as a selection mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

Thereafter, by using a known photolithography technique, a photoresist having an opening provided in a portion where the first separation region 7 is formed is formed using the initial step t1 of the alignment mark 5 as a selection mask. Then, a P-type impurity, for example, boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

Next, as shown in FIG. 3, the silicon oxide film on the surface of the substrate 3 is removed, and the substrate 3 is placed on the susceptor of the epitaxial growth apparatus. Then, a high temperature of, for example, about 1200 ° C. is given to the substrate 3 by lamp heating, and SiHCl ₃ gas and H ₂ gas are introduced into the reaction tube. Thereby, an epitaxial layer 8 having a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of about 1.0 to 6.0 μm is grown on the substrate 3, for example.

  Here, also in the scribe line region 2, the epitaxial layer 8 is formed on the upper surface of the alignment mark 5 formed on the surface of the substrate 3. As a result, the step depth is shallower than the initial step t 1, but the step t 2 of the alignment mark 9 is also formed in the epitaxial layer 8. In this embodiment, the initial step t1 of the alignment mark 5 is about 0.54 to 0.81 μm. Therefore, the step t2 of the alignment mark 9 is formed without sagging. In particular, for example, even when the epitaxial layer thickness is 9 μm or more, by forming the alignment mark 5 of 0.54 μm or more as the initial step t1, the amount of reduction in the step t2 of the alignment mark 9 in the upper layer can be reduced.

Thereafter, the surface of the epitaxial layer 8 is thermally oxidized to form a silicon oxide film of about 0.03 to 0.05 μm, for example. Thereafter, using a step t2 of the alignment mark 9 by a known photolithography technique, a photoresist having an opening in a portion where the second isolation region 10 is formed is formed as a selection mask. Then, a P-type impurity, for example, boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

  Next, as shown in FIG. 4, a LOCOS oxide film 11 is formed in a desired region of the epitaxial layer 4. Here, the method of forming the LOCOS oxide film 11 is the same as the method described with reference to FIG. 1, so the description of FIG. Incidentally, by forming the LOCOS oxide film 11 on the P-type isolation region 12, the element isolation is further achieved. Further, the LOCOS oxide film 11 is formed with a thickness of, for example, about 0.5 to 1.0 μm in the flat portion.

Next, as shown in FIG. 5, a silicon oxide film is formed on the surface of the epitaxial layer 8 to a thickness of, for example, about 0.01 to 0.20 μm. Then, by using the step t2 of the alignment mark 9 by a known photolithography technique, a photoresist having an opening in a portion where the N type diffusion region 13 is formed is formed as a selection mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

Next, as shown in FIG. 6, a polysilicon film is deposited on the silicon oxide film, for example, about 0.2 to 0.3 μm. Thereafter, an N-type impurity, for example, phosphorus (P) is ion-implanted into the polysilicon film at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, the polysilicon film other than the gate electrode 14 formation region is removed by a known photolithography technique.

After that, as shown in the drawing, a photoresist having an opening in the portion where the P-type diffusion region 15 is formed is selected from the silicon oxide film by using the step t2 of the alignment mark 9 by a known photolithography technique. Form as a mask. Then, a P-type impurity, for example, boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.
At this time, ion implantation can be performed more accurately by using the gate electrode 14 as a mask.

Next, as shown in FIG. 7, openings are provided in the portions where the N type diffusion regions 16 and 17 are to be formed on the silicon oxide film 9 by using the step t2 of the alignment mark 9 by a known photolithography technique. The formed photoresist is formed as a selection mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

  Next, as shown in FIG. 8, a TEOS (Tetra-Ethyl-Orso-Silicate) film layer (not shown), a BPSG (Boron Phospho Silicate Glass) film layer 18 and the like are formed on substantially the entire upper surface of the epitaxial layer 8. .

  On the upper surface of the BPSG film layer 18 from which the silicon nitride film has been removed, contact holes 21 and 22 for the source electrode 19 or the drain electrode 20 of the MOS transistor are formed in the BPSG film layer 18 or the like by, for example, a known photolithography technique. At this time, the step t3 of the alignment mark 23 formed on the BPSG film layer 18 is used.

  Next, the barrier metal layer 24, the tungsten (W) layer 25, and the Al layer 26 are deposited by sputtering. At this time, the barrier metal layer 24 is formed by laminating a titanium (Ti) layer and a titanium nitride (TiN) layer. The W layer 25 is selectively formed in the contact hole 21 and 22 formation region, and the Al layer 26 is selectively formed in the electrode and first wiring layer formation region. By this step, the source electrode 19 and the drain electrode 20 of the MOS transistor are formed. In addition, although not shown, a first wiring layer of the semiconductor device is formed.

  Next, as shown in FIG. 9, an interlayer insulating layer between the first wiring layer and the second wiring layer 30, and between the second wiring layer 30 and the third wiring layer 34. An interlayer insulating layer and a third wiring layer 34 are formed. A TEOS film layer 27 is deposited on the top surface of the first wiring layer or the like. The TEOS film layer 27 has irregularities formed on the surface thereof by the first wiring layer or the like. In order to eliminate this unevenness and form a flat surface, liquid SOG (Spin On Glass) is applied to form the SOG film layer 28. Thereafter, a TEOS film layer 29 is deposited again on the SOG film layer 28. With this structure, it is possible to flatten the upper surface of the TEOS film layer 27 in which the uneven portion is formed by the first wiring layer or the like. Since the second wiring layer 30 is formed while maintaining flatness, it is possible to prevent the second wiring layer 30 from being short-circuited.

  Thereafter, the TEOS film layer 31, the SOG film layer 32, the TEOS film layer 33, and the third wiring layer 34 are formed on the upper surface of the second wiring layer 30 by the manufacturing method described above. Then, on the upper surface of the third wiring layer 34, for example, a silicon nitride film layer 35 is deposited on substantially the entire surface by a plasma CVD (plasma-enhanced chemical vapor deposition) method in a reduced pressure state at a formation temperature of 450 ° C. or less. A semiconductor device is completed.

  As described above, in the present embodiment, the LOCOS oxide film 4 is used when the alignment mark 5 is formed in the scribe line region 2 of the substrate 3. As a result, the alignment mark 5 having a deep initial step t1 is formed, and the amount of reduction in the alignment mark step can be mitigated also by the subsequent lamination of the epitaxial layer 8, the BPSG film layer 18, and the like. Even after the epitaxial layer 8 and the BPSG film layer 18 are stacked, they can be used as alignment marks when transferring the mask pattern to the photoresist. In the present embodiment, the case where the LOCOS oxide film 4 is used as the method for forming the alignment mark 5 has been described. However, the present invention is not limited to this case. For example, if the initial step t1 can be set to a desired depth, an arbitrary design change such as forming a trench or simply forming a thick oxide film is possible. Further, the region for forming the alignment mark is not limited to the scribe line region, and any design change can be made.

  Next, a second embodiment of the present invention will be described.

  First, as shown in FIG. 10, a P-type single crystal silicon substrate 43 is prepared.

  Here, the substrate 43 is prepared by performing processing such as lapping and polishing after slicing a silicon single crystal ingot. The main surface of the substrate 43 is a silicon surface whose plane orientation is substantially represented by (100). The crystal axis of the substrate 43 is inclined by 0.5 ° with respect to the crystal axis of the silicon surface whose plane orientation is approximately (100). Here, in this embodiment, the case where the crystal axis is tilted by 0.5 ° will be described, but the present invention is not limited to this case. For example, the design angle of the crystal axis can be arbitrarily changed, and the crystal layer may be stacked so that the epitaxial layer on the upper surface of the substrate 43 is tilted in a certain direction.

Then, the surface of the substrate 43 is thermally oxidized to form a silicon oxide film of about 0.03 to 0.05 μm, for example. In the element formation region 41, a photoresist having an opening provided in a portion where the N-type buried diffusion layer 44 is formed is formed by a known photolithography technique as a selection mask. Then, after selectively removing the silicon oxide film exposed from the selection mask, an N-type impurity such as phosphorus (P) is accelerated from the surface of the substrate 43 at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ¹³ to 1. Ion implantation at 0.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

  At this time, in the scribe line region 42, an N type buried diffusion layer 45 used for the alignment mark 47 (see FIG. 11) is formed. The N type buried diffusion layer 45 is formed simultaneously with the N type buried diffusion layer 44 and is formed by the above-described manufacturing method.

  Next, as shown in FIG. 11, the silicon oxide film formed on the surface of the substrate 43 is removed. At this time, in the N type buried diffusion regions 44 and 45, impurities are ion-implanted directly from the surface of the substrate 43, and then the surface of the substrate 43 is thermally oxidized when the impurities are diffused. As a result, recesses are formed in the N-type buried diffusion regions 44 and 45 with respect to the surface of the substrate 43 in the other regions, thereby forming alignment marks 47. The initial step t4 of the alignment mark 47 is about 0.12 μm.

After that, by using a known photolithography technique, using the initial step t4 of the alignment mark 47, a photoresist having an opening in a portion where the first isolation region 46 is formed is formed as a selection mask. Then, a P-type impurity, for example, boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

Next, as shown in FIG. 12, the silicon oxide film on the surface of the substrate 43 is removed, and the substrate 43 is placed on the susceptor of the epitaxial growth apparatus. Then, a high temperature of, for example, about 1200 ° C. is given to the substrate 43 by lamp heating, and SiHCl ₃ gas and H ₂ gas are introduced into the reaction tube. Thereby, an epitaxial layer 48 having a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of about 1.0 to 6.0 μm is grown on the substrate 43, for example.

  At this time, in the scribe line region 42, an alignment mark 49 is newly formed using the initial step t 4 of the alignment mark 47 formed on the substrate 43. As described above, since the crystal axis of the main surface of the substrate 43 is inclined in a certain direction, the alignment mark 49 is formed by moving, for example, α ° with respect to the alignment mark 47.

  That is, since the epitaxial layer 48 is deposited while moving in a certain direction, the reduction amount of the step t5 of the alignment mark 49 can be mitigated. For example, when the crystal axis is not tilted or hardly tilted, the epitaxial layer moves in a certain direction, making it difficult to stack, and the step t5 of the alignment mark 49 is likely to collapse or be buried. Therefore, in the present embodiment, a substrate 43 having a crystal axis on which the epitaxial layer 48 is stacked while being shifted in a certain direction is prepared. As a result, the amount of alignment mark reduction in the upper layer can be mitigated. Further, by reducing the movement of the epitaxial layer, the pattern design rule can be reduced, and high integration of elements can be realized.

  Thereafter, a MOS transistor is formed in the element formation region 41. Since the manufacturing method is the same as that in FIGS. 4 to 9 in the first embodiment, the first embodiment is described here. I will refer to it and omit its explanation.

  In the first and second embodiments described above, the case where the buried diffusion layer or the LOCOS oxide film is used to form a recess in the substrate and used as the initial step of the alignment make has been described. It is not limited to the case. For example, the same effect can be obtained also when the LOCOS oxide film is left on the substrate and the convex portion is formed on the substrate and used as the initial step of the alignment mark. In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Element formation area 2 Scribe line area 3 P type single crystal silicon substrate 4 LOCOS oxide film 5 Alignment mark 8 Epitaxial layer 9 Alignment mark 41 Element formation area 42 Scribe line area 43 P type single crystal silicon substrate 44 N type filling Embedded diffusion layer 45 N-type buried diffusion layer 47 Alignment mark 48 Epitaxial layer 49 Alignment mark

Claims (7)

Prepare a semiconductor substrate,
After selectively forming an oxide film on the substrate surface, by removing the oxide film, an initial step of a concave alignment mark is formed on the substrate surface,
At least one epitaxial layer is deposited on the surface of the substrate including the upper surface of the initial step, and a step of an alignment mark using the initial step is formed on the surface of the epitaxial layer. Method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a LOCOS oxide film is used as the oxide film. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the initial step is formed in a scribe line region of the substrate. Prepare a semiconductor substrate,
Selectively forming a LOCOS oxide film on the substrate surface, forming an initial step of an alignment mark convex to the substrate surface;
At least one epitaxial layer is deposited on the surface of the substrate including the upper surface of the initial step, and a step of an alignment mark using the initial step is formed on the surface of the epitaxial layer. Method. Preparing a silicon single crystal substrate having a main surface inclined with respect to the crystal axis of the silicon surface whose plane orientation is substantially represented by (100);
Impurities are injected from the main surface and diffused to form a diffusion layer, and an initial step of a concave alignment mark is formed on the main surface on which the diffusion layer is formed,
A method of manufacturing a semiconductor device, comprising depositing at least one epitaxial layer on the substrate surface including the upper surface of the initial step, and forming an alignment mark using the initial step on the surface of the epitaxial layer. 6. The main surface of the silicon single crystal substrate is characterized in that the crystal axis is inclined by 0.5 [deg.] With respect to the crystal axis of the silicon surface whose plane orientation is substantially represented by (100). Semiconductor device manufacturing method. The method of manufacturing a semiconductor device according to claim 5, wherein the concave initial step is formed in a scribe line region of the substrate.

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