JP2005281713A - Method for plating substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain satisfactory embedding characteristics uniform over the entire surface of a substrate in formation of a embedded metal wiring by plating formation. <P>SOLUTION: The substrate 4 is immersed into a plating solution 2 in a plating bath 1 and plating is formed on a principal surface of the substrate 4 while the substrate 4 and the plating solution 2 are relatively moved in such a manner that the relative speeds of the substrate 4 and the plating solution 2 in a direction along the principal surface of the substrate 4 are kept within the range from 0.03 to 1.5 m/sec. By forming the plating in such a manner, the accumulation of the additives included in the plating solution 2 in wiring grooves and near apertures of holes can be prevented and the occurrence of voids in metallic films can be suppressed when the metallic films are embedded into the fine wiring grooves and the holes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for plating a substrate, and more particularly to wiring formation using copper or the like.

With the miniaturization and speeding up of semiconductor devices, signal transmission delay due to an increase in parasitic capacitance between wirings and wiring resistance has become a problem. Since the signal transmission delay is proportional to the product of the inter-wiring parasitic capacitance and the wiring resistance, it is important to develop a manufacturing process for reducing both.
In order to reduce the parasitic capacitance between wirings, a technique for applying a low dielectric constant film as an interlayer insulating film has been developed. On the other hand, regarding the reduction of the wiring resistance, a shift to a copper wiring using a copper film having a resistance lower than that of a conventional aluminum wiring has been studied.

6, 8, and 9 are cross-sectional views illustrating a manufacturing process of a semiconductor device using a conventional plating method. In these drawings, the same portions are denoted by the same reference numerals, and redundant description is omitted.
Since the copper film is difficult to process by dry etching, in the conventional formation of copper wiring, as shown in FIG. 6, the narrow wiring groove 20a and the wide wiring groove 20b formed in the upper insulating film 19 are made of copper. By embedding the film and removing the copper film formed outside the wiring trench 20a and the wiring trench 20b, a buried wiring is formed.
In FIG. 6, 14 is a silicon substrate, 15 is a lower insulating film, 16 is a stopper film, 17 is a lower metal wiring, and 18 is a via hole.

In the above-described process of embedding the copper film, conventionally, for example, a plating apparatus as shown in FIG. 7 is used to form plating on the main surface of the substrate 4, and the copper film is formed in the wiring grooves 20a and 20b shown in FIG. The method of embedding is used.
In FIG. 7, 1 is a plating tank, 2 is a plating solution, 3 is a copper seed film, 5 is a holding plate, 6 is a substrate holder, 7 is a contact, 8 is a rotating shaft, 11 is a supply port, and 12 is an anode plate. , 13 indicate electric field correction plates.
Further, in order to form a metal film having a uniform thickness, as shown in FIG. 7 of the conventional example, an electric field correction plate 13 is provided inside the plating tank 1 to make the electric field distribution inside the plating tank 1 uniform. Further, in order to embed a fine wiring groove, the embeddability is improved by a method of providing a plurality of plating steps or adding an additive to the plating solution.

  Further, when the substrate 4 shown in FIG. 7 is immersed in the plating solution 2, the substrate 4 is made to prevent air from entering between the surface of the substrate 4 and the plating solution (air venting) and to make the plating film thickness uniform. It was necessary to immerse in the plating solution 2 while rotating at a high speed with the main surface of the substrate facing down and facing down (see, for example, Patent Document 1).

At this time, the relative speed between the substrate 4 and the plating solution 2 in the direction along the main surface of the substrate 4 increases as the distance from the center of the substrate 4 increases. For this reason, as the radius of the substrate 4 increases, the difference between the relative speed at the center of the substrate 4 and the relative speed at the end of the substrate 4 increases.
As described above, the plating solution 2 contains an additive for improving the embedding property, and the amount of the additive that comes into contact with the substrate 4 depends on the substrate 4 and the plating solution in the direction along the main surface of the substrate 4. Depends on the relative speed of 2. For this reason, as the radius of the substrate 4 increases, the difference between the amount of the additive that contacts the central portion of the substrate 4 and the amount of the additive that contacts the end portion of the substrate 4 increases.

On the other hand, when the center of the substrate 4 is directly above the supply port 11, the plating solution 2 supplied from the supply port 11 hits the surface of the substrate 4 substantially perpendicularly to the surface and toward the end of the surface of the substrate 4. It flows along the surface of the substrate 4. For this reason, the amount of the additive supplied to the end portion of the substrate is different from that in the central portion, and the deposition rate of copper on the surface of the substrate 4 also changes. As a result, the amount of the additive is not optimized, and voids 24 are formed in the metal film 23 embedded in the fine holes and grooves as shown in FIG. Further, when removing the metal film 23 formed outside the wiring groove, as shown in FIG. 9, the void 24 is exposed to the surface inside the wiring groove 20a having a small width, thereby reducing the reliability of the metal wiring. End up.
8 and 9, reference numerals 21, 21a, and 21b denote barrier metal films, reference numerals 22, 22a, and 22b denote copper seed films, and reference numerals 23a and 23b denote metal films.

Thus, in the process of forming the plating on the main surface of the substrate and embedding the copper film in the wiring groove, when the substrate is immersed in the plating solution while rotating, the substrate and the plating solution in the direction along the main surface of the substrate The relative speed of the substrate increases as it approaches the edge of the substrate, and the amount of the additive contained in the plating solution in contact with the substrate varies greatly between the center and the edge of the substrate.
For this reason, the embedding characteristics are not optimized over the entire surface of the substrate, voids are generated in the metal film embedded in the wiring grooves, and the voids are exposed on the surface in the subsequent process, reducing the reliability of the metal wiring. There was a problem of letting it go.
JP 2002-049494 A

  As described above, in the conventional plating method, when the buried metal wiring is formed by the plating apparatus, the amount of the additive contained in the plating solution in contact with the substrate is greatly different between the central portion and the end portion of the substrate. There is a problem that the embedding characteristics are not optimized over the entire surface, and voids are generated in the embedded metal wiring.

  The present invention has been made to solve the above problems, and provides a plating method capable of obtaining uniform and good embedding characteristics over the entire surface of a substrate in the formation of embedded metal wiring by plating. Objective.

In the plating method according to the present invention, a substrate is immersed in a plating solution in a plating tank, and a relative speed between the substrate and the plating solution in a direction along the main surface of the substrate is set to 0.03 to 1.5 m / second. In this range, plating is formed on the main surface of the substrate while relatively moving the substrate and the plating solution.
Other features of the present invention are described in detail below.

  According to the present invention, it is possible to obtain a plating method capable of obtaining uniform and good embedding characteristics over the entire surface of a substrate in the formation of embedded metal wiring by plating.

Embodiment As an example of a method for forming plating according to the present embodiment, an example in which an insulating film is formed on a main surface of a semiconductor substrate and a buried copper wiring is formed in the insulating film using a plating apparatus will be described.

FIG. 1 is a cross-sectional view schematically showing a plating apparatus used in the process of forming the metal wiring of the present embodiment.
In FIG. 1, a plating solution 2 is placed in a plating tank 1 having an opening at the top. Plating can be formed on the main surface of the substrate 4 by immersing the substrate 4 in the plating solution 2 from the upper part of the plating tank 1 in a face-down direction (the main surface of the substrate 4 faces downward).

First, the configuration of the plating apparatus will be described.
The substrate 4 is fixed by a pressing plate 5 and a substrate holder 6. On the main surface of the substrate 4, a copper seed film 3 for conducting electricity to the main surface of the substrate 4 is formed. A contact 7 for passing a current to the substrate 4 is attached along the inside of the substrate holder 6, and the tip of the contact 7 is in contact with the copper seed film 3 so as to be conductive. The rotating shaft 8 has a lower end attached to the central portion of the holding plate 5 in a direction perpendicular to the main surface of the substrate 4, and an upper end attached to the rotating arm 9. The rotating arm 9 is attached to the revolution shaft 10 on the center of the plating tank 1, and can rotate the rotation shaft 8 in the plating tank 1.
In the plating tank 1, a supply port 11 for supplying the plating solution 2 is provided at the center of the bottom. An anode plate 12 made of phosphorous copper is attached around the supply port 11. Further, an electric field correction plate 13 is attached to the side wall.

Next, a method for depositing metal on the main surface of the substrate 4 will be described.
First, as shown in FIG. 1, the plating solution 2 supplied to the inside of the plating tank 1 from the supply port 11 rises directly above the supply port 11, and the main portion of the silicon substrate 14 is located above the plating tank 1. It flows in a horizontal direction (direction D in FIG. 1) along the surface direction, and further overflows at the end of the plating tank 1. The overflowed plating solution 2 is collected and supplied again from the supply port 11 into the plating tank 1.
Here, when a current is passed from the anode plate 12 toward the substrate 4, the metal constituting the anode plate 12 emits electrons and becomes metal ions on the surface of the anode plate 12 and is eluted into the plating solution 2. Further, a copper seed film 3 is formed on the main surface of the substrate 4. When a current is passed through the contact 7, the eluted metal ions can receive electrons on the surface of the copper seed film 3. 4 is deposited as metal on the main surface.

Here, in the plating apparatus shown in FIG. 1, the substrate 4 is displaced in a direction parallel to the main surface thereof by moving the rotation shaft 8 in the direction along the longitudinal direction of the rotary arm 9 (direction A). Plating can be performed.
In addition, by rotating the rotation shaft 8 (both clockwise and counterclockwise in the direction B), plating can be performed while rotating the substrate 4 about the vertical axis of the main surface thereof. .
Furthermore, by rotating the rotating arm 9 around the revolution axis 10 (both clockwise and counterclockwise in the direction of C is possible), plating is performed while the substrate 4 is revolving in the plating tank 1. be able to.

  2, 3, and 5 show a method of manufacturing a semiconductor device in which a buried copper wiring is formed using the plating apparatus shown in FIG. 1 by the plating method of the present embodiment. It is process explanatory drawing demonstrated in order. In this embodiment, a silicon substrate having a diameter of 300 mm is used as a substrate for forming a semiconductor device. In these drawings, the same portions are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 2 is a cross-sectional view after forming a wiring groove on the main surface of the silicon substrate by lithography and etching in the manufacturing process of the semiconductor device according to the present embodiment. In FIG. 2, a lower insulating film 15 made of a silicon oxide film or the like and a stopper film 16 made of a silicon nitride film are formed on a silicon substrate 14, and a lower metal wiring 17 made of aluminum or the like is formed in the lower insulating film 15. Forming. Further, the stopper film 16 and the lower insulating film 15 are opened to form a via hole 18, and the upper insulating film 19 made of a silicon oxide film or the like is opened by lithography and etching to form a wiring groove 20a and a wiring groove 20b. ing. The wiring trench 20a has a width of about 170 nm and a depth of about 1000 nm. On the other hand, the wiring trench 20b has a width of about 2000 nm and a depth of about 1000 nm. Accordingly, the wiring groove 20a is a wiring groove that has substantially the same depth and a small width as the wiring groove 20b.

Next, as shown in FIG. 3, a barrier metal film 21 made of Ta is formed on the inner surfaces of the wiring groove 20a and the wiring groove 20b as an adhesion layer with a film thickness of about 30 nm. At this time, the barrier metal film 21 leaves the grooves on the inner surfaces of the wiring grooves 20a and 20b.
Next, a copper seed film 22 for plating is formed on the inner surface of the groove formed of the barrier metal film 21 by physical vapor deposition so as to leave the groove with a film thickness of about 75 nm.

Further, as shown in FIG. 3, a copper film 23 is formed on the inner surface of the groove formed of the copper seed film 22 with a film thickness of about 1000 nm by the plating apparatus shown in FIG.
Here, the process of forming the copper film 23 will be described in detail. A copper sulfate bath is used as the plating solution 2 shown in FIG. The copper sulfate bath is composed of copper sulfate, sulfuric acid, and water as main components, with a small amount of chlorine ions and additives added.

  Here, the silicon substrate 14 is immersed in the plating solution 2 in the plating tank 1, and the relative speed between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is 0.03 to 1.5 m / second. In this range, plating is performed on the main surface of the silicon substrate 14 while relatively moving the silicon substrate 14 and the plating solution 2. The specific method will be described below.

In the first plating forming method, in the vicinity of the upper part of the plating tank 1, the flow rate of the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec. In this method, plating is performed by adjusting the flow rate of the plating solution 2.
At this time, the plating is performed by fixing the silicon substrate 14 at a position where the flow rate of the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec. To.
For example, in the plating tank 1, the silicon substrate 14 is fixed at a position where the end of the silicon substrate 14 is separated by 50 mm or more from directly above the end of the supply port 11, and is along the main surface of the silicon substrate 14. The plating is performed so that the flow rate of the plating solution in the direction is in the range of 0.1 to 0.3 m / sec over the entire surface of the silicon substrate 14.

Next, in the second plating forming method, the rotation axis 8 is moved in the direction along the longitudinal direction of the rotary arm 9 (A in FIG. 1), so that the silicon substrate 14 is parallel to the main surface of the silicon substrate 14. In this method, the plating is formed while being displaced. At this time, the flow rate of the plating solution 2, the silicon substrate so that the relative velocity between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec. This is done by adjusting the range, direction, and speed of displacement of 14.
For example, in the region where the flow rate of the plating solution 2 in the direction along the main surface of the silicon substrate 14 in the plating tank 1 is 0.1 to 0.2 m / second, the main surface of the silicon substrate 14 is aligned. The plating is performed while displacing the silicon substrate 14 so that the relative speed of the silicon substrate 14 and the plating solution 2 in the direction is in the range of 0.03 to 1.5 m / sec over the entire surface of the silicon substrate 14.

Next, the third plating forming method is a method of forming plating while rotating the rotation shaft 8 (B in FIG. 1) to rotate the silicon substrate 14 around the vertical axis of the main surface of the silicon substrate 14. It is. At this time, the flow rate of the plating solution 2, the silicon substrate so that the relative velocity between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec. The position where the 14 is rotated and the rotation speed are adjusted to form the plating.
For example, the plating is formed while rotating the silicon substrate 14 at a rotation speed of 30 rpm. At this time, the speed is 0.47 m / sec at the end of the silicon substrate 14 and is almost 0 m / sec at the center, so that the flow rate of the plating solution 2 is adjusted as appropriate along the main surface of the silicon substrate 14. The flow rate of the plating solution 2 is adjusted so that the relative speed between the silicon substrate 14 and the plating solution 2 in the direction is in the range of 0.03 to 1.5 m / sec over the entire surface of the silicon substrate 14.

Furthermore, the fourth plating forming method is a method of forming plating by rotating the rotating arm 9 around the revolution axis 10 (C in FIG. 1). At this time, the flow rate of the plating solution 2, the silicon substrate so that the relative velocity between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec. Plating is performed by appropriately adjusting the radius of revolution 14 and the revolution speed.
For example, the plating is formed while revolving so that the revolution radius of the silicon substrate 14 is 200 mm and the revolution speed is 20 rpm. At this time, the innermost speed of revolution is 0.1 m / sec, and the outermost speed is 0.37 m / sec. In this way, the relative speed between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec over the entire surface of the silicon substrate 14. The plating is performed by appropriately adjusting the flow rate of the plating solution 2.

  The first, second, third, and fourth plating forming methods have been described above. By appropriately combining these forming methods, the silicon substrate 14 and the plating solution in the direction along the main surface of the silicon substrate 14 are combined. The plating may be carried out so that the relative speed to 2 is in the range of 0.03 to 1.5 m / sec over the entire surface of the silicon substrate 14.

FIG. 4 compares the incidence of voids generated inside the wiring groove 20a for each rotation speed of the silicon substrate 14 when the copper film 23 (see FIG. 3) is formed by the third plating method described above. It is a graph. E and F are the void generation rates at the center and end of the silicon substrate 14, respectively. Here, the flow rate of the plating solution 2 is assumed to be zero.
When the rotation speed of the silicon substrate 14 is 150 rpm, the void generation rate E at the center of the silicon substrate 14 is 3%, and the void generation rate F at the end is 9%. Next, when the rotational speed is 100 rpm, the void generation rate E at the center of the silicon substrate 14 is 0%, and the void generation rate F at the end is 6%. Furthermore, when the rotational speed is 2 rpm, the void generation rate E at the center and the void generation rate F at the end are both 0%. Although not shown, when the rotational speed is zero, the void generation rate is slightly larger at both the center and the end than at 2 rpm.
Furthermore, although not shown, when the rotational speed is in the range of 30 to 60 rpm, the void generation rate at the end of the silicon substrate 14 can be reduced with good reproducibility.

Here, in this embodiment, since a silicon substrate having a diameter of 300 mm is used, when the silicon substrate 14 is rotated at 2 rpm, 100 rpm, and 150 rpm, the speed at the end of the silicon substrate 14 is 0.03 m / sec. 1.6 m / sec, 2.4 m / sec.
Focusing on the void generation rate F at the end of the silicon substrate 14, it is considered that the void generation rate is reduced by setting the speed of the end to a range of 0.03 to 1.5 m / sec.
Accordingly, when the relative velocity between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec over the entire surface of the silicon substrate 14, the wiring groove 20a. The generation rate of voids generated in the interior of the can be reduced.
Further, when the rotational speed is in the range of 30 to 60 rpm, the speed of the end portion of the silicon substrate 14 is 0.5 to 0.9 m / second, so that the relative speed is 0.5 to 0.9 m / second. If it is within the range, the void generation rate can be reduced with good reproducibility, which is more preferable.

This result can be explained as follows.
When the relative velocity between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is smaller than 0.03 m / second or larger than 1.5 m / second, the main surface of the silicon substrate 14 The plating solution 2 flowing along substantially parallel is less likely to enter the wiring groove 20a. For this reason, the flow of the plating solution 2 becomes very small in the wiring groove 20a, and the additive accumulates in the vicinity of the opening of the wiring groove 20a. As a result, copper deposition at this portion is extremely suppressed, and voids are formed.
On the other hand, when the relative speed between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec, the plating solution 2 is used as a wiring groove. 20a can be stably entered, and the additive does not accumulate in the vicinity of the opening of the wiring groove 20a, so that formation of voids can be prevented.

Thereafter, as shown in FIG. 5, the barrier metal film 21, the copper seed film 22 and the copper film 23 (see FIG. 3) formed outside the wiring trench 20a and the wiring trench 20b are subjected to chemical mechanical polishing (CMP). ) To form a buried copper film 23a together with the barrier metal film 21a and the copper seed film 22a inside the wiring trench 20a, and to fill the buried copper film 23b together with the barrier metal film 21b and the copper seed film 22b inside the wiring trench 20b. Form.
At this time, in the step of forming the copper film 23 (see FIG. 3), the silicon substrate 14 is immersed in the plating solution 2 in the plating tank 1 shown in FIG. 1, and silicon in the direction along the main surface of the silicon substrate 14 is obtained. The relative speed of the substrate 14 and the plating solution 2 is in the range of 0.03 to 1.5 m / second, and the silicon substrate 14 and the plating solution 2 are moved relative to each other on the main surface of the silicon substrate 14. Since plating is formed, the copper film is satisfactorily embedded in the embedded copper film 23a without generating voids in the wiring groove 20a.

In the present embodiment, the relative speed of the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14 is in the range of 0.03 to 1.5 m / sec. The plating is formed on the main surface of the silicon substrate 14 while relatively moving the plating solution 2 and the plating solution 2, but the relative speed is adjusted to be in the range of 0.5 to 0.9 m / sec. Therefore, the void generation rate can be suppressed with good reproducibility, which is more preferable.
Further, in this embodiment, a silicon substrate having a large diameter of 300 mm is used, and when the above relative speed is obtained by rotating the silicon substrate 14, the speed of the substrate end portion is greatly different from that of the central portion. Therefore, as shown in the present embodiment, the above relative speed can be made uniform over the entire surface of the substrate by a combination of horizontal displacement of the substrate, revolution, and adjustment of the flow rate of the plating solution. This is suitable when a large-diameter substrate is used.

As described above, in the present embodiment, the silicon substrate 14 is immersed in the plating solution 2 in the plating tank 1, and the relative speed between the silicon substrate 14 and the plating solution 2 in the direction along the main surface of the silicon substrate 14. In this way, plating is formed on the main surface of the silicon substrate 14 while relatively moving the silicon substrate 14 and the plating solution 2 so that the range of 0.03 to 1.5 m / sec is reached.
By forming in this way, when the copper film is embedded in the wiring groove or hole to be embedded, the additive is prevented from collecting near the opening of the wiring groove or hole, and the generation of voids is suppressed. Can do.

  Therefore, in the formation of the buried metal wiring by plating, an excellent method for manufacturing a semiconductor device can be obtained, which can obtain uniform and good filling characteristics over the entire surface of the substrate.

The cross-sectional schematic diagram of the plating apparatus used for embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of embodiment of this invention. The figure which shows the incidence rate of the void by embodiment of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of embodiment of this invention. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. The cross-sectional schematic diagram of the plating apparatus used for the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Plating tank, 2 Plating solution, 3 Copper seed film, 4 Substrate, 5 Presser plate, 6 Substrate holder, 7 Contact, 8 Rotating shaft, 9 Rotating arm, 10 Revolving shaft, 11 Supply port, 12 Anode plate, 13 Electric field correction Plate, 14 silicon substrate, 15 lower insulating film, 16 stopper film, 17 lower metal wiring, 18 via hole, 19 upper insulating film, 20a wiring groove, 20b wiring groove, 21 barrier metal film, 22 copper seed film, 23 copper film, 24 Void.

Claims (4)

  Immerse the substrate in the plating solution in the plating tank, and the relative velocity between the substrate and the plating solution in the direction along the main surface of the substrate is in the range of 0.03 to 1.5 m / second, Plating is formed on the main surface of the substrate while relatively moving the substrate and the plating solution.   The plating method according to claim 1, wherein the plating is performed while displacing the substrate in a direction parallel to the main surface of the substrate.   The plating method according to claim 1 or 2, wherein the plating is performed while rotating the substrate about a vertical axis of the main surface of the substrate.   4. The plating method according to claim 1, wherein the plating is performed while the substrate is revolved in the plating tank.

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