JP2005269564A - High-frequency module and communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency module which has realized size reduction as a whole, without deteriorating the electrical characteristics of transmission filter and reception filter, by forming an impedance adjusting circuit using a capacitive component and an inductive component equipped within a multi-layer board. <P>SOLUTION: A board of a high-frequency module is composed of a multi-layer board, a circuit composed of two inter-ground capacitive components C1 and C2 and an inductive component L1 connected between the two inter-ground capacity components C1 and C2 is adopted as an impedance-adjusting circuit, and the inter-ground capacitive components C1 and C2 and the inductive component L1 are equipped within the multi-layer board. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a high-frequency module in which a high-frequency power amplifier circuit, a transmission / reception filter and the like are mounted on a dielectric multilayer substrate, and a communication device such as a mobile phone on which the high-frequency module is mounted.

In recent years, cellular phones have been widely used, and functions and services of cellular phones have been improved. In such a cellular phone, a high-frequency signal processing circuit necessary for the configuration of each transmission / reception system is mounted on a substrate.
In a conventional general configuration of a high-frequency signal processing circuit, a transmission filter and a reception filter are provided for switching between a reception signal input from an antenna and a transmission signal fed to the antenna.

The reception signal that has entered from the antenna is input to the reception filter through an impedance adjustment circuit provided in the preceding stage of the reception filter, where the reception signal is selectively passed. The received signal that has passed is amplified by a low noise amplifier and supplied to a signal processing circuit.
On the other hand, the transmission signal is passed through a high frequency filter that allows transmission signals in a predetermined transmission pass band to pass through, and is transmitted to the high frequency power amplifier circuit. The high frequency power amplifier circuit amplifies the power of the transmission signal and supplies it to the transmission filter.

The impedance adjustment circuit is connected between the transmission / reception shared terminal and the reception filter, and plays a role of phase rotation of the reception band impedance of the reception filter to the vicinity of the open state.
Conventionally, a method of rotating the phase by using one strip line in the impedance adjustment circuit is applied.

Further, since the impedance of the pass band is located at 50Ω, the matching state can be maintained regardless of the length of the stripline by designing the stripline to be 50Ω.
As a result, the transmission filter and the reception filter can be impedance-matched so that the transmission signal does not flow to the reception side and the reception signal does not flow to the transmission side.
JP 2002-171137 A

However, in the above configuration, since the strip line becomes long, the occupied area in the dielectric layer becomes large.
In addition to this, since it is necessary to design the strip line to be 50Ω in order to function as an impedance adjustment circuit, the upper and lower dielectric layers sandwiching the strip line require a dielectric-only region without other conductor patterns. To do.

For this reason, conductor patterns of other circuits cannot be arranged in the lower region of the multilayer substrate on which the transmission filter and the reception filter are installed, which is an adverse effect of downsizing the high-frequency module.
In the present invention, the impedance adjustment circuit is composed of a capacitive element and an inductive element built in a multilayer substrate, thereby realizing a high-frequency reduction in overall size without deteriorating the electrical characteristics of the transmission filter and the reception filter. An object is to provide a module and a communication device in which the module is mounted.

The high-frequency module according to the present invention includes a multilayer substrate as a module substrate, and a circuit including two grounded capacitive elements and an inductive element connected between the two grounded capacitive elements as an impedance adjustment circuit. And the grounded capacitive element and the inductive element are housed in the multilayer substrate.
Further, the high frequency module of the present invention comprises a multilayer substrate as a module substrate, two capacitive elements connected in series as an impedance adjustment circuit, one terminal connected between the two capacitive elements, and A circuit composed of an inductive element whose other terminal is grounded is adopted, and the capacitive element and the inductive element are incorporated in the multilayer substrate.

According to each of the above-described configurations, since the impedance adjustment circuit is configured by a combination of a capacitive element and an inductive element, the area occupied by the impedance adjustment circuit in the high-frequency module can be reduced as compared with a case where only the strip line is configured. Thereby, the whole high frequency module can be reduced in size.
The inductive element is preferably constituted by a transmission line formed in one or a plurality of dielectric layers in a multilayer substrate, and the capacitive element is a pair of capacitors formed with the dielectric layer in the multilayer substrate interposed therebetween. It is preferable to use an electrode.

Further, if the capacitive element and the inductive element are provided in a lower region of the multilayer substrate in which the transmission filter and the reception filter are installed, a demultiplexing circuit or a directional coupler is provided inside the multilayer substrate. The area for mounting the conductor pattern of other circuits and the like can be secured, and a compact high-frequency module can be obtained as a whole.
As the multilayer substrate, a multilayer ceramic substrate including a ceramic dielectric layer can be used. In the conventional resin substrate, it is difficult to reduce the size of the entire high-frequency module because the area becomes large to install the impedance adjustment circuit. The relative dielectric constant of the ceramic dielectric is higher than that of the resin substrate, and is usually 9 to 25. For this reason, the dielectric layer can be thinned, the size of the element of the impedance adjustment circuit incorporated in the dielectric layer can be reduced, and the distance between the elements can also be reduced. Therefore, further downsizing and integration can be realized as compared with the case of using a resin substrate.

  The present invention also relates to a communication device such as a mobile phone which is mounted with the high-frequency module described above and which is downsized as a whole.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram of a CDMA dual-band high-frequency signal processing circuit used for mobile communication devices such as mobile phones.
In this CDMA dual band system, a GPS reception band of 1.5 GHz band is used in order to use two transmission / reception systems having a frequency band of a cellular system 800 MHz band and a PCS system 1.9 GHz band and a positioning function by GPS (Global Positioning System). And one receiving system having

  In FIG. 1, 1 is an antenna, 2 is a demultiplexing circuit including a low-pass filter LPF and a high-pass filter HPF for dividing a frequency band, 3a is a transmission filter for separating a transmission system in the 1.9 GHz band, and 3b is A reception filter for separating the reception system, 4a is a transmission filter for separating the transmission system in the 800 MHz band, and 4b is a reception filter for separating the reception system. Reference numeral 12 denotes a filter for passing a GPS signal taken from the branching circuit 2. Reference numerals 3c and 4c denote impedance adjustment circuits that rotate the phase of the received signal.

The transmission filters 3a and 4a and the reception filters 3b and 4b are composed of SAW (Surface Acoustic Wave) filter elements.
A signal flow in the transmission system will be described. The cellular transmission signal output from the transmission signal processing circuit RFIC 17 has its noise reduced by the band pass filter BPF 9 and is transmitted to the high frequency power amplifier circuit 7. The PCS transmission signal output from the transmission signal processing circuit RFIC 17 is reduced in noise by the band pass filter BPF 10 and transmitted to the high frequency power amplifier circuit 8.

The high frequency power amplifier circuits 7 and 8 amplify the power of transmission signals in the 800 MHz band and 1.9 GHz band, respectively. The amplified transmission signal passes through the directional couplers 5 and 6 and is input to the transmission filters 4a and 3a.
The directional couplers 5 and 6 are for monitoring the level of output signals from the high-frequency power amplifier circuits 7 and 8 and for performing auto power control of the high-frequency power amplifier circuit based on the monitor signals. The monitor output is input to the detection circuit 11.

  On the other hand, the reception system includes low noise amplifiers LNAs 14 and 13 for amplifying the reception signals separated by the reception filters 4b and 3b, and high frequency filters 16 and 15 for removing noise from the reception signals. The received signals that have passed through the high frequency filters 16 and 15 are transmitted to the received signal processing circuit RFIC 18 and processed. The GPS signal separated by the GPS filter 12 is input to the received signal processing circuit RFIC 18 for signal processing.

The configuration of each filter is not limited, but preferably 36 ° Y cut-X propagation LiTaO ₃ crystal, 64 ° Y cut-X propagation LiNbO ₃ crystal, 45 ° X cut-Z propagation LiB ₄ O ₇ crystal. This is a SAW filter in which comb-like IDT (Inter Digital Transducer) electrodes are formed on a substrate made of, for example.
The configuration of the high-frequency power amplifier circuits 7 and 8 is not limited, but preferably, a GaAsHBT (gallium arsenide heterojunction bipolar transistor) structure or a P-HEMT structure transistor in order to reduce the size and increase the efficiency. Is formed of a semiconductor device including a GaAs transistor, silicon or germanium transistor.

In mobile communication devices equipped with a high-frequency signal processing circuit having the above-described configuration, there is a great demand for downsizing and weight reduction of each part. In consideration of these requirements, a high-frequency signal processing circuit has desired characteristics. It is modularized in units that can be achieved.
That is, as indicated by a solid line 22 in FIG. 1, a demultiplexing system including the demultiplexing circuit 2, the transmission / reception filters 3a, 3b, 4a, 4b, the high frequency power amplification circuits 7, 8, the directional couplers 5, 6, and the like. The circuit and the transmission system circuit form one high-frequency module 22 formed on one substrate.

A mounting method is also possible in which the high-frequency module 22 is divided into a high-frequency module in the 800 MHz band and two high-frequency modules in the 1.9 GHz band. Further, a module including the low noise amplifiers LNA 13 and 14 and the reception high frequency filters 15 and 16 may be additionally formed.
Hereinafter, description will be given based on one high-frequency module 22 including two frequency bands of 800 MHz band and 1.9 GHz band.

2 is a plan view of the high-frequency module 22, FIG. 3 is a sectional view thereof, and FIG. 4 is an external perspective view.
The high-frequency module 22 has a multilayer substrate structure in which a plurality of dielectric layers having the same size and shape are stacked. Reference numeral 40 denotes a ground layer provided in the lowermost layer. Reference numeral 28 denotes an external terminal for signal input / output provided around the ground layer 40.

On the surface layer of the multilayer substrate 23, in addition to various patterns and various chip components, BPF 9, 10, GPS filter 12, detection circuit 11, transmission / reception filters 3a, 4a, 3b, 4b, and high-frequency power amplification circuit 7 , 8 are mounted on power amplification semiconductor elements 24, 25, etc., which are joined to the conductor pattern on the dielectric layer by soldering or the like.
The power amplification semiconductor elements 24 and 25 are connected to the conductor pattern on the multilayer substrate 23 by wire bonding. Around the power amplifying semiconductor elements 24 and 25, output matching circuits 26 and 27 that are also part of the high-frequency power amplifying circuits 7 and 8 are formed by chip parts or conductor patterns.

The power amplification semiconductor elements 24 and 25, the output matching circuits 26 and 27, and the like may be mounted on the back surface of the multilayer substrate.
Inside the multilayer substrate 23, impedance adjustment circuits 3 c and 4 c (collectively referred to as “impedance adjustment circuit C”), a branching circuit 2, and directional couplers 5 and 6 are housed.

Speaking structurally, conductor patterns such as distributed constant lines, coupled lines, distributed capacitors, resistors, and the like constituting these internal elements are respectively formed in the dielectric layers.
In each dielectric layer, via conductors necessary for vertically connecting circuits are formed across a plurality of layers. In particular, reference numeral 50 in FIG. 3 denotes a thermal via conductor that vertically passes through the dielectric layer and is provided to release heat generated in the power amplification semiconductor elements 24 and 25 to the ground layer 40.

Each dielectric layer is formed by, for example, forming a conductor pattern with a conductor such as copper foil on an organic dielectric substrate such as a glass epoxy resin, and laminating and thermosetting, or a ceramic material or the like. Various conductor patterns are formed on the inorganic dielectric layer, and these are laminated and fired at the same time.
In particular, if a ceramic material is used, the dielectric constant of the ceramic dielectric is usually 7 to 25, which is higher than that of the resin substrate. Therefore, the dielectric layer can be made thin, and the size of the circuit element embedded in the dielectric layer can be reduced. The distance between the elements can be reduced, and the distance between the elements can also be reduced.

In particular, it is desirable to use a ceramic material that can be fired at a low temperature, such as glass ceramics, because the conductor pattern can be formed of low resistance copper, silver, or the like. The via conductor is formed by plating the through hole formed in the dielectric layer or filling the through hole with a conductive paste.
FIG. 5 is a circuit diagram showing an embodiment of the impedance adjustment circuit C. In FIG. 5, the filter corresponding to the filter 3a or 4a in FIG. A filter corresponding to the filters 3b and 4b in FIG.

The impedance adjustment circuit C is inserted between the output terminal of the branching circuit 2 and the reception filter B.
The impedance adjustment circuit C includes a series induction element L1 and two capacitance elements C1 and C2 provided between both ends of the series induction element L1 and the ground.
FIG. 6 is a Smith chart showing the impedance when the impedance adjustment circuit C is viewed from the input point of the reception filter B. FIG.

In the figure, black circles indicate the impedance in the pass band of the reception filter B, and black triangles indicate the impedance in the stop band of the reception filter B. The locus of the impedance in the pass band that is changed by the impedance adjustment circuit C is indicated by a broken line arrow, and the locus of the impedance in the blocking area is indicated by a solid arrow.
In the case where the impedance adjustment circuit C is not provided and the branching circuit 2 and the reception filter B are short-circuited, the impedance in the stop band is about 40 ° from the reactance 0 state to the capacitive side. When the circuit C is connected, the phase can be rotated clockwise to the vicinity of the open state.

In the pass band, by adjusting the values of the two capacitive elements C1 and C2 and the inductive element L1 in FIG. 6, the impedance of the pass band draws a locus indicated by a dashed arrow from the center 50Ω point, and again Rotate to position at 50Ω.
Thereby, an impedance matching state can be maintained. Therefore, it is possible to match the transmission filter A and the reception filter B and prevent the transmission signal from flowing to the reception side and the reception signal from flowing to the transmission side.

FIG. 7 is a plan perspective view showing the internal line pattern of the multilayer board of the impedance adjustment circuit C of FIG. 5, in which the internal line pattern of the multilayer board is indicated by a solid line and the terminal pattern of the surface layer is indicated by a dotted line.
As shown in FIG. 7, a transmission filter input terminal 609, a transmission filter output terminal 610, a reception filter input terminal 612, a reception filter output terminal 613, and GND connection terminals 611a and 611b are formed on the surface layer of the multilayer substrate 23. .

Inside the multilayer substrate, transmission lines 614a, 614b, 614c constituting the inductive element L1 of the impedance adjusting circuit C, via conductors 622b, 622c connected to the end of the inductive element L1, and electrodes 615 of the capacitive elements C1, C2 , 616 are formed.
Next, an element structure in the multilayer substrate of the impedance adjustment circuit C will be described with reference to FIG.
The multilayer substrate 23 is formed by sequentially laminating dielectric layers 601 to 606. The front dielectric layer 601 has a transmission filter input terminal 609 and a transmission filter output terminal 610 for connecting the transmission filter A, and a reception filter input terminal 612 and a reception filter output terminal 613 for connecting the reception filter B. The GND connection terminals 611a and 611b are formed in a conductor pattern.

The GND connection terminals 611a and 611b are connected to the back conductor 40 through via conductors 622f to 622i.
On the back surface of the dielectric layer 606, a back conductor 40 connected to GND, a reception signal external output terminal 619, and an antenna terminal 621 are formed.
The inductive element L1 constituting the impedance adjustment circuit C includes transmission lines 614a, 614b, and 614c provided in the plurality of dielectric layers 602, 603, and 604 and via conductors 622b and 622c for connecting the transmission lines. Consists of. The transmission lines 614a, 614b, and 614c are configured to circulate by being connected by via conductors 622b and 622c.

The capacitive element C1 constituting the impedance adjustment circuit C is formed between the capacitor electrode 615 formed on the dielectric layer 605 and the back conductor 40, and the capacitive element C2 is formed on the capacitor electrode 616 formed on the dielectric layer 605. It is formed between the back conductor 40.
The connection between the capacitive element C1 and the induction element L1 is made by a via conductor 622a passing through the dielectric layer, and the connection between the induction element L1 and the capacitive element C2 is made by a via conductor 622d passing through the dielectric layer.

The flow of signals in the above impedance adjustment circuit C is as follows.
The transmission signal output from the power amplifier circuit is transmitted to the branching circuit 2 after being transmitted in the order of the transmission filter input terminal 609, the transmission filter A, the transmission filter output terminal 610, the via conductor 622a, and the branching circuit connection line 617. Entered. A transmission signal that has passed through the branching circuit 2 is transmitted in the order of the branching circuit connection line 618, the via conductor 622j, and the antenna terminal 621, and is output to the outside.

Next, the transmission path of the received signal will be described. First, when a signal including a plurality of transmission / reception systems is received at the antenna terminal 621, the signal is input to the branching circuit 2 in the order of the via conductor 622 j and the branching circuit connection line 618.
The received signal that has passed only the desired transmission / reception frequency signal in the demultiplexing circuit 2 is connected to the impedance adjustment circuit C via the demultiplexing circuit connection line 617. In the impedance adjustment circuit C, the received signal is connected to the reception filter input terminal 612 via the transmission line 614a, the via conductor 622b, the transmission line 614b, the via conductor 622c, the transmission line 614c, and the via conductor 622d constituting the inductive element L1. The The branch circuit connection line 617 is connected to the capacitor electrode 615 through the via conductor 622a, and a capacitor C1 is formed between the capacitor electrode 615 and the back conductor 40. Further, the via conductor 622d is connected to the capacitor electrode 616, and a capacitor C2 is formed between the capacitor electrode 616 and the back conductor 40. Then, the signal is transmitted to the reception signal external output terminal 619 through the reception filter input terminal 612, the reception filter B, the reception filter output terminal 613, and the via conductor 622e.

On the other hand, a comparative example using a strip line for the impedance adjustment circuit C is shown in FIG. In FIG. 13, a folded strip line is formed on one dielectric layer.
As is clear from comparison between FIG. 7 and FIG. 13, it can be seen that the arrangement of the impedance adjustment circuit C in FIG. 7 can reduce the occupied volume to about ¼. Unlike FIG. 13, in the present invention, even if a pattern of another circuit is arranged around the impedance adjustment circuit C, the influence on the reactance value and capacitance value to be formed is very small. The pattern of the other circuit or the like can be arranged in the area in the multilayer substrate below the transmission filter A and the reception filter B. As a result, the high-frequency module can be reduced in size.

Next, another embodiment of the impedance adjustment circuit C of the present invention is shown in FIG.
The impedance adjustment circuit C is inserted between the output terminal of the branching circuit 2 and the reception filter B. The impedance adjustment circuit C includes series capacitance elements C3 and C4 and an inductor element L2 provided between the connection point of the series capacitance elements C3 and C4 and the ground.
FIG. 10 is a Smith chart showing the impedance of the impedance adjustment circuit C viewed from the input point of the reception filter B.

In the figure, black circles indicate the impedance in the pass band of the reception filter B, and black triangles indicate the impedance in the stop band of the reception filter B. The locus of the impedance in the pass band that is changed by the impedance adjustment circuit C is indicated by a broken line arrow, and the locus of the impedance in the blocking area is indicated by a solid arrow.
In the case where the impedance adjustment circuit C is not provided and the branching circuit 2 and the reception filter B are short-circuited, the impedance in the stop band is about 40 ° from the reactance 0 state to the capacitive side. When the circuit C is connected, the phase can be rotated counterclockwise to the vicinity of the open state.

Further, in the passband, by adjusting the values of the two capacitive elements C3 and C4 and the inductive element L2 in FIG. 9, the impedance of the passband draws a locus indicated by a broken line arrow from the center 50Ω, and again 50Ω Rotate to position
Thereby, an impedance matching state can be maintained. Therefore, the transmission filter A and the reception filter B can be matched, and the transmission signal can be prevented from flowing to the reception side, and the reception signal can be prevented from flowing to the transmission side.

FIG. 11 is a plan perspective view showing the interior line pattern in the multilayer substrate of the impedance adjustment circuit C in FIG. 9, and the interior line pattern of the multilayer substrate is indicated by a solid line, and the terminal pattern of the surface layer is indicated by a dotted line.
As shown in FIG. 11, a transmission filter input terminal 909, a transmission filter output terminal 910, a reception filter input terminal 912, a reception filter output terminal 913, and GND connection terminals 911a and 911b are formed on the surface layer of the multilayer substrate 23. .

In the interior of the multilayer substrate 23, transmission lines 917a, 917b and via conductors 923c, 923d, 923e, capacitor electrodes 914a, 914b, 915a, 915b, connection lines 916, and via conductors 923a that constitute the inductive element L2 of the impedance adjustment circuit C are provided. , 923b.
Next, the element structure in the multilayer substrate of the impedance adjustment circuit C will be described with reference to FIG.

The multilayer substrate 23 is formed by sequentially laminating dielectric layers 901 to 906.
The front dielectric layer 901 has a transmission filter input terminal 909 and a transmission filter output terminal 910 for connecting the transmission filter A, and a reception filter input terminal 912 and a reception filter output terminal 913 for connecting the reception filter B. The GND connection terminals 911a and 911b are formed of a conductor pattern.

The GND connection terminals 911a and 911b are connected to the back conductor 40 through via conductors 923g to 923j. On the back surface of the dielectric layer 906, a back conductor 40 connected to the GND, a reception signal external output terminal 920, and an antenna terminal 922 are formed.
On the back surface, a back conductor 40 connected to GND, a reception signal external output terminal 920, and an antenna terminal 922 are formed.

The inductive element L2 constituting the impedance adjustment circuit C includes transmission lines 917a and 917b provided in the plurality of dielectric layers 904 and 905, and via conductors 923d for connecting the transmission lines. The transmission lines 917a and 917b are configured to circulate by being connected by the via conductor 923d.
The capacitive element C3 constituting the impedance adjustment circuit C is formed between the capacitor electrode 914a formed on the dielectric layer 902 and the capacitor electrode 914b formed on the dielectric layer 903. The capacitive element C4 is formed between the capacitor electrode 915a formed on the dielectric layer 902 and the capacitor electrode 915b formed on the dielectric layer 903. The capacitive elements C3 and C4 are connected by a connection line 916 formed in the dielectric layer 903.

The capacitive elements C3 and C4 and the induction element L2 are connected by connecting the connection line 916 and the transmission line 917a constituting the inductance with a via conductor 923c penetrating the dielectric layer 903. The GND connection of the induction element L2 is made by connecting a via conductor 923e between the line 917b and the back conductor 40 constituting the induction element L2.
The flow of signals in the above impedance adjustment circuit C is as follows.

  The transmission signal output from the power amplifier circuit is transmitted in the order of the transmission filter input terminal 909, the transmission filter A, the transmission filter output terminal 910, the via conductor 923a, the capacitor electrode 914a, and the branching circuit connection line 918 and then separated. Input to the wave circuit 2. The transmission signal that has passed through the branching circuit 2 is transmitted in the order of the branching circuit connection line 919, the via conductor 923k, and the antenna terminal 922, and is output to the outside.

Next, the transmission path of the received signal will be described. First, when a signal including a plurality of transmission / reception systems is received at the antenna terminal 922, the signal is input to the branching circuit 2 through the via conductor 923 k and the branching circuit connection line 919.
The received signal that has passed only the desired transmission / reception system frequency signal in the demultiplexing circuit 2 is input to the impedance adjustment circuit C through the demultiplexing circuit connection line 918. In the impedance adjustment circuit C, the received signal is coupled from the capacitor electrode 914a to the capacitor electrode 914b via the capacitance C3, passes through the connection line 916, and is coupled from the capacitor electrode 915b to the capacitor electrode 915a via the capacitance C4. Then, it is connected to the reception filter input terminal 912 through the via conductor 923b. The connection line 916 is grounded through the via conductors 923c and the transmission lines 917a and 917b constituting the inductor element L2.

The reception signal is transmitted to the reception signal external output terminal 920 through the reception filter input terminal 912, the reception filter B, the reception filter output terminal 913, and the via conductor 923f.
As is clear from comparison between FIG. 11 and FIG. 13, it can be seen that the arrangement of the impedance adjustment circuit C in FIG. 11 can reduce the occupied volume to about 1/4. Further, unlike the conventional example using a strip line for the impedance adjustment circuit C, even if a pattern of another circuit is arranged around the impedance adjustment circuit C in the present invention, the influence on the reactance value and capacitance value to be formed is very small. Therefore, the patterns of other circuits such as a branching circuit and a directional coupler can be arranged in the multilayer substrate area below the transmission filter A and the reception filter B. As a result, the high-frequency module can be reduced in size.

  Although the embodiments of the present invention have been described above, the embodiments of the present invention are not limited to the above-described embodiments. For example, in the high-frequency module, the filter structure may be an FBAR (Film Bulk Acoustic Resonator) filter. In the present invention, an embodiment of a CDMA high frequency module is shown, but the present invention can also be applied to other communication methods. In addition, various modifications can be made within the scope of the present invention.

1 is a block configuration diagram of a CDMA dual-band high-frequency signal processing circuit. FIG. 4 is a plan view showing the entire high-frequency module 22 mounted on a multilayer substrate 23. FIG. FIG. It is the same perspective view. 2 is a circuit diagram showing an embodiment of an impedance adjustment circuit C. FIG. 6 is a Smith chart showing impedance when an impedance adjustment circuit C is viewed from an input point of a reception filter B. It is a plane perspective view which shows an internal line pattern at the time of mounting the impedance adjustment circuit C on a multilayer substrate. 3 is an exploded perspective view of a multilayer board on which an impedance adjustment circuit C is mounted. FIG. FIG. 6 is a circuit diagram showing another embodiment of the impedance adjustment circuit C. 6 is a Smith chart showing impedance when an impedance adjustment circuit C is viewed from an input point of a reception filter B. It is a plane perspective view which shows an internal line pattern at the time of mounting the impedance adjustment circuit C on a multilayer substrate. 3 is an exploded perspective view of a multilayer board on which an impedance adjustment circuit C is mounted. FIG. It is a top view of a dielectric material layer which shows the comparative example which used the stripline for the impedance adjustment circuit.

Explanation of symbols

1: antenna 2: demultiplexing circuits 3a, 4a, A: transmission filters 3b, 4b, B: reception filters 3c, 4c, C: impedance adjustment circuit 5, 6: directional coupler (coupler)
7, 8: Power amplifier circuit 9, 10: BPF
11: Detection circuit 12: GPS filter 13, 14: LNA
15, 16: SAW filter for reception 17: RFIC for transmission
18: RFIC for reception
19: Baseband IC
22: High frequency module 23: Multilayer substrate 24, 25: Power amplifying semiconductor element 26, 27: Output matching circuit 28: External terminals 601 to 606, 901 to 906: Dielectric layer

Claims (7)

Connected to the antenna terminal directly or through a demultiplexing circuit and connected to the transmission filter and reception filter for switching between the transmission system and the reception system, the impedance adjustment circuit inserted on the input side of the reception filter, and the transmission filter A high-frequency module in which a high-frequency power amplifier circuit that amplifies a transmission signal in a predetermined transmission passband is mounted on a multilayer substrate in which a plurality of dielectric layers are stacked,
The impedance adjustment circuit includes two grounding capacitive elements and an inductive element connected between the two grounding capacitive elements, and the grounding capacitive element and the inductive element are arranged in the multilayer substrate. A high-frequency module characterized by its interior. Connected to the antenna terminal directly or through a demultiplexing circuit and connected to the transmission filter and reception filter for switching between the transmission system and the reception system, the impedance adjustment circuit inserted on the input side of the reception filter, and the transmission filter A high-frequency module in which a high-frequency power amplifier circuit that amplifies a transmission signal in a predetermined transmission passband is mounted on a multilayer substrate in which a plurality of dielectric layers are stacked,
The impedance adjusting circuit includes two capacitive elements connected in series, and an inductive element having one terminal connected between the two capacitive elements and the other terminal grounded, and A high-frequency module, wherein the inductive element is housed in the multilayer substrate.   The high-frequency module according to claim 1 or 2, wherein the inductive element is constituted by a transmission line formed on one or a plurality of dielectric layers in a multilayer substrate.   The high-frequency module according to claim 1 or 2, wherein the capacitive element includes a pair of capacitor electrodes formed with a dielectric layer in a multilayer substrate interposed therebetween.   5. The high-frequency module according to claim 1, wherein the capacitive element and the inductive element are housed in a lower region of a multilayer substrate on which the transmission filter and the reception filter are installed.   The high frequency module according to claim 1, wherein the multilayer substrate is a multilayer ceramic substrate in which ceramic dielectric layers are laminated.   The communication apparatus carrying the high frequency module in any one of the said Claims 1-6.

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