JP2005268569A - Arrangement wiring method of poly-phase filter and mos integrated circuit wherein poly-phase filter is formed - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variation in characteristics of a poly-phase filter formed on an MOS integrated circuit substrate. <P>SOLUTION: Four resistances R1a to R1d in the first stage of the poly-phase filter 11 are arranged close in the vertical direction of the figure. Similarly, four capacitors C1a to C1d of the first stage are also arranged close in the vertical direction. Four resistances and four capacitors of a second stage and a third stage are also arranged close each other. Consequently, it is possible to reduce variation in resistance value of each stage and variation in capacitance, thus reducing variation in frequency characteristics of the filter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of arranging and wiring a polyphase filter formed on a MOS integrated circuit substrate and a MOS integrated circuit in which a polyphase filter is formed.

  In a mixer circuit of a radio receiver, a received signal and a local oscillation signal are mixed and converted into a predetermined intermediate frequency signal, amplified and detected, and demodulated into an original audio signal. When mixing the received signal and the local oscillation signal, if there is a so-called image signal whose frequency difference between the local oscillation signal and the local oscillation signal is close to the intermediate frequency, the image signal is also converted to the intermediate frequency signal, and noise with respect to the desired reception signal Become. Therefore, conventionally, an image signal is removed by an external band pass filter or the like.

On the other hand, it is possible to mount a wireless receiving circuit on a one-chip IC (integrated circuit), and at that time, it is required to form an external filter on the integrated circuit. Therefore, it is considered to use a polyphase filter as an image removal filter.
When the polyphase filter is used as an image removal filter, there is a problem in that the image signal cannot be completely removed if there is an amplitude error between the I channel signal and the Q channel signal output from the mixer circuit.

In order to solve such a problem, for example, Patent Document 1 describes that the amplitude error is corrected by setting the resistance and capacitance values of the polyphase filter in consideration of the amplitude error. Yes.
Japanese Patent Application Laid-Open No. H11-228707 describes that the deterioration of the image removal characteristics of the polyphase filter due to variations in the constants of circuit elements is improved by making the shift of the phase rotation angle of the polyphase fill reverse. .

When components are arranged on a semiconductor integrated circuit substrate, the components are generally arranged so that the wiring length of each component is shortened.
FIG. 3 is a diagram showing an example of the arrangement of the polyphase filter having the circuit configuration shown in FIG. 2 on the integrated circuit board.

  In FIG. 3, the uppermost square block R1a in the left column corresponds to the resistor R1a in FIG. 2, and the second block C1a from the top corresponds to the capacitor C1a in FIG. Similarly, the third block R1b from the top is the resistor R1b in FIG. 2, the fourth block C1b is the capacitor C1b in FIG. 2, the fifth block R1c is the resistor R1c in FIG. The block C1c corresponds to the capacitor C1c in FIG. 2, the seventh block R1d corresponds to the resistor R1d in FIG. 2, and the eighth block C1d corresponds to the capacitor C1d in FIG. The same applies to the blocks in the second and third columns in FIG.

That is, the capacitor C1a is disposed near the resistor R1a, the capacitor C1b is disposed near the resistor R1b, the capacitor C1c is disposed near the resistor R1c, and the capacitor C1d is disposed near the resistor R1d.
Japanese Patent Laid-Open No. 2001-45080 JP 2003-198329 A

When the resistors and capacitors are arranged as shown in FIG. 3, the resistance value and the capacitance vary due to variations in the manufacturing conditions of the MOS process even on the same substrate. Therefore, the frequency characteristics of the polyphase filter differ from the design values due to these variations. End up.
An object of the present invention is to reduce variation in characteristics of a polyphase filter formed on a MOS integrated circuit substrate.

  A polyphase filter arrangement and wiring method according to the present invention is a polyphase filter arrangement and wiring method used in a mixer circuit that generates a predetermined medium frequency signal by mixing a received signal and a local oscillation signal, and includes a MOS integrated circuit board. A plurality of resistors of at least one stage of the polyphase filter are arranged in the vicinity, a plurality of capacitors connected to the plurality of resistors are arranged in the vicinity, and the plurality of resistors and the capacitors are connected by a conductor pattern.

  According to the present invention, by disposing a plurality of resistors and capacitors close to each other, variations in resistance value and capacitance can be reduced, and variations in frequency characteristics of the polyphase filter can be reduced. Thereby, the removal performance of the image signal etc. output from the mixer circuit can be enhanced.

  According to another aspect of the present invention, in the above invention, the polyphase filter includes a first resistor to which a signal having the same phase as the intermediate frequency signal mixed by the mixer is input, and a signal having a first phase difference. A second resistor to be input; a third resistor to which a signal having a second phase difference is input; a fourth resistor to which a signal having a third phase difference is input; and the first resistor. A first capacitor connected between the input side of the second resistor and the output side of the second resistor, and a second capacitor connected between the input side of the second resistor and the output side of the third resistor. A capacitor, a third capacitor connected between an input side of the third resistor and an output side of the fourth resistor, an input side of the fourth resistor, and an output of the first resistor And a fourth capacitor connected between the first and fourth resistors, the first to fourth resistors having the same value. It was disposed in the vicinity, and from the first to the same capacity of the fourth capacitor is arranged in the vicinity thereof.

  With this configuration, variations in the resistance values of the first to fourth resistors and the capacitances of the first to fourth capacitors are reduced, so that variations in the frequency characteristics of the filter can be reduced.

  According to the present invention, variation in the frequency characteristics of the filter can be reduced by reducing variation in resistance value and capacitance in the polyphase filter.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating an arrangement of polyphase filters according to the embodiment.
The polyphase filter of the embodiment is mounted on an integrated circuit substrate for FM and AM radio receivers manufactured by a CMOS process capable of forming a p-channel MOS transistor and an n-channel MOS transistor.

Here, the circuit configuration of the polyphase filter 11 will be described with reference to FIG. The polyphase filter 11 according to the embodiment is a third-order polyphase filter in which a circuit composed of a resistor and a capacitor is connected in three stages in cascade as shown in FIG.
The four input terminals on the left side of the polyphase filter 11 have a signal in phase with an intermediate frequency signal output from a mixer circuit (not shown), and a first phase difference, for example, a 90 ° phase difference, from the intermediate frequency signal. And a signal having a second phase difference, for example, a phase difference of 180 °, and a signal having a third phase difference, for example, a phase difference of 270 °, are input.

The input side of the first resistor R1a (first resistor) in the first column (hereinafter referred to as the first stage) from the left in FIG. 2, and the output side of the second resistor R1b (second resistor) from the top in FIG. Is connected with a capacitor C1a (first capacitor).
A capacitor C1b (second capacitor) is connected between the input side of the second resistor R1b and the output side of the third resistor R1c (third resistor).

A capacitor C1c (third capacitor) is connected between the input side of the third resistor R1c and the output side of the fourth resistor R1d (fourth resistor).
Further, a capacitor C1d (fourth capacitor) is connected between the input side of the fourth resistor R1d and the output side of the first resistor R1a. The second and third stage filters have the same configuration.

Note that the first-stage resistance value and capacitance have a relationship of R1a = R1b = R1c = R1d and C1a = C1b = C1c = C1d. The same applies to R2a to R2d, R3a to R3d, C2a to C2d, and C3a to C3d.
Next, a method for arranging resistors and capacitors when the polyphase filter 11 is formed on a MOS integrated circuit substrate will be described with reference to FIG.

  In FIG. 1, the four resistors R1a to R1d constituting the first-stage filter (first column from the left) are arranged close to each other in the vertical direction of FIG. Similarly, the four capacitors C1a to C1d in the first stage are also arranged close to each other in the vertical direction. This is because when a resistor or a capacitor is formed, in the oxide film generation, ion implantation, etching, etc., if the parts are of the same type, the closer they are arranged, the variation in film thickness, impurity concentration, etching, etc. This is because variations in values and capacities are reduced.

  Each of the resistors R1a to R1d is not shown, but a rod-shaped resistor having a predetermined resistance value is formed by etching or the like, and a desired resistance value is realized by adjusting the cross-sectional area and length of the resistor. Yes. Regarding the capacitors C1a to C1d, a plurality of small capacitors are formed and connected in parallel to achieve a desired capacitance.

The four resistors R2a to R2d and capacitors C2a to C2d constituting the second stage filter, and the four resistors R3a to R3d and capacitors C3a to C3d constituting the third stage filter are also brought close to each other in the vertical direction. Are arranged.
The first resistor arrangement portion (the portion where the resistors R1a to R1d are arranged hereinafter is referred to as a resistor arrangement portion) in FIG. Hereinafter, the input side of the capacitor C1 at the top of the portion where the capacitors C1a to C1d are arranged is referred to as a capacitor arrangement portion (hereinafter, the input side indicates the left side when viewed from the front of FIG. 1). Connected by pattern. The output side of the capacitor C1a (hereinafter, the output side indicates the right side in FIG. 1) is connected to the output side of the second resistor R1b from the top of the resistor portion by a wiring pattern.

The output side of the first-stage resistor R1a in the first stage is connected to the input side of the first-stage resistor R2a in the second stage by a wiring pattern.
The input side of the second resistor R1b from the top of the first-stage resistor placement section and the input side of the second capacitor C1b from the top of the capacitor placement section are connected by a wiring pattern, and the output side of the second capacitor C1b The output side of the third resistor R1c from the top of the resistor placement portion is connected by a wiring pattern. The output side of the second resistor R1b in the first stage is connected to the input side of the second resistor R2b from the top in the second stage by a wiring pattern.

  Similarly, the input side of the third resistor R1c from the top of the first resistor arrangement portion and the input side of the third capacitor C1c from the top of the capacitor arrangement portion are connected by a wiring pattern, and the output of the third capacitor C1c Side and the output side of the fourth resistor R1d are connected by a wiring pattern. The output side of the third resistor 2Rc in the first stage is connected to the input side of the third resistor R2c from the top in the second stage by a wiring pattern.

  Furthermore, the input side of the fourth resistor R1d from the top of the first-stage resistor placement portion and the input side of the fourth capacitor C1d from the top of the capacitor placement portion are connected by a wiring pattern, and the output side of the fourth capacitor C1d And the output side of the uppermost resistor R1a are connected by a wiring pattern. The output side of the fourth resistor R1d at the first stage is connected to the input side of the fourth resistor R2d at the second stage.

The second and third stage resistors R2a to R2d, R3a to R3d and capacitors C2a to C2a to C2d, C3a to C3d are similarly wired.
In FIG. 1, the wiring of the second and third stage resistors and capacitors is omitted for the sake of simplicity.

  As described above, the resistors R1a to R1d, R2a to R2d, and R3a to R3d of each stage of the polyphase filter 11 formed on the MOS integrated circuit substrate are arranged close to each other, and the capacitors connected to these resistors By disposing C1a to C1d, C2a to C2d, and C3a to C3d close to each other, variation in resistance value and capacitance is reduced, and variation in frequency characteristics of the polyphase filter with respect to a design value is reduced.

  As a result, the error with respect to the design value of the stop frequency of the polyphase filter can be reduced, so that the removal performance of the image signal output from the mixer circuit can be enhanced. Furthermore, when the intermediate frequency is set to a low frequency, the removal of the image signal becomes an important problem. However, according to the polyphase filter of the present embodiment, the image signal is accurately removed by increasing the frequency accuracy of the filter. can do.

Note that the wiring length between the resistor and the capacitor becomes longer than that of the arrangement method of FIG. 3 by arranging the resistors and capacitors at each stage close to each other. However, the influence of the wiring length on the frequency characteristics of the filter. There are few.
The present invention is not limited to the embodiment described above, and may be configured as follows.
(1) The polyphase filter is not limited to the circuit as shown in FIG. The polyphase filter is not limited to a third-order filter, and may have a primary, secondary, or fourth-order configuration. Further, the filter is not limited to a filter that removes a signal in a specific band, and may be a band-pass filter.
(2) The arrangement of resistors and capacitors in each stage is not limited to the arrangement in the vertical direction as shown in FIG. 1, and the resistors and capacitors in each stage, or part or all of the resistors and capacitors are arranged in the horizontal direction and oblique directions. You may arrange | position so that it may approach.
(3) The resistance value and capacity of the polyphase filter are not limited to those of the embodiment, and can be appropriately changed according to the required filter characteristics.
(4) The present invention can be applied not only to AM and FM radio receivers but also to circuits of other wireless communication devices and other devices.

It is a figure which shows arrangement | positioning of the polyphase filter of embodiment of this invention. It is a circuit diagram of a polyphase filter. It is a figure which shows arrangement | positioning of the conventional polyphase filter.

Explanation of symbols

R1a to R1d First stage resistor R2a to R2d Second stage resistor R3a to R3d Third stage resistor C1a to C1d First stage capacitor C2a to C2d Second stage capacitor C3a to C3d Third stage capacitor 11 Poly Phase filter

Claims (4)

A polyphase filter placement and wiring method used in a mixer circuit that generates a predetermined medium frequency signal by mixing a reception signal and a local oscillation signal,
A plurality of resistors of at least one stage of the polyphase filter are arranged in the vicinity on the MOS integrated circuit substrate,
A plurality of capacitors connected to the plurality of resistors are arranged in the vicinity,
A polyphase filter placement and wiring method in which the plurality of resistors and capacitors are connected by a conductor pattern.   The polyphase filter includes a first resistor to which a signal having the same phase as the intermediate frequency signal mixed by the mixer is input, a second resistor to which a signal having a first phase difference is input, and a second resistor. A third resistor to which a signal having a phase difference is input, a fourth resistor to which a signal having a third phase difference is input, an input side of the first resistor, and an output side of the second resistor A first capacitor connected between the second capacitor, a second capacitor connected between an input side of the second resistor and an output side of the third resistor, and an input side of the third resistor And a third capacitor connected between the output side of the fourth resistor and a fourth capacitor connected between the input side of the fourth resistor and the output side of the first resistor And the first to fourth resistors have the same value and are arranged in the vicinity of the first to fourth resistors. 4 of the capacitance of the capacitor in the same polyphase placement and routing method of the filter of claim 1, wherein arranged in the vicinity of their capacitors. A polyphase filter used in a mixer circuit that generates a predetermined medium frequency signal by mixing a reception signal and a local oscillation signal,
A plurality of resistors of at least one stage of the polyphase filter are arranged in the vicinity,
A plurality of capacitors connected to the plurality of resistors are arranged in the vicinity,
A MOS integrated circuit in which a polyphase filter is formed by connecting the plurality of resistors and capacitors by a conductor pattern. The polyphase filter includes a first resistor to which a signal having the same phase as the intermediate frequency signal mixed by the mixer is input, a second resistor to which a signal having a first phase difference is input, and a second resistor. A third resistor to which a signal having a phase difference is input, a fourth resistor to which a signal having a third phase difference is input, an input side of the first resistor, and an output side of the second resistor A first capacitor connected between the second capacitor, a second capacitor connected between an input side of the second resistor and an output side of the third resistor, and an input side of the third resistor And a third capacitor connected between the output side of the fourth resistor and a fourth capacitor connected between the input side of the fourth resistor and the output side of the first resistor And the first to fourth resistors have the same value and are arranged in the vicinity of the first to fourth resistors. 4 of the capacitance of the capacitor in the same MOS integrated circuit forming a polyphase filter according to claim 3, wherein arranged in the vicinity of their capacitors.

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