JP2005268534A5 - - Google Patents

Claims (6)

A chip on the chip is formed on the main surface, and the chip wiring is configured to be electrically connected to the external connection wiring,
The semiconductor chip is characterized in that the on-chip wiring is formed so as to extend from a first end portion side of the main surface to a second end portion side. A first semiconductor chip in which a first on-chip wiring is formed on a first main surface;
A second semiconductor chip stacked on the first main surface and having a second on-chip wiring formed on the second main surface;
A stacked semiconductor device having a plurality of external connection wirings electrically connected to the first on-chip wiring or the second on-chip wiring,
The second semiconductor chip is stacked while being shifted so that at least a part of the wiring on the first chip is exposed,
The second on-chip wiring is formed so as to extend from the first end side to the second end side of the second main surface, and the first on-chip wiring or the external A stacked semiconductor device having a structure electrically connected to a connection wiring.   3. The stacked semiconductor device according to claim 2, wherein the first on-chip wiring is electrically connected to the external connection wiring through the second on-chip wiring.   3. The stacked semiconductor device according to claim 2, wherein the second on-chip wiring is configured to be electrically connected to the external connection wiring through the first on-chip wiring.   5. The stacked semiconductor device according to claim 2, wherein the external connection wiring includes a lead frame.   5. The stacked semiconductor device according to claim 2, wherein the external connection wiring is wiring formed on a tape carrier.