JP2005267294A - Network interrupt control method, information processing apparatus and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a reduction in the performance of an information processing apparatus, an image forming apparatus or the like by preventing an increase in the processing load on a CPU due to an interrupt at data reception via a network. <P>SOLUTION: When some of packet data arriving at a network 101 are received, an ASIC 103 issues a batch interrupt to the CPU 102, which reduces the bus occupation rate of interrupts to reduce the CPU load. The interrupt is generated according to the number of received packets, the lapse of a predetermined time or the combination of both. Once the interrupt is generated, interrupt issuance is suspended until software finishes processing the received packets, and after the finish of packet processing by the software is notified, another interrupt can be generated. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a network interrupt control method, an information processing apparatus, and an image forming apparatus, and more particularly, when an information processing apparatus or image forming apparatus connected to a network receives packet data transmitted via the network. The present invention relates to a network interrupt control method for controlling an interrupt to a CPU, an information processing apparatus, and an image forming apparatus.

  In general, when an information processing apparatus, an image forming apparatus, or the like connected to a network receives packet data (which may be frame data but will be described as packet data below) transmitted via the network, Each time packet data is received, the CPU is interrupted to process the received packet data.

  FIG. 8 is a diagram for explaining packet data reception and processing operations according to the prior art. In FIG. 8, 101 is a network, 102 is a CPU, 103 is an ASIC, 104 is a memory, 81 is an interface, and 82 is a controller.

  As shown in FIG. 8, an ASIC 103 having an interface 81 and a controller 82 for connecting the network 101 is provided in a network connection unit such as an information processing apparatus or an image forming apparatus. The memory 104 connected to the ASIC 103 has an area for storing packet data received via the network, and is well known in the past for controlling the packet data. A plurality of descriptors connected in a ring shape are preset by the CPU 102.

  In FIG. 8, when one packet data is received from the network 101, the ASIC 103 stores the received packet data in the memory 104 and describes the packet data in one of the empty descriptors. Stores the information. The descriptor includes a next descriptor pointer (ND) indicating the location of the next descriptor, a start address storing the received packet data, a VALID indicating whether the descriptor is valid or invalid, and a STATUS indicating the processing status of the received packet data. It is configured.

  Further, the ASIC 103 stores the received packet data in the memory 104, and when the necessary data is set in the descriptor corresponding to the packet data, causes the CPU 102 to generate an interrupt. The CPU 102 executes interrupt processing for this interrupt and also executes processing for packet data stored in the memory 104.

  As described above, in the reception of packet data from the network according to the conventional technique, when one packet data is received, one interrupt is generated to process the packet (when the processing speed of the system is sufficiently in time with respect to the speed of the network) Then, the received packet is processed. As a result, an interrupt processing instruction generated every time one packet is received flows to the system bus, which increases the processing load on the CPU and decreases the performance of the system.

As a conventional technique that can prevent an increase in CPU processing load and a decrease in performance as a system due to such interrupt processing, for example, a technique described in Patent Document 1 is known. In this prior art, a packet arrival interrupt is adjusted so that the CPU is not burdened with an excessive interrupt while receiving a burst of network data, and the first packet of a new data burst is adjusted. Alternatively, an interrupt is immediately generated to the CPU by the first packet of the short message so as to avoid an unnecessary waiting time for the CPU response.
Japanese Patent Laid-Open No. 9-223091

  In the prior art described with reference to FIG. 8, an interrupt occurs every time one packet is received from the network, and the actual packet processing time for the software to process data on the memory occurs. As a result, the generated interrupt processing instruction flows to the system bus, causing an increase in the processing load on the CPU and degrading the performance of the system.

  The prior art described in Patent Document 1 generates an interrupt immediately to the CPU by a first packet of a new data burst or a first packet of a short message, and generates subsequent interrupts. Although it can be adjusted based on the number of received packets to avoid unnecessary waiting time for the CPU response, it is considered that the arrival of packet data is not bursty but distributed. Have the problem of not.

  The object of the present invention is to solve the above-mentioned problems of the prior art, and suppress the occurrence of interrupts to the CPU until a certain time elapses after receiving the first packet data or until a certain number of packets are received. Accordingly, an object of the present invention is to provide a network interrupt control method, an information processing apparatus, and an image forming apparatus that can prevent an increase in processing load due to an interrupt to a CPU and prevent a decrease in performance as a system.

  In order to achieve the above object, a first means of the present invention is a network interrupt control method for receiving data transmitted via a network in an information processing apparatus or an image forming apparatus having an ASIC for connecting to a network. And when the ASIC receives a predetermined number of pieces of packet data, the CPU connected to the ASIC generates an interrupt to process the received data. To do.

  According to a second means of the present invention, there is provided a network interrupt control method for receiving data transmitted via a network in an information processing apparatus or an image forming apparatus having an ASIC for connecting to a network. In addition, it is characterized in that an interrupt is generated for the CPU connected to the ASIC at predetermined time intervals to process the data received within the predetermined time.

  The third means of the present invention is characterized in that, in the second means, the measurement of the predetermined time is started when the first packet data is received.

  According to a fourth means of the present invention, there is provided a network interrupt control method for receiving data transmitted via a network in an information processing apparatus or image forming apparatus having an ASIC for connecting to a network. When a predetermined number of pieces of packet data are received, and at predetermined intervals, the received data is processed by generating an interrupt to the CPU connected to the own ASIC. It is characterized by making it.

  According to a fifth means of the present invention, in the fourth means, the generation of an interrupt when receiving the predetermined number of packet data, the generation of an interrupt every predetermined time interval, When one occurs first, the generation of the other interrupt is stopped.

  According to a sixth means of the present invention, there is provided a network interrupt control method at the time of receiving data transmitted via a network in an information processing apparatus or image forming apparatus having an ASIC for connecting to a network. The received packet data is stored in a memory connected to the own ASIC, and when the capacity of the stored packet data reaches a predetermined capacity, an interrupt is generated for the CPU connected to the own ASIC and received. It is characterized in that the processed data is processed.

  According to a seventh aspect of the present invention, in the information processing apparatus or image forming apparatus having an ASIC for connecting to a network, the ASIC counts a number of packet data received, a predetermined number of And means for causing the CPU connected to the ASIC to process the received data when the counter counts the reception of a plurality of packet data.

  According to an eighth aspect of the present invention, there is provided an information processing apparatus or image forming apparatus having an ASIC for connecting to a network, wherein the ASIC counts a predetermined time, and a predetermined time determined by the timing means. And means for generating an interrupt to the CPU connected to the ASIC and processing the received data within a predetermined time.

  According to a ninth means of the present invention, in the eighth means, the time measuring means starts time counting when the first packet data is received.

  According to a tenth means of the present invention, in the information processing apparatus or image forming apparatus having an ASIC that connects to a network, the ASIC counts a number of received packet data and a predetermined time. When the counter counts the reception of a predetermined number of pieces of packet data, or when the time measuring means measures a predetermined time, the CPU connected to the own ASIC And means for processing the data received within a predetermined time by generating an interrupt.

  The eleventh means of the present invention is characterized in that, in the tenth means, an interrupt is generated when the predetermined number of pieces of packet data are received, and an interrupt is generated at predetermined intervals. It is characterized by having means for stopping the generation of the other interrupt when one occurs first.

  According to a twelfth aspect of the present invention, in the information processing apparatus or image forming apparatus having an ASIC for connecting to a network, the ASIC stores received packet data in a memory connected to the ASIC. Determining means for determining that the capacity of the stored packet data has reached a predetermined capacity; and when the determining means determines that the capacity of the packet data has reached a predetermined capacity, And a means for causing the connected CPU to generate an interrupt and to process the received data.

  According to the present invention, the occurrence of an interrupt to the CPU is suppressed until a certain time elapses after the first packet data is received or until a certain number of packets are received. It is possible to prevent an increase in processing load and to prevent a decrease in performance as a system such as an information processing apparatus or an image forming apparatus.

  Embodiments of a network interrupt control method, an information processing apparatus, and an image forming apparatus according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of an embodiment of an image forming apparatus to which the present invention is applied, and FIG. 2 is a block diagram showing another configuration example of the embodiment of the image forming apparatus to which the present invention is applied. First, the configuration of the image forming apparatus to which the present invention is applied will be described. Note that, as an embodiment of the present invention, an image forming apparatus to which the present invention is applied will be described. However, the present invention is also applied to an information processing apparatus in which a general workstation and a PC are provided with a communication function. be able to. 1 and 2, reference numeral 100 denotes an image forming apparatus, 107 denotes an ASIC, 105 denotes a MAC, and 106 denotes an image forming unit. Other reference numerals are the same as those in FIG.

  An image forming apparatus 100 illustrated in FIG. 1 is configured by connecting an ASIC 103 connected to a network 101 to a CPU 102, a memory 104, and an image forming unit 104. An interface (not shown) that controls the network 101 is directly connected to the ASIC 103, and reception of packet data and the like from the network is processed by the MAC 105 of the network control unit of the ASIC 103.

  An image forming apparatus 100 shown in FIG. 2 is an example in the case of using an I / O ASIC 107 for a network or the like. An ASIC 107 having a MAC 105 is connected to the ASIC 103 shown in FIG. 1 via a general-purpose bus such as a PCI bus. Reception of packet data or the like from the network is processed by the MAC 105 of the network control unit of the ASIC 107, and processing of the received packet data is performed by the ASIC 103 through the PCI bus.

  In the embodiment of the present invention, when several pieces of packet data arriving on the network are received, an interrupt is collectively issued, the bus occupation rate due to the interrupt is reduced to reduce the CPU load. Or, an interrupt based on time or an interrupt that uses both is performed. Then, in the embodiment of the present invention, when one interruption occurs, the interruption of the packet received by the software is stopped until the processing of the packet received by the software is notified. An interrupt can be generated again. Further, the threshold of the number of interrupts when an interrupt is generated depending on the number of received packets and the time count when an interrupt is generated according to time can be changed during operation. As described above, the basic idea of the present invention is to allow the software to determine the start of an interrupt operation because an interrupt cannot be processed even if an interrupt is generated before the software process ends.

  FIG. 3 is a diagram for explaining an example in which a packet is processed by interruption according to time in an embodiment of the present invention. FIG. 3 shows the descriptors developed on the memory as in the case described with reference to FIG. 8, and the number of descriptors can be arbitrarily determined according to the system specifications. In FIG. 3, the dark color is an empty descriptor, and the outline has an unprocessed packet data.

  The embodiment of the present invention is provided with a timer (time is measured by a subtraction counter or an addition counter) that measures the time until the interruption set in advance in the ASIC for the case of performing interruption processing by time. When the first packet data is received from the network, a timer is started to start timing, and after a certain period of time, an interrupt is generated for processing the packet data received during that time. For example, if the time until the interruption is set to t seconds, no interruption occurs for t seconds after the reception of the first packet data, and the interruption occurs after t seconds. In the example shown in FIG. 3, it is assumed that three packet data have arrived during t seconds. Due to the interrupt generated after t seconds, the three packet data are processed by software according to the information of the three packet data stored in the descriptor. When the next packet data arrives during the processing of these three packet data, the packet data is stored in the memory, and the corresponding descriptor is generated and connected to the descriptor chain. The received packet data is also processed without generating an interrupt.

  According to the above-described example, it is only necessary to generate an interrupt once every predetermined time by a timer interrupt, and the number of interrupts can be reduced.

  FIG. 4 is a diagram illustrating an example in which a packet is processed by an interruption based on the number of received packets according to an embodiment of the present invention. FIG. 4 shows the descriptors developed on the memory as in the case described with reference to FIG. 8, and the number of descriptors can be arbitrarily determined according to the system specifications. In FIG. 3 as well, a dark color is an empty descriptor, and an outline is a descriptor with unprocessed packet data.

  The embodiment of the present invention includes a counter (a subtraction counter or an addition counter) that counts the number of received packets set in advance in the ASIC for the case of performing an interrupt process based on the number of packets. When the first packet data is received from the network, a counter for counting the number of received packets is activated. When a certain number of packet data is received, an interrupt is generated for processing the received packet data. . For example, if the reception number of packet data is set to 5, no interruption occurs between the reception of the first packet data and the reception of a total of 5 packet data, and 5 packet data An interrupt is generated after is received. Due to the generated interrupt, the five packet data are processed by software according to the information of the five packet data stored in the descriptor. When the next packet data arrives during the processing of these five packet data, the packet data is stored in the memory, the corresponding descriptor is generated, and connected to the descriptor chain. The received packet data is also processed without generating an interrupt.

  According to the above-described example, an interrupt is generated when a predetermined number of packet data is received. Therefore, it is only necessary to generate an interrupt once when a set number of packet data is received, thereby reducing the number of interrupts. be able to.

  In the above description, the interrupt by the timer and the interrupt by the number of packets have been described. However, these can be used alone, but in practice, two interrupts of the timer interrupt and the interrupt by the number of packets may be used in combination. desirable. The reason is that the descriptor overflows while waiting for the timer interrupt time, or the packet data is not transferred indefinitely in the memory if it is less than the number of packets set for the interrupt due to the number of packets. This is because there may be a case where unprocessed packet data remains.

  FIG. 5 is a diagram for explaining the operation in the case where the timer interrupt and the interrupt based on the number of packets are used in combination, and the timer interrupt occurs first. In FIG. 5, it is assumed that time has passed from the top to the bottom of the figure. Further, it is assumed that the packet count and the time measurement by the timer are started at an upper position (not shown) in FIG.

  In FIG. 5, when the timer counts a predetermined time and stops the timer count at time t1 in a state where the packet number counter does not reach the predetermined number of received packets, a timer interrupt is issued to the CPU. The received packet data is processed. By stopping the timer count, the counter for counting received packets is also stopped at the same time. Then, when the processing of the packet data in the CPU ends at time t2, the cause of the timer interruption is cleared. At the same time, the timer is brought into a state where it can start counting again. The fact that the timer interrupt is cleared means that the processing of the packet data has ended, and at the same time, the counter for the interrupt based on the number of packets is also cleared. As described above, according to the embodiment of the present invention, the timer interrupt counter is cleared, and at the same time, the interrupt count according to the number of packets is cleared so that the count can be started again. The counter as a timer and the counter for the number of packets can be configured by preparing a register in the memory.

  FIG. 6 is a diagram for explaining the operation when an interrupt based on the number of packets first occurs when two interrupts of a timer interrupt and an interrupt based on the number of packets are used in combination. In FIG. 6, it is assumed that time has passed from the top to the bottom of the figure. Further, it is assumed that the packet count and the time measurement by the timer are started at an upper position (not shown) in FIG.

  In FIG. 6, when the packet counter counter counts a predetermined received packet and stops counting at time t1 in a state where the timer counter does not finish measuring the predetermined time, an interrupt based on the number of packets is issued to the CPU. The CPU starts processing the packet data received. By stopping the counting of the number of packets, the timer counter is also stopped at the same time. When the packet data processing at the CPU ends at time t2, the cause of the interruption due to the number of packets is cleared. At the same time, the timer is brought into a state where it can start counting again. The fact that the interrupt due to the number of packets is cleared means that the processing of the packet data has ended, and at the same time, the counter for the interrupt due to the timer is also cleared. As described above, the embodiment of the present invention clears the interrupt counter based on the number of packets and simultaneously clears the interrupt count based on the timer so that the counting can be started again. The counter as a timer and the counter for the number of packets can be configured by preparing a register in the memory.

  In the above description, when the timer interrupt and the frame interrupt occur simultaneously, the frame interrupt is given priority in the embodiment of the present invention. In addition, when the timer interrupt and the frame interrupt are used, the process of generating one interrupt and not generating the other interrupt is performed by hardware, but can also be performed by software. The interrupt counters are operated only after the software sends a signal indicating that the processing has been completed.

  In the above-described embodiment of the present invention, the number of received packets, the interruption by time, or the combination of both is described. However, the present invention is a modification in the case of generating an interrupt by the number of received packets. As an example, a threshold may be set for the memory capacity occupied by the packet data of the memory that stores the received packet data, and an interrupt may be generated by monitoring the threshold of the memory capacity.

  FIG. 7 is a timing chart for explaining processing of received packet data in the prior art and the embodiment of the present invention. Next, this will be described.

  In the case of the prior art, as shown in FIG. 7A, an interrupt is generated every time one packet is received, and an actual packet processing time is required for the software to process data on the memory. For this reason, the frequency of occurrence of interrupts increases, the bus occupancy rate of interrupts increases, and the performance of the system decreases.

  The example shown in FIG. 7B is according to the embodiment of the present invention, and the number of received packets (when the number of received packets is set to 3) or interruption by time (three packets within the set time). When an interrupt occurs, three packet data are sequentially processed with only one interrupt. For this reason, in this example, the three interrupt processing times can be reduced to one.

  The example shown in FIG. 7C is an example in which an interrupt is generated by the threshold based on the memory capacity described as a modification in the case of generating an interrupt depending on the number of packets received as described above. In this example, an interrupt is generated when the threshold is exceeded in comparison with the memory capacity due to the number of bytes of packets from the network. In this example, for example, if 3/4 of the memory capacity is just packets 1 to 3, an interrupt is generated when the threshold of that capacity is exceeded. This method is effective when processing on the software side that processes data on the memory is considered in terms of the number of bytes.

  In the example shown in FIG. 7D, when only the interruption based on the number of packets is used, in order to prevent packet data processing from proceeding without waiting until the number of received packets does not reach the set value, This is an example in the case of using an interrupt due to. For example, even if only two packets have arrived, packet data can be processed by generating an interrupt by time after t seconds by using an interrupt by time. The set value of this time is arbitrary and can be set by the operation clock.

  The above-described embodiment of the present invention is based on the premise that the arrival frequency of packet data coming from the network is such that it can be sufficiently processed on the system side (information processing apparatus and image forming apparatus configured with an ASIC). However, if the data packet arrives at such a frequency that the processing on the system side cannot catch up, in the embodiment of the present invention, the pause packet is transmitted to the network at regular intervals, and the packet data coming from the network It can also be made to restrict.

  According to the embodiment of the present invention described above, an interrupt can be generated according to the number of received packets or a set value of a timer, and it is not necessary to generate an interrupt every time a packet is received. System performance can be improved.

1 is a block diagram illustrating a configuration example of an embodiment of an image forming apparatus to which the present invention is applied. It is a block diagram which shows the other structural example of one Embodiment of the image forming apparatus with which this invention is applied. It is a figure explaining the example which processes a packet by interruption by time in one Embodiment of this invention. It is a figure explaining the example which processes a packet by the interruption by the number of received packets in one Embodiment of this invention. It is a figure explaining the operation | movement when a timer interruption generate | occur | produces first, when using two interruptions of a timer interruption and interruption by the number of packets together. It is a figure explaining the operation | movement when the interruption by a packet number generate | occur | produces first in the case of using two interruptions of a timer interruption and the interruption by a packet number together. It is a timing chart explaining processing of received packet data in the prior art and the embodiment of the present invention, It is a figure explaining operation of packet data reception by the prior art, and its processing.

Explanation of symbols

100 Image forming apparatus 101 Network 102 CPU
103, 107 ASIC
104 memory 105 MAC
106 Image forming unit 81 Interface 82 Controller

Claims (18)

  In a network interrupt control method for receiving data transmitted via a network in an information processing apparatus or an image forming apparatus having an ASIC for connecting to a network, the ASIC includes a predetermined number of packet data. A network interrupt control method characterized in that when a reception is performed, an interrupt is generated for a CPU connected to the own ASIC to process the received data.   In the network interrupt control method for receiving data transmitted via the network in an information processing apparatus or image forming apparatus having an ASIC for connecting to the network, the ASIC is automatically updated at predetermined time intervals. What is claimed is: 1. A network interrupt control method, comprising: causing a CPU connected to an ASIC to generate an interrupt and processing received data within a predetermined time.   3. The network interrupt control method according to claim 2, wherein the counting of the predetermined time is started when the first packet data is received.   In a network interrupt control method for receiving data transmitted via a network in an information processing apparatus or an image forming apparatus having an ASIC for connecting to a network, the ASIC includes a predetermined number of packet data. A network interrupt control method characterized by causing a CPU connected to its own ASIC to generate an interrupt and processing the received data at the time of reception and at predetermined time intervals.   When one of the occurrence of an interrupt when receiving a predetermined number of packet data and the occurrence of an interrupt every predetermined time interval occurs first, the generation of the other interrupt is stopped 5. The network interrupt control method according to claim 4, wherein:   In the network interrupt control method when receiving data transmitted via the network in an information processing apparatus or image forming apparatus having an ASIC that connects to the network, the ASIC connects the received packet data to its own ASIC. When the capacity of the stored packet data reaches a predetermined capacity, the CPU connected to the ASIC is interrupted to process the received data. Network interrupt control method.   In an information processing apparatus having an ASIC that connects to a network, the ASIC includes a counter that counts the number of received packet data and a counter that counts reception of a predetermined number of packet data. An information processing apparatus comprising: means for generating an interrupt to a CPU connected to the own ASIC and processing the received data.   In an information processing apparatus having an ASIC for connecting to a network, the ASIC includes a time measuring means for measuring a predetermined time, and a CPU connected to the own ASIC when the time measuring means measures a predetermined time. An information processing apparatus comprising: means for generating an interrupt to process data received within a predetermined time.   9. The information processing apparatus according to claim 8, wherein the time measuring unit starts time counting when the first packet data is received.   In an information processing apparatus having an ASIC that connects to a network, the ASIC receives a counter that counts the number of received packet data, a time measuring unit that measures a predetermined time, and reception of a predetermined number of packet data. When the counter counts or when the time measuring means measures a predetermined time, processing of data received within a predetermined time by generating an interrupt to the CPU connected to the ASIC And an information processing apparatus.   When one of the generation of an interrupt when receiving a predetermined number of packet data and the generation of an interrupt at a predetermined fixed time occurs first, the generation of the other interrupt is stopped. The information processing apparatus according to claim 10, further comprising: means.   In an information processing apparatus having an ASIC for connecting to a network, the ASIC stores means for storing received packet data in a memory connected to its own ASIC, and the capacity of the stored packet data becomes a predetermined capacity. And a data received by generating an interrupt to the CPU connected to the ASIC when the determination means determines that the capacity of the packet data has reached a predetermined capacity. An information processing apparatus comprising: means for performing the process.   In an image forming apparatus having an ASIC for connecting to a network, the ASIC includes a counter that counts the number of received packet data and a counter that counts reception of a predetermined number of packet data. An image forming apparatus comprising: means for generating an interrupt to a CPU connected to the own ASIC and processing the received data.   In an image forming apparatus having an ASIC for connecting to a network, the ASIC includes a time measuring means for measuring a predetermined time, and a CPU connected to the own ASIC when the time measuring means measures a predetermined time. An image forming apparatus comprising: means for generating an interrupt to process received data within a predetermined time.   9. The image forming apparatus according to claim 8, wherein the time measuring unit starts time counting when the first packet data is received.   In an image forming apparatus having an ASIC that connects to a network, the ASIC receives a counter that counts the number of received packet data, a time measuring unit that measures a predetermined time, and reception of a predetermined number of packet data. When the counter counts or when the time measuring means measures a predetermined time, processing of data received within a predetermined time by generating an interrupt to the CPU connected to the ASIC And an image forming apparatus.   When one of the generation of an interrupt when receiving a predetermined number of packet data and the generation of an interrupt at a predetermined fixed time occurs first, the generation of the other interrupt is stopped. 11. The image forming apparatus according to claim 10, further comprising: means.   In an image forming apparatus having an ASIC that is connected to a network, the ASIC stores a received packet data in a memory connected to the ASIC, and a capacity of the stored packet data becomes a predetermined capacity. And a data received by generating an interrupt to the CPU connected to the ASIC when the determination means determines that the capacity of the packet data has reached a predetermined capacity. And an image forming apparatus.

Images