JP2005260449A - Ad converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an AD converter regulating the gain internally for input signals in different signal level range. <P>SOLUTION: An AD converter 102 performs AD conversion of an analog input signal 101 to produce a digital output signal 104. The AD converter 102 can alter the conversion resolution, i.e. the quantization width, according to an external gain control signal 103. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an AD converter capable of changing an input / output gain, and the AD converter is used in communication, audio signal processing, image signal processing, and the like.

Patent Document 1 proposes a circuit that changes the resolution of an AD converter that quantizes a signal according to the average level of an input signal and outputs the signal with a desired resolution. In this invention, it is assumed that the input signal is quantized by the pipeline AD converter, and the number of conversion stages from the first conversion stage to the number of conversion stages used is controlled according to the required resolution. It proposes to stop the operation of unused conversion stages and reduce the current consumption.
JP 2003-174364 A (publication date: June 20, 2003)

  In the circuit described above, as the necessary resolution decreases, the operation is stopped as stages not used for conversion in order from the last pipeline stage. However, since the pipeline stage generally amplifies analog signals in order from the first stage, the contribution to noise becomes larger as the stage is located near the first stage. Accordingly, in order to obtain a desired S / N for the output signal, the S / N required for each stage is the largest at the first stage and becomes smaller from the second stage onwards. That is, it is preferable that the input conversion noise is smaller as it is closer to the first pipeline stage.

  This usually means that the current consumption at the first stage is the largest, and the current consumption becomes smaller as the stage is later after the second stage. Therefore, the reduction of the current consumption obtained by stopping the operation of the stage located at the rear stage, that is, the reduction of the power consumption is not so great.

  When the signal level range of the input signal changes, as shown in FIG. 8, the signal is once amplified with a gain corresponding to the signal level range and then input to the AD converter. . In FIG. 8, a variable gain amplifier 802 is provided in front of the AD converter 804, and the gain control signal 803 changes the gain of the variable gain amplifier 802 according to the signal level range of the input signal 801. The input signal 801 is amplified with a set gain by the variable gain amplifier 802 and then input to the AD converter 804 and output as an output signal 805 which is a digital signal.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to realize an AD converter capable of performing gain adjustment internally for input signals having different signal level ranges. Further, in such an AD converter, a pipeline type AD converter capable of reducing power consumption is realized.

  In order to solve the above problems, the AD converter of the present invention is characterized in that the conversion resolution for an analog input signal can be changed based on a control signal from the outside.

  According to the above invention, when there are several signal level ranges of the input signal, the conversion resolution is changed in accordance with each signal level range, that is, the input signal having a different signal level range is changed by changing the quantization width. The number of quantization levels can be the same. Therefore, gain adjustment inside the AD converter is possible, and it is not necessary to once amplify the input signal with a gain corresponding to the signal level range in the previous stage of the AD converter.

  As a result, there is an effect that it is possible to realize an AD converter capable of performing gain adjustment internally for input signals in different signal level ranges.

  In order to solve the above problems, the AD converter of the present invention includes a pipeline type AD converter in which a plurality of pipeline stages are connected in series, and the pipeline stage in which the input signal is input first. The conversion resolution is changed by making the variable variable.

  According to the above invention, the conversion resolution is changed and the number of quantization levels is the same by changing the pipeline stage to which the input signal is first input for input signals in different signal level ranges. There is an effect that can be made.

  In order to solve the above-described problem, the AD converter according to the present invention stops the operation of the pipeline stage located on the upstream side of the pipeline stage to which the input signal is first input, or consumes power. It is characterized by controlling to a mode in which the image quality decreases.

  According to the above invention, the operation of the pipeline stage located upstream of the pipeline stage to which the input signal is first input, that is, upstream of the pipeline stage used for AD conversion, is stopped. Since the pipeline stage for stopping the operation is sequentially selected from the first pipeline stage to the subsequent stage side, the operation is stopped in order from the pipeline stage having a large contribution to noise. Therefore, the operation is stopped in order from the largest S / N, in other words, from the pipeline stage having the largest power consumption, so that the reduction in power consumption is increased.

  In order to solve the above problems, the AD converter according to the present invention is characterized in that the conversion resolution is changed by changing a reference value of AD conversion for the input signal.

  According to the above invention, by changing the reference value of AD conversion for an input signal with respect to input signals in different signal level ranges, the conversion resolution can be changed to make the number of quantization levels the same. There is an effect that can be done.

  In order to solve the above problems, the AD converter of the present invention includes a pipeline type AD converter in which a plurality of pipeline stages are connected in series, and the reference value for AD conversion of each pipeline stage is variable. It is characterized by that.

  According to the above invention, the AD conversion reference value for the input signal is changed by changing the AD conversion reference value of each pipeline stage for the input signals having different signal level ranges, and the quantum conversion is performed. There is an effect that the number of conversion levels can be made the same.

  In order to solve the above problems, the AD converter according to the present invention is characterized in that the conversion resolution is changed by changing the pipeline stage to which the input signal is first input.

  According to the above invention, for input signals with different signal level ranges, in addition to the reference value, by changing the pipeline stage to which the input signal is first input, the conversion resolution is changed and quantization is performed. The number of levels can be made the same.

  In order to solve the above-described problem, the AD converter according to the present invention stops the operation of the pipeline stage located on the upstream side of the pipeline stage to which the input signal is first input, or consumes power. It is characterized by controlling to a mode in which the image quality decreases.

  According to the above invention, the operation of the pipeline stage located upstream of the pipeline stage to which the input signal is first input, that is, upstream of the pipeline stage used for AD conversion, is stopped. Since the pipeline stage for stopping the operation is sequentially selected from the first pipeline stage to the subsequent stage side, the operation is stopped in order from the pipeline stage having a large contribution to noise. Therefore, the operation is stopped in order from the largest S / N, in other words, from the pipeline stage having the largest power consumption, so that the reduction in power consumption is increased.

  As described above, the AD converter of the present invention can change the conversion resolution for an analog input signal based on an external control signal. There is an effect that the gain can be adjusted inside the converter.

[First Embodiment]
The first embodiment of the present invention will be described below with reference to FIG.

  FIG. 1 shows a configuration of the AD converter 102 according to the present embodiment.

  The AD converter 102 AD-converts the input signal 101 that is an analog signal and outputs the result as an output signal 104 that is a digital signal. The AD converter 102 can change the conversion resolution in accordance with an external gain control signal 103. Here, changing the conversion resolution means changing the quantization width. For example, when the input voltage width as the signal level range of the input signal 101 is from 0V to 1V, if the quantization width is 10 mV, the input signal 101 is quantized to 100 levels. When the input range is 0V to 10V and the quantization width is 100 mV, the input signal 101 is also quantized to 100 levels. This is because an AD converter with a quantization width of 100 mV is used, the signal is quantized as it is when the input range is from 0 V to 10 V, and the signal is amplified 10 times when the input range is from 0 V to 1 V. It is equivalent to the process of quantizing from.

  By changing the conversion resolution in this way, the analog conversion level of the LSB changes. Therefore, when there are several signal level ranges of the input signal 101, if the conversion resolution is changed in accordance with each signal level range, that is, if the quantization width is changed, the input signal 101 with a different signal level range is applied. The number of levels of quantization can be made the same.

In this embodiment, by changing the conversion resolution of the AD converter 102 with respect to the input signal 101 using the gain control signal 103, gain adjustment inside the AD converter becomes possible, and the input signal is input before the AD converter. There is no need to amplify with a gain corresponding to the signal level range. As a result, it is possible to realize processing equivalent to signal processing having a configuration in which the variable gain amplifier 802 and the AD converter 804 are connected in series as shown in FIG.
[Second Embodiment]
The second embodiment of the present invention will be described below with reference to FIG.

  FIG. 2A shows a configuration of the AD converter 250 according to the present embodiment.

  The AD converter 250 includes an input position selection switch 201, pipeline stages 204, 205, 206, and 207, and a digital arithmetic unit 209. As a result, the AD converter includes a pipeline type AD converter. .

  The input position selection switch 201 includes an input terminal 201in for an input signal 203, which is an analog signal, and output terminals 201oa, 201ob, 201oc, and 201od that are selectively connected to the input terminal 201in. A gain control signal 202 is input to the input position selection switch 201. The gain control signal 202 is a signal whose content corresponds to the magnitude of the signal level range of the input signal 203, and this determines which of the output terminals 201oa, 201ob, 201oc, 201od is connected to the input terminal 201in. Is done.

  The pipeline stages 204, 205, 206, and 207 constitute AD conversion stages of pipeline AD converters connected in series so as to be arranged in the order from the upstream side to the downstream side. Although the pipeline stage is four stages here, it may generally be a plurality of stages. Each pipeline stage includes an analog input terminal Ain, a digital output terminal Dout, and an analog output terminal Aout. The analog input terminal Ain of the first pipeline stage 204 is connected to the output terminal 201oa of the input position selection switch 201. In adjacent pipeline stages, the analog output terminal Aout of the preceding pipeline stage and the analog input terminal Ain of the subsequent pipeline stage are connected to each other. The analog input terminal Ain of the pipeline stage 205 is connected to the output terminal 201ob of the input position selection switch 201. The analog input terminal Ain of the pipeline stage 206 is connected to the output terminal 201 oc of the input position selection switch 201. The analog input terminal Ain of the pipeline stage 207 is connected to the output terminal 201od of the input position selection switch 201.

  The digital output terminal Dout of each pipeline stage inputs the quantization result of the signal input to the analog input terminal Ain by each pipeline stage to the digital calculator 209. The analog output terminal Aout of each pipeline stage is an analog signal obtained by amplifying the difference (quantization error) between the signal input to the analog input terminal Ain and the DA conversion result of the digital signal output from the digital output terminal Dout. , Input to the analog input terminal Ain of the next pipeline stage. The digital arithmetic unit 209 outputs the AD conversion result of the input signal 203 input to the AD converter 250 as a digital signal 210 based on the quantized value output from the digital output terminal Dout of each pipeline stage.

  In the AD converter 250 having the above-described configuration, the input signal 203 is input / output switched by the input position selection switch 201 by the gain control signal 202 indicating the gain required according to the signal level range. Input to any of the line stages 204, 205, 206, and 207. When the input signal 203 is first input to the pipeline stage 204, the input signal 203 is processed by the pipeline stage 204 and then sequentially processed by the pipeline stages 205, 206, and 207. When the input signal 203 is first input to the pipeline stage 205, the input signal 203 is processed by the pipeline stage 205 and then sequentially processed by the pipeline stages 206 and 207. When the input signal 203 is first input to the pipeline stage 206, the input signal 203 is processed by the pipeline stage 206 and then processed by the pipeline stage 207. When the input signal 203 is first input to the pipeline stage 207, the input signal 203 is processed only by the pipeline stage 207.

  Here, each pipeline stage outputs a quantization value for the signal input to the analog input terminal Ain from the digital output terminal Dout, and outputs an analog signal obtained by amplifying the quantization error from the analog output terminal Aout. For example, when each pipeline stage binarizes the analog input Ain (0 ≦ Ain ≦ 16), Dout and Aout are calculated so that the relationship of Aout = 2 · (Ain− (8 × Dout)) is established. . Here, Dout is 0 or 1, and 0 ≦ Aout ≦ 16.

  When the digital output value of the pipeline stage 204 is N1, the digital output value of the pipeline stage 205 is N2, the digital output value of the pipeline stage 206 is N3, and the digital output value of the pipeline stage 207 is N4, the digital computing unit 209 Outputs 8 × N1 + 4 × N2 + 2 × N3 + N4 as an AD conversion result. Therefore, the analog input signal 203 in the range from 0 to 16 is quantized to 16 levels with a quantization width of 1.

  Next, when the input signal 203 is first input to the pipeline stage 204 by the input position selection switch 201, the quantization width and the number of levels finally obtained are input to the input position selection switch 201 in FIG. The quantization width and the number of levels finally obtained when the signal 203 is first input to the pipeline stage 205 are shown in FIG. 2C, and the input signal 203 is first input to the pipeline stage 206 by the input position selection switch 201. FIG. 2D shows the quantization width and the number of levels finally obtained when input.

  When the range of the analog input signal is in the range of 0 to 4 as shown by the arrow in FIG. 2B in the range of 0 to 16, this signal is input to the pipeline stage 204, so that the signal Is quantized to 4 levels. Further, when the range of the analog input signal is in the range of 0 to 8 as shown by the arrow in FIG. 2C among the range of 0 to 16, this signal is input to the pipeline stage 205. , The signal is quantized to 4 levels. Further, when the range of the analog input signal is in the range of 0 to 16 as indicated by the arrow in FIG. 2D in the range of 0 to 16, this signal is input to the pipeline stage 206. , The signal is quantized to 4 levels.

  Accordingly, when the signal level range of the input signal 203 is in the range of 0 to 4 as shown in FIG. 2B, inputting this input signal 203 to the pipeline stage 204 will change the input signal 203 to 4 This is equivalent to double amplification and input to the pipeline stage 206. Further, when the signal level range of the input signal 203 is in the range of 0 to 8 as shown in FIG. 2C, inputting this input signal 203 to the pipeline stage 205 will cause the input signal 203 to be 2 This is equivalent to double amplification and input to the pipeline stage 206.

  As described above, in the present embodiment, by changing the pipeline stage to which the input signal 203 is first input with respect to the input signal 203 having a different signal level range, the quantization width is changed, that is, the conversion is performed. The resolution can be changed to make the number of quantization levels the same. By changing the conversion resolution of the AD converter, it is possible to adjust the gain inside the AD converter, and it is not necessary to once amplify the input signal with a gain corresponding to the signal level range in the previous stage of the AD converter.

An AD converter having a necessary gain can be realized by using a necessary part of the variable signal processing circuit including pipeline stages connected in series described in the present embodiment.
[Third Embodiment]
The third embodiment of the present invention will be described below with reference to FIG.

  FIG. 3 shows a configuration of the AD converter 350 according to the present embodiment.

  The AD converter 350 includes an input position selection switch 301, an operation state control circuit 302, pipeline stages 305, 306, 307, and 308, and a digital calculator 309.

  The input position selection switch 301 includes an input terminal 301in for an input signal 303, which is an analog signal, and output terminals 301oa, 301ob, 301oc, and 301od that are selectively connected to the input terminal 301in. A gain control signal 304 is input to the input position selection switch 301. The gain control signal 304 is a signal whose content corresponds to the size of the signal level range of the input signal 303, and this determines which of the output terminals 301oa, 301ob, 301oc, and 301od the input terminal 301in is connected to. Is done.

  The pipeline stages 305, 306, 307, and 308 constitute AD conversion stages of pipeline AD converters that are connected in series so that they are arranged in this order from the upstream side to the downstream side. Although the pipeline stage is four stages here, it may generally be a plurality of stages. Each pipeline stage includes an analog input terminal Ain, a digital output terminal Dout, an analog output terminal Aout, and a power supply control terminal PD. The analog input terminal Ain of the first pipeline stage 305 is connected to the output terminal 301oa of the input position selection switch 301. In adjacent pipeline stages, the analog output terminal Aout of the preceding pipeline stage and the analog input terminal Ain of the subsequent pipeline stage are connected to each other. The analog input terminal Ain of the pipeline stage 306 is connected to the output terminal 301ob of the input position selection switch 301. The analog input terminal Ain of the pipeline stage 307 is connected to the output terminal 301 oc of the input position selection switch 301. The analog input terminal Ain of the pipeline stage 308 is connected to the output terminal 301od of the input position selection switch 301.

  The digital output terminal Dout of each pipeline stage inputs the quantization result of the signal input to the analog input terminal Ain by each pipeline stage to the digital calculator 309. The analog output terminal Aout of each pipeline stage is an analog signal obtained by amplifying the difference (quantization error) between the signal input to the analog input terminal Ain and the DA conversion result of the digital signal output from the digital output terminal Dout. , Input to the analog input terminal Ain of the next pipeline stage. The digital computing unit 309 outputs the AD conversion result of the input signal 303 input to the AD converter 350 as a digital signal 310 based on the quantized value output from the digital output terminal Dout of each pipeline stage.

  The power control terminal PD is a terminal to which a stage control signal PD (substitute with the same reference numeral as the power control terminal) output from the operation state control circuit 302 is input. Each pipeline stage is switched between operation and operation stop according to the content of the stage control signal PD. The control signal PD1 is input to the power supply control terminal PD of the pipeline stage 305, the control signal PD2 is input to the power supply control terminal PD of the pipeline stage 306, and the control signal PD3 is input to the power supply control terminal PD of the pipeline stage 307. Is entered. However, since the final pipeline stage 308 is always operated, the stage control signal PD is not input.

  The operation state control circuit 302 receives a gain control signal 304 that is the same signal as the control signal of the input position selection switch 301, and a stage control signal PD that instructs the pipeline stage used for AD conversion of the input signal 303 to operate. And a stage control signal PD for instructing to stop the operation to a pipeline stage not used for AD conversion. Thereby, the operation state control circuit 302 controls the operation state of each pipeline stage.

  When the pipeline stage uses an operational amplifier, the operation state control circuit 302 outputs a stage control signal PD for controlling the bias current of the operational amplifier, thereby switching between the operation of the pipeline stage and the stop of the operation. It is possible.

  In the AD converter 350 having the above-described configuration, the input signal 303 is input / output switched by the input position selection switch 201 by the gain control signal 304 indicating the gain required according to the signal level range. Input to any of the line stages 305, 306, 307, and 308.

  When the input signal 303 is first input to the pipeline stage 305, the input signal 303 is processed in the pipeline stage 305 and then sequentially processed in the pipeline stages 306, 307, and 308. At this time, the stage control signals PD1, PD2, and PD3 output from the operation state control circuit 302 in response to the gain control signal 304 are all signals for instructing the operation. Therefore, all the pipeline stages 305 to 308 operate.

  When the input signal 303 is first input to the pipeline stage 306, the input signal 303 is processed by the pipeline stage 306 and then sequentially processed by the pipeline stages 307 and 308. At this time, among the stage control signals PD1, PD2, and PD3 output from the operation state control circuit 302 in response to the gain control signal 304, the stage control signal PD1 is a signal for instructing to stop the operation, and the stage control signals PD2 and PD3 operate. Is a signal for instructing. Accordingly, the pipeline stage 305 stops operating, and the pipeline stages 306 to 308 operate. Since the operation of the pipeline stage 305 is stopped, power consumption is reduced.

  When the input signal 303 is first input to the pipeline stage 307, the input signal 303 is processed by the pipeline stage 307 and then processed by the pipeline stage 308. At this time, among the stage control signals PD1, PD2, and PD3 output from the operation state control circuit 302 in response to the gain control signal 304, the stage control signals PD1 and PD2 are signals for instructing to stop the operation, and the stage control signal PD3 is operated. Is a signal for instructing. Accordingly, the pipeline stages 305 and 306 stop operating, and the pipeline stages 307 and 308 operate. Since the operation of the pipeline stages 305 and 306 is stopped, power consumption is reduced.

  When the input signal 303 is first input to the pipeline stage 308, the input signal 303 is processed only by the pipeline stage 308. At this time, the stage control signals PD1, PD2, and PD3 output from the operation state control circuit 302 in response to the gain control signal 304 are signals for instructing to stop the operation. Accordingly, the pipeline stages 305, 306, and 307 stop operating, and the pipeline stage 308 operates. Since the operations of the pipeline stages 305, 306, and 307 are stopped, power consumption is reduced.

  As described above, in this embodiment, the operation of the pipeline stage that is positioned upstream of the pipeline stage to which the input signal 303 is input, that is, upstream of the pipeline stage used for AD conversion, is stopped. Thus, power consumption can be reduced. Since the pipeline stage for stopping the operation is sequentially selected from the first pipeline stage 305 to the subsequent stage side, the operation is stopped in order from the pipeline stage having a large contribution to noise. Therefore, the operation is stopped in order from the largest S / N, in other words, the pipeline stage having the largest power consumption, and the power consumption is reduced.

  Note that power consumption can be reduced by controlling the pipeline stage to a mode in which the power consumption is reduced instead of stopping the operation of the pipeline stage.

In this embodiment, a circuit composed of pipeline stages connected in series can be partially used by selecting each pipeline stage, which is a signal processing circuit, as necessary. Therefore, the circuit is regarded as a variable signal processing circuit. be able to. An AD converter having a necessary gain can be realized by using a necessary part of such a variable signal processing circuit. In particular, when the input signal is small, a large gain may be required, such as when controlling the gain of the variable signal processing circuit according to the level of the input signal to control the output signal to be at a substantially constant level. For this reason, it is preferable to use a signal processing circuit having a smaller input conversion noise for a signal processing circuit closer to the first stage. In this embodiment, when the level of the input signal is relatively high, the first-stage signal processing circuit (pipeline stage) with low input conversion noise is stopped or the power consumption is reduced to save power consumption. Can be planned.
[Fourth Embodiment]
The following describes the fourth embodiment of the present invention with reference to FIG.

  FIG. 4 shows the configuration of the AD converter 402 according to this embodiment.

  The AD converter 402 AD-converts the input signal 401 that is an analog signal and outputs it as an output signal 403 that is a digital signal. A reference value control signal 406 from a reference value generation circuit 404 provided outside is input to the AD converter 402. The reference value generation circuit 404 generates the control signal 406 based on the gain control signal 405 that is input. The gain control signal 405 is a signal having a gain content corresponding to the signal level range of the input signal 401 of the AD converter 402, and the reference value control signal 406 instructs setting of a reference value corresponding to the signal level range. The signal has the following contents. The AD converter 402 changes a reference value for performing quantization in accordance with an instruction of the input reference value control signal 406. Thus, the AD converter 402 can change the conversion resolution, that is, change the quantization width. The quantization width is set in proportion to the reference value.

  For example, when the signal level range of a certain input signal 401 is 0 to 16 and the quantization width is 1, the reference value is 8, but when the signal level range of the input signal 401 is 0 to 4, the reference value is The value is 2. At this time, the quantization width is ¼, and the number of quantization levels is the same for both input signals 401.

  By changing the conversion resolution in this way, the analog conversion level of the LSB changes. Therefore, when there are several signal level ranges of the input signal 401, if the conversion resolution is changed in accordance with each signal level range, that is, if the quantization width is changed, the input signal 401 with a different signal level range is applied. The number of levels of quantization can be made the same.

  In the present embodiment, by changing the conversion resolution of the AD converter 402 with respect to the input signal 401 using the reference value control signal 406, gain adjustment in the AD converter can be performed, and the input signal is input before the AD converter. Need not be amplified once with a gain corresponding to the signal level range. As a result, it is possible to realize processing equivalent to signal processing having a configuration in which the variable gain amplifier 802 and the AD converter 804 are connected in series as shown in FIG. In this embodiment, when the reference value is multiplied by A, the quantization width becomes A times. This is because the analog input signal 401 is input after being multiplied by 1 / A with respect to the AD converter having a fixed quantization width. Is equivalent to

In this embodiment, the pipeline type AD converter is exemplified as the reference value. However, the reference value is not limited to this, and the weighting amount to be compared with the analog input voltage as in the successive approximation type AD converter is used. The reference value may be used.
[Fifth Embodiment]
The following describes the fifth embodiment of the present invention with reference to FIG.

  FIG. 5 shows a configuration of the AD converter 550 according to the present embodiment.

  The AD converter 550 includes pipeline stages 501, 502, 503, and 504, a reference value generation circuit 505, and a digital arithmetic unit 506. As a result, the AD converter includes a pipeline type AD converter. .

  Pipeline stages 501, 502, 503, and 504 constitute AD conversion stages of pipeline AD converters connected in series so that they are arranged in this order from the upstream side to the downstream side. Although the pipeline stage is four stages here, it may generally be a plurality of stages. Each pipeline stage includes an analog input terminal Ain, a digital output terminal Dout, an analog output terminal Aout, and a reference value setting terminal Vref. The input signal 506 of the AD converter 501 is input to the analog input terminal Ain of the first pipeline stage 501. In adjacent pipeline stages, the analog output terminal Aout of the preceding pipeline stage and the analog input terminal Ain of the subsequent pipeline stage are connected to each other.

  The digital output terminal Dout of each pipeline stage inputs the quantization result of the signal input to the analog input terminal Ain by each pipeline stage to the digital calculator 506. The analog output terminal Aout of each pipeline stage is an analog signal obtained by amplifying the difference (quantization error) between the signal input to the analog input terminal Ain and the DA conversion result of the digital signal output from the digital output terminal Dout. , Input to the analog input terminal Ain of the next pipeline stage. The digital computing unit 506 outputs the AD conversion result of the input signal 506 input to the AD converter 550 as a digital signal 508 based on the quantized value output from the digital output terminal Dout of each pipeline stage.

  A reference value signal Vref from the reference value generation circuit 505 (substitute with the same sign as the reference value setting terminal) is input to the reference value setting terminal Vref of each pipeline stage. Each pipeline stage sets a reference value for performing AD conversion according to the content of the reference value signal Vref. A reference value signal Vref 1 is input to the reference value setting terminal Vref of the pipeline stage 501, a reference value signal Vref 2 is input to the reference value setting terminal Vref of the pipeline stage 502, and a reference value setting terminal Vref of the pipeline stage 503. Is supplied with the reference value signal Vref3, and the reference value setting terminal Vref of the pipeline stage 504 is supplied with the reference value signal Vref4. Here, the reference value is a voltage.

  The reference value generation circuit 505 receives a gain control signal 507 having a gain corresponding to the signal level range of the input signal 506, generates and outputs reference value signals Vref1 to Vref4, and sets them in each pipeline stage. Indicates the size of the reference value to be used.

  In the AD converter 550 configured as described above, the input signal 506 is input to the pipeline stage 501, processed by the pipeline stage 501, and then sequentially processed by the pipeline stages 502, 503, and 504. At this time, reference value signals Vref1 to Vref4 generated by the reference value generation circuit 505 according to the gain control signal 507 are input to each pipeline stage, and a reference value corresponding to the signal level range of the input signal 506 is set.

  Assuming that the signal level range of an input signal 506 is 0 to 16 and the quantization width is 1, the reference value is set to 1 at each pipeline stage for the input signal 506 having a signal level range of 0 to 4. / 4 times. At this time, the quantization width is 1/4. As a result, the number of quantization levels can be kept at 16 for the input signal 506 in different signal level ranges, with the signal amplification before being output from the analog output terminal Aout in each pipeline stage being constant. When the signal level range is larger than 0 to 16, the quantization width may be increased by increasing the reference value in proportion. By changing the quantization width, the same effect as when the amplitude of the input signal 506 is amplified or attenuated can be obtained.

As described above, in the present embodiment, the input signal 506 having different signal level ranges is changed by changing the reference value for AD conversion, thereby changing the quantization width, that is, changing the conversion resolution, and quantizing. The number of levels can be the same. By changing the conversion resolution of the AD converter, it is possible to adjust the gain inside the AD converter, and it is not necessary to once amplify the input signal with a gain corresponding to the signal level range in the previous stage of the AD converter.
[Sixth Embodiment]
The following describes the sixth embodiment of the present invention with reference to FIG.

  FIG. 6 shows a configuration of the AD converter 650 according to the present embodiment.

  The AD converter 650 includes pipeline stages 601, 602, 603, and 604, a reference value generation circuit 605, a digital calculator 606, and an input position selection switch 609. As a result, the AD converter having the pipeline type AD converter is provided. It is a converter.

  The input position selection switch 609 includes an input terminal 609in for an input signal 610 that is an analog signal, and output terminals 609oa, 609ob, 609oc, and 609od that are selectively connected to the input terminal 609in. In addition, a gain control signal 607 is input to the input position selection switch 609. The gain control signal 607 is a signal having contents corresponding to the magnitude of the signal level range of the input signal 610, and this determines which of the output terminals 609oa, 609ob, 609oc, and 609od is connected to the input terminal 609in. Is done.

  The pipeline stages 601, 602, 603, and 604 constitute the AD conversion stages of the pipelined AD converters connected in series so as to be arranged in this order from the upstream side to the downstream side. Although the pipeline stage is four stages here, it may generally be a plurality of stages. Each pipeline stage includes an analog input terminal Ain, a digital output terminal Dout, an analog output terminal Aout, and a reference value setting terminal Vref. The analog input terminal Ain of the first pipeline stage 601 is connected to the output terminal 609oa of the input position selection switch 609. In adjacent pipeline stages, the analog output terminal Aout of the preceding pipeline stage and the analog input terminal Ain of the subsequent pipeline stage are connected to each other. The analog input terminal Ain of the pipeline stage 602 is connected to the output terminal 609ob of the input position selection switch 609. The analog input terminal Ain of the pipeline stage 603 is connected to the output terminal 609oc of the input position selection switch 609. The analog input terminal Ain of the pipeline stage 604 is connected to the output terminal 609od of the input position selection switch 609.

  The digital output terminal Dout of each pipeline stage inputs the quantization result of the signal input to the analog input terminal Ain by each pipeline stage to the digital calculator 606. The analog output terminal Aout of each pipeline stage is an analog signal obtained by amplifying the difference (quantization error) between the signal input to the analog input terminal Ain and the DA conversion result of the digital signal output from the digital output terminal Dout. , Input to the analog input terminal Ain of the next pipeline stage. The digital calculator 606 outputs the AD conversion result of the input signal 610 input to the AD converter 650 as a digital signal 608 based on the quantized value output from the digital output terminal Dout of each pipeline stage.

  A reference value signal Vref from the reference value generation circuit 605 (substitute with the same sign as the reference value setting terminal) is input to the reference value setting terminal Vref of each pipeline stage. Each pipeline stage sets a reference value for performing AD conversion according to the content of the reference value signal Vref. A reference value signal Vref 1 is input to the reference value setting terminal Vref of the pipeline stage 601, a reference value signal Vref 2 is input to the reference value setting terminal Vref of the pipeline stage 602, and a reference value setting terminal Vref of the pipeline stage 603. Is supplied with the reference value signal Vref3, and the reference value setting terminal Vref of the pipeline stage 604 is supplied with the reference value signal Vref4. Here, the reference value is a voltage.

  A reference value generation circuit 605 receives a gain control signal 607, which is the same signal as the control signal of the input position selection switch 609, generates and outputs reference value signals Vref1 to Vref4, and sets a reference for each pipeline stage. Indicates the magnitude of the value.

  In the AD converter 650 having the above-described configuration, the input signal 610 is input / output switched by the input position selection switch 609 by the gain control signal 607 indicating the gain required according to the signal level range. Input to any of the line stages 601, 602, 603, and 604. In any case, the reference value signals Vref1 to Vref4 output from the reference value generation circuit 605 in response to the gain control signal 607 are input to the pipeline stages 601 to 604, and each pipeline stage receives the input signal 610. A reference value corresponding to the signal level range is set.

  When the input signal 610 is first input to the pipeline stage 601, the input signal 610 is processed by the pipeline stage 601 and then sequentially processed by the pipeline stages 602, 603, and 604. When the input signal 610 is first input to the pipeline stage 602, the input signal 610 is processed by the pipeline stage 602 and then sequentially processed by the pipeline stages 603 and 604. When the input signal 610 is first input to the pipeline stage 603, the input signal 610 is processed by the pipeline stage 603 and then processed by the pipeline stage 604. When the input signal 610 is first input to the pipeline stage 604, the input signal 610 is processed only by the pipeline stage 604.

  As described above, in the present embodiment, the input signal 610 having different signal level ranges is made variable by changing the pipeline stage to which the input signal 610 is first input, that is, the conversion width is changed. The resolution can be changed to make the number of quantization levels the same. By changing the conversion resolution of the AD converter, it is possible to adjust the gain inside the AD converter, and it is not necessary to once amplify the input signal with a gain corresponding to the signal level range in the previous stage of the AD converter.

  At the same time, in the present embodiment, by changing the reference value of AD conversion for the input signal 610 having a different signal level range, the quantization width is changed, that is, the conversion resolution is changed, The number of levels can be the same. By changing the conversion resolution of the AD converter, it is possible to adjust the gain inside the AD converter, and it is not necessary to once amplify the input signal with a gain corresponding to the signal level range in the previous stage of the AD converter.

An AD converter having a necessary gain can be realized by using a necessary part of the variable signal processing circuit including pipeline stages connected in series described in the present embodiment.
[Seventh Embodiment]
The seventh embodiment of the present invention will be described below with reference to FIG.

  FIG. 7 shows a configuration of the AD converter 750 according to the present embodiment.

  The AD converter 750 includes pipeline stages 701, 702, 703, and 704, a reference value generation circuit 705, a digital arithmetic unit 706, an input position selection switch 709, and an operation state control circuit 711. As a result, the pipeline AD It is an AD converter provided with a converter.

  The input position selection switch 709 includes an input terminal 709in for an input signal 710, which is an analog signal, and output terminals 709oa, 709ob, 709oc, and 709od that are selectively connected to the input terminal 709in. A gain control signal 707 is input to the input position selection switch 709. The gain control signal 707 is a signal having a gain content corresponding to the magnitude of the signal level range of the input signal 710, whereby the input terminal 709in is connected to any of the output terminals 709oa, 709ob, 709oc, and 709od. Is decided.

  Pipeline stages 701, 702, 703, and 704 constitute each AD conversion stage of a pipelined AD converter connected in series so that they are arranged in this order from the upstream side to the downstream side. Although the pipeline stage is four stages here, it may generally be a plurality of stages. Each pipeline stage includes an analog input terminal Ain, a digital output terminal Dout, an analog output terminal Aout, a reference value setting terminal Vref, and a power supply control terminal PD. The analog input terminal Ain of the first pipeline stage 701 is connected to the output terminal 709 oa of the input position selection switch 709. In adjacent pipeline stages, the analog output terminal Aout of the preceding pipeline stage and the analog input terminal Ain of the subsequent pipeline stage are connected to each other. The analog input terminal Ain of the pipeline stage 702 is connected to the output terminal 709ob of the input position selection switch 709. The analog input terminal Ain of the pipeline stage 703 is connected to the output terminal 709oc of the input position selection switch 709. The analog input terminal Ain of the pipeline stage 704 is connected to the output terminal 709od of the input position selection switch 709.

  The digital output terminal Dout of each pipeline stage inputs the quantization result of the signal input to the analog input terminal Ain by each pipeline stage to the digital calculator 706. The analog output terminal Aout of each pipeline stage is an analog signal obtained by amplifying the difference (quantization error) between the signal input to the analog input terminal Ain and the DA conversion result of the digital signal output from the digital output terminal Dout. , Input to the analog input terminal Ain of the next pipeline stage. The digital calculator 706 outputs the AD conversion result of the input signal 710 input to the AD converter 750 as a digital signal 708 based on the quantized value output from the digital output terminal Dout of each pipeline stage.

  A reference value signal Vref from the reference value generation circuit 705 (substitute with the same sign as the reference value setting terminal) is input to the reference value setting terminal Vref of each pipeline stage. Each pipeline stage sets a reference value for performing AD conversion according to the content of the reference value signal Vref. A reference value signal Vref 1 is input to the reference value setting terminal Vref of the pipeline stage 701, a reference value signal Vref 2 is input to the reference value setting terminal Vref of the pipeline stage 702, and a reference value setting terminal Vref of the pipeline stage 703. Is supplied with the reference value signal Vref3, and the reference value setting terminal Vref of the pipeline stage 704 is supplied with the reference value signal Vref4. Here, the reference value is a voltage.

  The reference value generation circuit 705 receives a gain control signal 707 that is the same signal as the control signal of the input position selection switch 709, generates and outputs reference value signals Vref1 to Vref4, and sets the reference values for each pipeline stage. Indicates the magnitude of the value.

  The power supply control terminal PD of each pipeline stage is a terminal to which a stage control signal PD (substitute with the same reference numeral as the power supply control terminal) output from the operation state control circuit 711 is input. Each pipeline stage is switched between operation and operation stop according to the content of the stage control signal PD. The control signal PD1 is input to the power supply control terminal PD of the pipeline stage 701, the control signal PD2 is input to the power supply control terminal PD of the pipeline stage 702, and the control signal PD3 is input to the power supply control terminal PD of the pipeline stage 703. Is entered. However, since the final pipeline stage 704 is always operated, the stage control signal PD is not input.

  The operation state control circuit 711 receives the gain control signal 707 which is the same signal as the control signal of the input position selection switch 709 and the reference value generation circuit 705, and operates the pipeline stage used for AD conversion of the input signal 710. A stage control signal PD to be instructed is input, and a stage control signal PD to instruct to stop the operation is input to a pipeline stage not used for AD conversion. Thereby, the operation state control circuit 711 controls the operation state of each pipeline stage.

  When the pipeline stage uses an operational amplifier, the operation state control circuit 711 switches between the operation of the pipeline stage and the stop of the operation by outputting a gain control signal 707 for controlling the bias current of the operational amplifier. It is possible.

  In the AD converter 750 having the above-described configuration, the input signal 710 is input / output switched by the input position selection switch 709 by the gain control signal 707 indicating the gain required according to the signal level range. It is input to any of the line stages 701, 702, 703, and 704.

  When the input signal 710 is first input to the pipeline stage 701, the input signal 710 is processed by the pipeline stage 701 and then sequentially processed by the pipeline stages 702, 703, and 704. At this time, the stage control signals PD1, PD2, and PD3 output from the operation state control circuit 711 in response to the gain control signal 707 are all signals for instructing the operation. Therefore, all the pipeline stages 701 to 704 operate. At this time, reference value signals Vref1 to Vref4 generated by the reference value generation circuit 711 according to the gain control signal 707 are input to each pipeline stage, and a reference value corresponding to the signal level range of the input signal 710 is set. .

  When the input signal 710 is first input to the pipeline stage 702, the input signal 710 is processed by the pipeline stage 702 and then sequentially processed by the pipeline stages 703 and 704. At this time, among the stage control signals PD1, PD2, and PD3 output from the operation state control circuit 711 in response to the gain control signal 707, the stage control signal PD1 is a signal that instructs the stop of the operation, and the stage control signals PD2 and PD3 operate. Is a signal for instructing. Accordingly, the pipeline stage 701 stops operating, and the pipeline stages 702 to 704 operate. Since the operation of the pipeline stage 701 is stopped, power consumption is reduced. At this time, reference value signals Vref1 to Vref4 generated by the reference value generation circuit 711 according to the gain control signal 707 are output from the reference value generation circuit 711 to each pipeline stage. Only in 702 to 704, a reference value corresponding to the signal level range of the input signal 710 is set.

  When the input signal 710 is first input to the pipeline stage 703, the input signal 710 is processed by the pipeline stage 703 and then processed by the pipeline stage 704. At this time, among the stage control signals PD1, PD2, and PD3 output from the operation state control circuit 711 in response to the gain control signal 707, the stage control signals PD1 and PD2 are signals for instructing to stop the operation, and the stage control signal PD3 is operated. Is a signal for instructing. Accordingly, the pipeline stages 701 and 702 stop operating, and the pipeline stages 703 and 704 operate. Since the operation of the pipeline stages 701 and 702 is stopped, power consumption is reduced. At this time, reference value signals Vref1 to Vref4 generated by the reference value generation circuit 711 according to the gain control signal 707 are output from the reference value generation circuit 711 to each pipeline stage. Only 703 and 704 are set with reference values corresponding to the signal level range of the input signal 710.

  When the input signal 710 is first input to the pipeline stage 704, the input signal 710 is processed only by the pipeline stage 704. At this time, the stage control signals PD1, PD2, and PD3 output from the operation state control circuit 711 in response to the gain control signal 707 are all signals for instructing to stop the operation. Accordingly, the pipeline stages 701 to 703 stop operating, and the pipeline stage 704 operates. Since the operations of the pipeline stages 701 to 703 are stopped, power consumption is reduced. At this time, reference value signals Vref1 to Vref4 generated by the reference value generation circuit 711 according to the gain control signal 707 are output from the reference value generation circuit 711 to each pipeline stage. Only at 704, a reference value corresponding to the signal level range of the input signal 710 is set.

  As described above, in the present embodiment, by changing the pipeline stage to which the input signal 710 is first input with respect to the input signal 710 having a different signal level range, the quantization width is changed, that is, conversion is performed. The resolution can be changed to make the number of quantization levels the same. By changing the conversion resolution of the AD converter, it is possible to adjust the gain inside the AD converter, and it is not necessary to once amplify the input signal with a gain corresponding to the signal level range in the previous stage of the AD converter.

  At the same time, in the present embodiment, by changing the reference value of AD conversion for the input signal 710 having a different signal level range, the quantization width is changed, that is, the conversion resolution is changed, The number of levels can be the same. By changing the conversion resolution of the AD converter, it is possible to adjust the gain inside the AD converter, and it is not necessary to once amplify the input signal with a gain corresponding to the signal level range in the previous stage of the AD converter.

  At the same time, in the present embodiment, by stopping the operation of the pipeline stage located on the upstream side of the pipeline stage to which the input signal 710 is input, that is, on the upstream side of the pipeline stage used for AD conversion. , Power consumption can be reduced. Since the pipeline stage for stopping the operation is sequentially selected from the first pipeline stage 701 to the subsequent stage, the operation is stopped in order from the pipeline stage having a large contribution to noise. Therefore, the operation is stopped in order from the largest S / N, in other words, the pipeline stage having the largest power consumption, and the power consumption is reduced.

  Note that power consumption can be reduced by controlling the pipeline stage to a mode in which the power consumption is reduced instead of stopping the operation of the pipeline stage.

  In this embodiment, a circuit composed of pipeline stages connected in series can be partially used by selecting each pipeline stage, which is a signal processing circuit, as necessary. Therefore, the circuit is regarded as a variable signal processing circuit. be able to. An AD converter having a necessary gain can be realized by using a necessary part of such a variable signal processing circuit. In particular, when the input signal is small, a large gain may be required, such as when controlling the gain of the variable signal processing circuit according to the level of the input signal to control the output signal to be a substantially constant level. For this reason, it is preferable to use a signal processing circuit having a smaller input conversion noise for a signal processing circuit closer to the first stage. In this embodiment, when the input signal level is relatively high, the first-stage signal processing circuit (pipeline stage) with low input conversion noise is stopped or the power consumption is reduced to reduce power consumption. Can be planned.

  The present invention can be suitably used in communication, audio signal processing, image signal processing, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a configuration of an AD converter according to a first embodiment of the present invention. FIG. 4 shows a second embodiment of the present invention, where (a) is a block diagram showing the configuration of an AD converter, and (b) through (d) show the relationship between the signal level range of an input signal and the quantization width. FIG. It is a block diagram which shows the 3rd Embodiment of this invention and shows the structure of AD converter. FIG. 9 is a block diagram illustrating a configuration of an AD converter according to a fourth embodiment of the present invention. 10 is a block diagram illustrating a configuration of an AD converter according to a fifth embodiment of the present invention. FIG. 10 is a block diagram illustrating a configuration of an AD converter according to a sixth embodiment of the present invention. FIG. 10 is a block diagram illustrating a configuration of an AD converter according to a seventh embodiment of the present invention. FIG. It is a block diagram which shows the structure of the circuit which performs AD conversion with the combination of a variable gain amplifier and AD converter.

Explanation of symbols

102, 250, 350, 402, 550, 650, 750
AD converters 101, 203, 303, 401, 506, 610, 710
Input signal 103, 202, 304, 405, 507, 607, 707
Gain control signal (control signal)
204-207, 305-308, 501-504, 601-604, 701-704
Pipeline stage

Claims (7)

  An AD converter characterized in that the conversion resolution for an analog input signal can be changed based on an external control signal.   A pipeline AD converter in which a plurality of pipeline stages are connected in series is provided, and the conversion resolution is changed by changing the pipeline stage to which the input signal is first input. The AD converter according to claim 1.   3. The operation of the pipeline stage located on the upstream side of the pipeline stage to which the input signal is initially input is controlled to a mode in which the operation is stopped or power consumption is reduced. The AD converter described.   The AD converter according to claim 1, wherein the conversion resolution is changed by changing a reference value of AD conversion for the input signal.   5. The AD converter according to claim 4, further comprising a pipeline type AD converter in which a plurality of pipeline stages are connected in series, wherein a reference value for AD conversion of each of the pipeline stages is variable. .   6. The AD converter according to claim 5, wherein the conversion resolution is changed by making the pipeline stage to which the input signal is first input variable.   7. The operation of the pipeline stage located on the upstream side of the pipeline stage to which the input signal is first input is controlled to a mode in which the operation is stopped or power consumption is reduced. The AD converter described.

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