JP2005260446A - Pll circuit and using method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the phase of a frequency of a signal to be generated fluctuates because a leak current flows due to the difference in voltage between electrodes of a capacitor and a control voltage cannot be defined highly precisely in a conventional PLL (Phase Locked Loop) circuit. <P>SOLUTION: This PLL circuit comprises a voltage-controlled oscillator and a loop filter. Two electrodes forming the capacitor are mutually substantially defined into an equal voltage. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit and a method of using the same.

  In order to cause the voltage controlled oscillator to generate a signal having a frequency corresponding to the control voltage, the PLL circuit supplies the voltage controlled oscillator with the control voltage defined by the frequency of the signal to be generated and the phase difference between the frequencies of the generated signals. It has a loop filter to apply. The loop filter includes a capacitor, and the control voltage is defined by flowing a charging current into the capacitor and discharging a discharging current from the capacitor.

  However, since a leak current flows between the two electrodes of the capacitor due to a tunnel effect due to a difference in voltage applied between the two electrodes, the above control voltage is defined with high accuracy. As a result, the frequency of the generated signal fluctuates.

  In order to solve the above-described problem, a PLL circuit according to the present invention includes a voltage-controlled oscillator that generates a signal having the frequency based on a control voltage for defining a frequency, and a desired signal to be generated by the voltage-controlled oscillator. The control voltage is generated by discharging the charging current and sucking the discharging current defined by the phase difference between the frequency of the signal and the actual frequency of the signal generated by the voltage controlled oscillator, and the voltage control is performed on the generated control voltage. A loop filter applied to an oscillator, the loop filter having a capacitor used for charging by the charging current and discharging by the discharging current, and the two electrodes constituting the capacitor are substantially equal in voltage to each other Stipulated in

  According to the PLL circuit of the present invention, the two electrodes of the capacitor constituting the loop filter are regulated to be substantially equipotential to each other, that is, no voltage difference exists between the two electrodes. Therefore, it is possible to reduce the occurrence of leakage current due to the voltage difference between the two electrodes as compared with the conventional case. As a result, it is possible to prevent the frequency phase of the generated signal from fluctuating.

  The PLL circuit according to the present invention described above further includes a storage circuit for storing a voltage corresponding to the desired frequency as the equal voltage.

  According to the present invention, there is provided a method of using the PLL circuit described above, wherein the voltage controlled oscillator generates a signal having the desired frequency, and the memory circuit generates the desired signal generated in the generating step. A storage step for storing a voltage corresponding to the frequency of the generation, a generation stop step for causing the voltage controlled oscillator to stop generating the signal, and a storage step for storing the voltage controlled oscillator in the storage step following the generation stop step. A regeneration step for generating another signal having the desired frequency based on a voltage corresponding to the desired frequency stored in a circuit.

  The method for using the PLL circuit according to the present invention further includes a re-storing step of re-storing another voltage corresponding to the desired frequency included in the other signal generated in the re-generating step, In another regeneration step subsequent to the regeneration step, another signal having the desired frequency based on another voltage corresponding to the desired frequency stored in the voltage storage oscillator in the voltage storage oscillator. Is generated.

  Specific examples of the PLL circuit according to the present invention will be described with reference to the drawings.

<< PLL circuit >>
FIG. 1 is a circuit diagram showing a configuration of a PLL circuit of a specific example. The PLL circuit 1 of a specific example has a conventionally known configuration. Specifically, as shown in FIG. 1, a phase comparator 20, a charge pump 21, a loop filter 22, and a voltage controlled oscillator 23 are provided. And a 1 / N frequency divider 24.

The phase comparator 20 includes a phase of a reference clock S _ref supplied from a reference clock generator (not shown) such as a crystal oscillator, and a phase of a feedback clock S _fb output from the 1 / N frequency divider 24. More specifically, the rising edges or the falling edges of both clocks are compared, and a time difference signal S _up or S _dn that is a pulse signal indicating a time difference between both clocks is output to the charge pump 21. More precisely, when the feedback clock S _fb is delayed from the reference clock S _ref , the phase comparator 20 outputs a time difference signal S _up indicating the delay amount, and the feedback clock S _fb advances from the reference clock S _ref. When it is, the time difference signal S _dn indicating the advance amount is output.

As shown in FIG. 1, the charge pump 21 includes two switches SW1 and SW2. The two switches SW1 and SW2 are connected in series between the power supply voltage and the ground voltage, and are controlled to be opened and closed by the time difference signal _Sup or _Sdn . In the charge pump 21, when the time difference signal S _up is input from the phase comparator 20, a charging current for charging the loop filter 22 having a predetermined value while the time difference signal S _up is being applied. When I _cp is discharged to the loop filter 22 and, on the other hand, the time difference signal S _dn is input from the phase comparator 20, the loop filter 22 has a value similar to the above while the time difference signal S _dn is applied. _Is discharged from the loop filter 22.

The loop filter 22 includes a resistor R and a capacitor C connected in series with each other. The loop filter 22 integrates a charging current I _cp and a discharging current I _cp that are discharged or sucked by the charge pump 21 to correspond to an integrated value of the current. A smoothed control voltage V _cnt for controlling the operation of the voltage controlled oscillator 23 is generated.

More specifically, in a steady operation, the loop filter 22 applies a lock voltage V _L described later to one electrode of the capacitor C, and an offset voltage V approximately equal to the lock voltage V _L to the other electrode. _L 'is applied. As a result, the voltage difference between both electrodes of the capacitor C becomes approximately 0 V, so that the leakage current flowing through the capacitor C can be reduced. As a result, since the control voltage V _cnt applied to the voltage controlled oscillator 23 can be defined with high accuracy, it is possible to reduce the fluctuation of the phase of the frequency of the generated signal S _vco compared to the conventional case. Become.

The voltage controlled oscillator 23 generates a signal S _vco having a frequency f _vco corresponding to the magnitude of the control voltage V _cnt output from the loop filter 22 during steady operation, in other words, a lock having a desired frequency. generating a lock signal S _L having the lock frequency f _L corresponding to the magnitude of the lock voltage V _L is the voltage corresponding to the frequency f _L.

The 1 / N frequency divider 24 _{divides the} signal S _vco output from the voltage controlled oscillator 23 to a frequency of 1 / N to generate a feedback clock S _fb having a feedback frequency f _fb , and the feedback clock S _fb. Is output to the phase comparator 20.

As described above, the voltage controlled oscillator 23 in the PLL circuit 1 of the specific example generates the lock signal S _L having the lock frequency f _L corresponding to the lock voltage V _L during the steady operation.

  FIG. 2 shows a configuration of a capacitor in the loop filter of the specific example. As shown in FIG. 2, the capacitor C constituting the loop filter 22 mainly includes a semiconductor substrate 30, an N well 31, an element isolation film 32, a lower electrode 33, an insulating film 34, and an upper electrode. 35, a dense portion 36, and plugs 37 and 38.

A lower electrode 33, an insulating film 34, and an upper electrode 35 are formed in this order in an N well 31 on the semiconductor substrate 30. One electrode of the capacitor C, that is, an electrode closer to the voltage controlled oscillator 23 is formed. A lock voltage V _L is applied to the upper electrode 35 corresponding to 1 through the plug 38, and an offset voltage V _L ′ is applied to the lower electrode 33 corresponding to the other electrode of the capacitor C through the plug 37. Applied.

Here, the application of the offset voltage V _L ′ to the lower electrode 33 is performed through the dense portion 36 for reducing the ohmic resistance with the plug 37, and at a position adjacent to the dense portion 36. An element isolation film 32 is provided to separate the dense portion 36 from other elements (for example, capacitors and transistors) adjacent to the dense portion 36. With this configuration, the lock voltage V _L and the offset voltage V _L ′ can be applied to the upper electrode 35 and the lower electrode 33 corresponding to both electrodes of the capacitor C shown in FIG.

  FIG. 3 shows a circuit for using the example PLL circuit. Hereinafter, a circuit for using the PLL circuit 1 of a specific example and a usage method will be described with reference to FIG.

A circuit for using the PLL circuit 1 of the specific example includes a storage element 40 such as a nonvolatile memory and a DA converter 41 as shown in FIG. Memory device 40, when the PLL circuit 1 producing and testing in a factory or the like producer (manufacturer), to measure the lock voltage V _L of the PLL circuit 1, the lock voltage V _L to substantially equal the offset voltage V _L 'Is used to store' in digital form, while the DA converter 41 relates to the offset voltage V _L 'stored in digital form in the storage element 40 when the user (user) uses the PLL circuit 1. It is used for applying the information to the other electrode (lower electrode 33 in FIG. 2) of the capacitor C in the loop filter 22 after analog conversion.

In other words, on the producer side, the lock signal S _L is generated by applying the lock voltage V _L to the voltage controlled oscillator 23 (generation process), and the offset voltage V _L that is substantially the same as the lock voltage V _L is generated. 'stored in the storage element 40 (the storage step), to stop the generation of the lock signal S _L by the voltage controlled oscillator 23 (product discontinued step).

On the other hand, when the PLL circuit 1 is transferred from the producer to the user, on the user side, the lock voltage V _L is applied to the voltage controlled oscillator 23, and on the other hand, the offset voltage V _L stored in the storage element 40. Is subjected to digital / analog conversion by the DA converter 41 and applied to the other electrode (lower electrode 33 in FIG. 2) of the capacitor C in the loop filter 22 (applying step). Thus, the lock signal S _L is generated again (regeneration step).

FIG. 4 shows another circuit for using the exemplary PLL circuit. Another circuit for using the PLL circuit 1 of a specific example and a usage method will be described with reference to FIG. Another circuit for using the PLL circuit 1 of the specific example includes an AD converter 50, a storage element 51, a register 52, and a DA converter 53. Hereinafter, to facilitate explanation and understanding, the user of the PLL circuit 1 (user) intermittently or intermittently possible to generate the lock signal S _L to the PLL circuit 1, for example, the user, the PLL circuit 1 It is assumed that the PLL circuit 1 is operated only when an incoming call is received from the mounted mobile phone, and the PLL circuit 1 is not operated at other times. That is, it is assumed that the user oscillates the lock signal S _L stably using the previous PLL circuit 1 and generates the lock signal S _L using the PLL circuit 1 this time after the previous time after a while.

When the user causes the PLL circuit 1 to generate the lock signal S _L last time and thereby the control voltage Vc is set to the lock voltage V _L , the AD converter 50 performs analog-digital conversion on the lock voltage V _L. converts the lock voltage V _L which is an analog value into a digital value, the storage element 51 consisting of a nonvolatile memory or the like, the digital value of the lock voltage V _L, i.e., substantially offset voltage is identical to the locking voltage V _L V _L 'is memorized.

Continuing from the previous time, when the user tries to generate the lock signal S _L in the PLL circuit 1 this time, the lock voltage V _L is applied to the voltage controlled oscillator 23 and the offset voltage V _L ′ is supplied from the storage element 51. After the digital value is read out, it is temporarily stored in the register 52, and the digital value of the offset voltage V _L ′ stored in the register 52 is converted into an analog value by the DA converter 53, whereby the offset voltage V _L ′ is regenerated, and the offset voltage V _L ′ is applied to the other electrode (lower electrode 33 in FIG. 2) of the capacitor C. As a result, this time, the lock voltage V _L is applied to one electrode (upper electrode 35 in FIG. 2) of the capacitor C, and the offset voltage V _L ′ is applied to the other electrode, that is, the voltage between both electrodes of the capacitor C. The difference is approximately 0 V, and as a result, the occurrence of leakage current in the capacitor C can be reduced.

Furthermore, this, if, when the lock voltage is changed from the voltage V _L to V _LL is the voltage V _LL substantially identical voltage V _LL 'stored in the storage device 51 as the offset voltage (re storing step), The new offset voltage V _LL ′ is used when the PLL circuit 1 generates the lock signal S _L next time.

As described above, in the PLL circuit 1 of the specific example, the lock voltage V _L is applied to the other electrode of the capacitor C so that the voltage difference between both electrodes of the capacitor C included in the charge pump 21 is substantially 0V. Since substantially the same offset voltage V _L ′ is applied, it is possible to reduce the leakage current flowing through the capacitor C, thereby reducing the fluctuation of the phase of the generated signal. Become.

The figure which shows the structure of the PLL circuit of a specific example. The figure which shows the structure of the capacitor of a specific example. The figure which shows the circuit for using the PLL circuit of a specific example. The figure which shows the other circuit for using the PLL circuit of a specific example.

Explanation of symbols

1 PLL circuit 22 Loop filter C Capacitor V _L Lock voltage V _L 'Offset voltage.

Claims (4)

A voltage controlled oscillator that generates a signal having the frequency based on a control voltage for defining the frequency;
The control voltage is generated by discharging a charging current and sinking a discharging current defined by a phase difference between a desired frequency of a signal to be generated by the voltage controlled oscillator and an actual frequency of the signal generated by the voltage controlled oscillator. A loop filter for applying the generated control voltage to the voltage controlled oscillator, the loop filter having a capacitor used for charging by the charging current and discharging by the discharging current,
A PLL circuit characterized in that the two electrodes constituting the capacitor are defined to be substantially equal to each other.   The PLL circuit according to claim 1, further comprising a storage circuit for storing a voltage corresponding to the desired frequency as the equal voltage. A method of using the PLL circuit according to claim 2,
A generation step of causing the voltage controlled oscillator to generate a signal having the desired frequency;
A storage step of storing in the storage circuit a voltage corresponding to a desired frequency of the signal generated in the generation step;
A generation stop step of causing the voltage controlled oscillator to stop generating the signal;
Following the generation stop step, the voltage-controlled oscillator generates another signal having the desired frequency based on the voltage corresponding to the desired frequency stored in the storage circuit in the storage step. And a method of using the PLL circuit. A method of using the PLL circuit according to claim 3,
A re-storing step of re-storing another voltage corresponding to the desired frequency of the other signal generated in the regeneration step,
In another regeneration step subsequent to the regeneration step, the voltage-controlled oscillator stores the other frequency having the desired frequency based on the other voltage corresponding to the desired frequency stored in the regeneration step. A method of using a PLL circuit, characterized by generating a signal.

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