JP2012044545A - Pll synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a capacitance value of a capacitor for a temperature-compensation loop filter.SOLUTION: A PLL synthesizer comprises: a phase comparator PD; a loop filter LF; and a voltage-controlled oscillator VCO. In addition, as a temperature-compensation loop, the PLL synthesizer comprises: a comparator CMP that outputs a comparison signal 30 when a frequency control voltage goes out of a control voltage range; a digital filter DF that integrates the comparison signal 30 to generate an M-bit first digital signal 32; ΣΔ modulators 12 and 10 that input the first digital signal 32 and generate a second digital signal 34 corresponding to the first digital signal 32 as an N-bit signal (where N is smaller than M); a temperature-compensation charge pump CPt that converts the second digital signal 34 to a current signal 36; and a temperature-compensation loop filter TF that converts the current signal 36 to a temperature-compensation control voltage. The voltage-controlled oscillator VCO controls a frequency of an output clock CKout based on the temperature-compensation control voltage ft.

Description

  The present invention relates to a PLL synthesizer.

  The PLL synthesizer is a clock generation circuit that generates a high-frequency clock phase-synchronized with a reference clock, and is incorporated in, for example, a wireless system or a processor.

  The PLL synthesizer receives a phase comparator that compares the phase of the output clock with the phase of the reference clock, a loop filter that generates a control voltage according to the phase result of the phase comparator, and an output clock having a frequency based on the control voltage. And a voltage controlled oscillator to be generated. The output clock is fed back to the phase comparator.

  The oscillation frequency of the voltage controlled oscillator changes according to the control voltage generated by the loop filter, and the frequency control range by the control voltage changes according to the control frequency band. The frequency range of the voltage controlled oscillator is widened so that the frequency control range can be changed by the control frequency band.

  Furthermore, the frequency of the voltage controlled oscillator fluctuates due to temperature changes. When the frequency changes beyond the frequency control range by the control voltage due to a change in temperature, control for changing the control frequency band is performed. If the frequency control range is changed by changing the control frequency band, the oscillation frequency may jump and the PLL may be temporarily unlocked. Therefore, it is necessary to prevent the control frequency band from being changed due to a temperature change.

  In order to avoid such a change of the control frequency band due to temperature change, the PLL circuit has a temperature compensation loop in addition to the main PLL loop. The temperature compensation loop compares a control voltage generated by the main PLL loop with a reference voltage, and generates a temperature compensation voltage by a charge pump circuit and a temperature compensation loop filter (LPF) based on the difference value. The temperature compensation voltage finely adjusts the oscillation frequency of the voltage controlled oscillator. That is, by providing a temperature compensation loop, fluctuations in the oscillation frequency due to temperature changes can be suppressed.

  The PLL circuit is described in the following Patent Documents 1, 2, and 3.

Japanese Patent Laid-Open No. 10-322198 JP 2007-259431 A JP 2006-526946 A

  However, it is necessary to increase the time constant of the temperature compensation loop to slow down the response speed so that it does not compete with the control by the main PLL loop. At the same time, the temperature compensation loop filter in the temperature compensation loop is required to remove the noise component by cutting the high frequency component of the output of the charge pump circuit. As a result, the capacitance value of the capacitor in the temperature compensation loop filter must be increased, and it is difficult to incorporate the capacitor in the same integrated circuit chip as the PLL circuit, and the temperature compensation loop filter must be provided outside the chip. Don't be.

  Furthermore, since the capacitance value of the temperature compensation loop filter is increased, when the system is started from the sleep state, the time for charging the capacitor of the loop filter becomes longer and the startup time becomes longer. For this reason, charging current is consumed to maintain the charged state of the capacitor even in the sleep state, which hinders power saving in the sleep state.

  Accordingly, an object of the present invention is to provide a PLL circuit in which the capacitance value of a loop filter in a temperature compensation loop is reduced.

The first aspect of the PLL synthesizer includes a phase comparator that compares the phases of the output clock and the reference clock,
A PLL loop filter that generates a frequency control voltage according to a phase comparison result of the phase comparator;
A voltage controlled oscillator for generating the output clock having a frequency controlled according to the frequency control voltage;
A comparator that outputs a comparison signal having first and second levels when the frequency control voltage is out of a control voltage range;
A digital filter that integrates the comparison signal in synchronization with a first control clock to generate an M-bit first digital signal;
The first digital signal is input, and is synchronized with a second control clock having a frequency higher than that of the first control clock, and is a second digital signal having N bits less than the M bits. A ΔΣ modulator for generating a second digital signal corresponding to the signal;
A temperature compensated charge pump for converting the second digital signal into a current signal;
A capacitor charged and discharged by the current signal, and a temperature compensation loop filter for converting the current signal into a temperature compensation control voltage,
The voltage controlled oscillator controls the frequency of the output clock based on the temperature compensation control voltage.

  According to the first aspect, the capacitor capacity value of the loop filter in the temperature compensation loop can be reduced.

It is a block diagram of the PLL synthesizer relevant to this Embodiment. It is a block diagram of the PLL synthesizer in 1st Embodiment 2 is a schematic configuration diagram of a voltage controlled oscillator VCO. FIG. It is a figure explaining control of the frequency of the voltage controlled oscillator VCO. It is a figure which shows the structure and signal of a temperature compensation loop in this Embodiment. It is a figure which shows the circuit example of digital filter DF. It is a figure which shows the circuit example of a delta-sigma modulator. It is a figure which shows the circuit example of charge pump CPt and the temperature compensation loop filter TF. It is a figure which shows another circuit example of charge pump CPt and the temperature compensation loop filter TF. It is a figure explaining the frequency characteristic of the temperature compensation loop filter TF. It is a figure explaining a temperature compensation loop filter. It is a figure explaining operation | movement when a PLL synthesizer returns. It is a block diagram of the temperature compensation loop of the PLL synthesizer in 2nd Embodiment. It is a figure which shows return operation | movement from the sleep state of the temperature compensation loop of the PLL synthesizer in 2nd Embodiment.

  FIG. 1 is a configuration diagram of a PLL synthesizer related to the present embodiment. The PLL synthesizer uses the phase comparator PD that compares the phase of the output clock CKout divided by the frequency divider DIV1 and the phase of the reference clock R-CLK, and the phase comparison result dPH of the phase comparator PD as a current value. Charge pump circuit CPm for conversion, loop filter LF that integrates the current generated by charge pump circuit CPm and cuts high frequency components to generate frequency control voltage Vt, and has a frequency controlled according to frequency control voltage Vt And a voltage controlled oscillator VCO that generates an output clock CKout.

  A control code Code is supplied to the voltage controlled oscillator VCO from a system side (not shown), and a frequency range controlled by the frequency control voltage Vt is selected corresponding to the control code Code. This feedback loop is the main loop of the PLL.

  In addition to the main loop (solid line in the figure), a temperature compensation loop indicated by a broken line in the figure is provided. The temperature compensation loop compares the frequency control voltage Vt with the reference voltage V_ref, and outputs a comparison signal having first and second levels when the frequency control voltage Vt and the reference voltage V_ref are out of a predetermined control voltage range based on the reference voltage. And a charge pump circuit CPt that outputs a current corresponding to the difference between the frequency control voltage Vt and the reference voltage V_ref. The comparator CMP and the charge pump circuit CPt constitute an OTA (Operational Transconductance Amplifier).

  Then, the temperature compensation loop filter TF integrates the current, cuts the high frequency component, and outputs the temperature compensation control voltage ft. The temperature compensation loop filter TF has a capacitor having a relatively large capacity, and in addition to the integration of the current and the cut of the high frequency component, the time constant of the temperature compensation loop is made larger than that of the main loop.

  Since the PLL loop filter LF of the main loop and the temperature compensation loop filter TF of the temperature compensation loop both have large capacitors, they are often not provided in the chip 10 where the PLL synthesizer circuit is formed. 20 is provided.

  FIG. 2 is a configuration diagram of the PLL synthesizer according to the first embodiment. As in FIG. 1, the PLL synthesizer compares the phase of the output clock CKout by the frequency divider DIV1 with the clock CK2 and the phase of the reference clock R-CLK, and the phase comparison result dPH as a current value. A charge pump circuit CPm that converts the signal into a PLL, a PLL loop filter LF that integrates the current and cuts the high-frequency component to generate the frequency control voltage Vt, and a voltage control that controls the frequency of the output clock CKout according to the frequency control voltage Vt And an oscillator VCO.

  For the voltage controlled oscillator VCO, the frequency range controlled by the frequency control voltage Vt is selected in accordance with the control code Code supplied from the system side. Then, the frequency of the output clock CKout is controlled in accordance with the frequency control voltage Vt within the frequency range. This feedback loop is the main loop of the PLL.

  The PLL synthesizer of the first embodiment also has a temperature compensation loop indicated by a broken line in the figure. This temperature compensation loop compares a comparator that outputs a comparison signal 30 having first and second levels when the frequency control voltage Vt is out of the control voltage range, in synchronization with the first control clock R_CLK. A digital filter DF that integrates the signal 30 to generate an M-bit first digital signal 32 and the first digital signal 32 are input and synchronized with a second control clock having a frequency higher than that of the first control clock R_CLK. ΔΣ modulators 12 and 10 for generating a second digital signal 34 corresponding to the first digital signal, which is an N-bit second digital signal 34 having fewer than M bits, and a second digital signal 34 A temperature compensation loop pump for converting a current signal into a temperature compensation control voltage ft, having a temperature compensation charge pump CPt for converting the current signal 36 and a capacitor charged and discharged by the current signal 36 And a TF. The voltage controlled oscillator VCO controls the frequency of the output clock CKout based on the temperature compensation control voltage ft.

  In this PLL synthesizer, since the capacitor capacity of the temperature compensation loop filter TF can be reduced, it is provided in the same chip as the PLL synthesizer circuit. However, the PLL loop filter LF is provided outside the chip because of its large capacitor capacity.

  FIG. 3 is a schematic configuration diagram of the voltage controlled oscillator VCO. The voltage controlled oscillator VCO is constituted by an LC oscillation circuit, for example, and the capacitance of the capacitor in the LC oscillation circuit is changed by the control code Code, the control voltage Vt, and the temperature compensation control voltage ft. Thereby, the oscillation frequency is controlled. In the example of FIG. 3, the capacitors in the LC oscillator include a first capacitor C1 whose capacitance value is variably controlled by the frequency control voltage Vt, and a second capacitor C2 whose capacitance value is variably controlled by the temperature compensation control voltage ft. And a third capacitor group C3_1 to C3_n connected or disconnected via a switch by a control code Code. The capacitance value of the third capacitor group is relatively large, whereas the capacitance values of the first and second capacitors C1 and C2 are relatively smaller.

  FIG. 4 is a diagram for explaining the frequency control of the voltage controlled oscillator VCO. FIG. 4A shows frequency control of the voltage controlled oscillator VCO when there is no temperature compensation loop. The control range of the frequency f0 is switched according to the control code Code (001, 010, 011 in the figure). Then, the frequency f0 is variably controlled within the frequency control range set by the control code Code according to the frequency control voltage Vt.

  As shown in FIG. 4A, when the voltage controlled oscillator VCO oscillates at the frequency A, if the temperature rises and changes to the frequency B and falls outside the frequency control range of the control code 010, the control code is Switching from 010 to 011 shifts the frequency control range up by one level. As a result, at the same frequency control voltage Vt, the frequency becomes C and the lock-off may occur due to a large change. In this case, the frequency control voltage Vt is changed by the PLL main loop, controlled to the frequency D, and controlled to lock on again.

  FIG. 4B shows frequency control of the voltage controlled oscillator VCO to which frequency control by the temperature compensation loop is added. The left side of FIG. 4 (B) is the same as FIG. 4 (A) and shows frequency control by the control code and the frequency control voltage Vt. In this figure, it is assumed that the frequency control voltage Vt is desirably controlled between Va and Vb in the figure. The right side of FIG. 4B shows frequency control using the temperature compensation control voltage ft within a certain frequency control range. When oscillating at the frequency A and the temperature rises and the frequency is going to rise, the temperature compensation loop detects the fluctuation of the frequency control voltage Vt, and the temperature compensation control voltage ft detects the capacitor C2 of the oscillator VCO. The capacitance value is variably controlled so that the frequency does not increase due to temperature rise. As a result, the control range of the frequency control voltage Vt is prevented from deviating from the range between Va and Vb.

  As described above, in the PLL synthesizer with temperature compensation shown in FIG. 2, the frequency control of the voltage controlled oscillator VCO is also performed by the temperature compensation control voltage ft in addition to the control code Code and the frequency control voltage Vt. Generally, the time constant of the temperature compensation loop is set larger than that of the main loop. Thereby, it is avoided that the frequency control by the main loop and the frequency control by the temperature compensation loop interfere with each other and compete with each other.

  FIG. 5 is a diagram showing the configuration and signals of the temperature compensation loop in the present embodiment. Each circuit constituting the temperature compensation loop will be described with reference to FIG.

  The comparator includes two comparators CMP1 and CMP2 that compare the frequency control voltage Vt with reference voltages Vref + and Vref−. As shown in (2) of FIG. 5, the output 30 of the comparator becomes the first level (for example, +1) when the frequency control voltage Vt exceeds the high reference voltage Vref +, and becomes the first level when the frequency control voltage Vt exceeds the low reference voltage Vref−. It becomes a level of 2 (broken line in the figure, for example, -1).

  FIG. 6 is a diagram illustrating a circuit example of the digital filter DF. The digital filter DF is a kind of integrator, and includes an amplifier 40 that amplifies the output 30 of the comparator, an adder 41, a delay circuit 42, and an amplifier 43. The delay circuit 42 delays the amplified comparator output 30 by, for example, one cycle of the reference clock R_CLK, and the adder 41 adds to the new comparator output 30 to generate an integrated value. The output 32 of the digital filter DF is an M-bit digital signal, for example.

  FIG. 5 (3) shows an example of the waveform of the output 32 of the digital filter. An integrated value synchronized with the reference clock R_CLK is output as +1 of the comparator output 30 as the M-bit output 32 of the digital filter DF. As described above, the digital filter 32 integrates the comparator output 30, so that the response to the change of the comparator output 30 can be delayed, and the time constant of the temperature compensation loop can be increased. That is, the digital filter 32 realizes the function of delaying the response of the temperature filter TF in the temperature compensation loop in FIG.

  FIG. 7 is a diagram illustrating a circuit example of the ΔΣ modulator. The delta-sigma modulators 10 and 12 provided in the temperature compensation loop of this embodiment up-sample the M-bit output 32 of the digital filter DF at a frequency dCLK higher than the clock R_CLK of the digital filter, and have fewer bits than M bits. A number of N-bit high frequency digital signals 34 are converted. The high-frequency digital signal 34 is a pseudo-random digital signal, and is equal to the value of the digital signal 32 when averaged on the time axis.

  By converting to a high-frequency digital signal, the cutoff frequency of the temperature compensation loop filter in the subsequent stage can be set high, and the capacitance value of the capacitor can be reduced. In addition, noise shaping is performed by converting the pseudo random digital signal, and quantization noise in a low frequency band can be reduced.

  FIG. 7 shows a second-order ΔΣ modulator as an example of the ΔΣ modulator. This modulator has an input register 50 for sampling the M-bit digital signal 32 with the clock dCLK, an adder 51, and a register 52 for latching the added value X + Y of the adder with the clock dCLK. The latched value is fed back to the adder 51. With this configuration, the carry signal C (1 bit) of the adder 51 is generated. Further, the modulator has an adder 53 that adds the values latched by the register 52 and a register 54 that latches the added value X + Y of the adder 53 with the clock dCLK. The value latched by the register 54 is added. Is fed back to the device 53. Further, the carry signal C of the adder 53 is obtained by a differentiation circuit 57 comprising a register 55 and a subtractor 56, the adder 58 adds the derivative value and the carry signal C of the adder 51, and N A digital output 34 of 2 bits (2 bits) is output.

  This digital output 34 is an N-bit pseudo-random digital signal having a higher frequency than the M-bit digital input 32 and fewer than M bits. As shown in (4) of FIG. 5, the ΔΣ modulator is a circuit that converts the digital input signal 32 into a digital signal 34 having a higher frequency and fewer bits. In FIG. 5 (4), 2 bits (4 (Quantum dot) digital signal. The digital output signal 34 is shown changing at a higher frequency than the digital input signal 32. That is, the high-frequency and low-bit digital output signal 34 is obtained by modulating the low-frequency and high-bit digital input signal 32 at a high frequency.

  FIG. 7 shows an example in which the high frequency clock dCLK for upsampling of the ΔΣ modulator is generated by the frequency divider DIV1 in the PLL main loop. The output clock CKout of the VCO is divided by the two dividers 46 and 47 in the divider DIV1. The clock dCLK output from the previous frequency divider 46 is used as the sampling clock dCLK of the ΔΣ modulator. The clock dCLK has a higher frequency than the synchronous clock R_CLK of the digital filter DF.

  FIG. 8 is a diagram illustrating a circuit example of the charge pump CPt and the temperature compensation loop filter TF. The charge pump CPt in FIG. 8 is a circuit corresponding to 1-bit input, and includes current sources I1 and I2 and switches SW1 and SW2. When the input 34 is “1”, the switch SW1 is conducted and the current I1 is supplied. When the input 34 is “0”, the switch SW2 is conducted and the current I2 is drawn. That is, a positive current is generated when the input is “1”, and a negative current is generated when the input is “0”.

  The simplest configuration of the temperature compensation loop filter TF is a single capacitor that stores the current. However, the loop filter TF shown in FIG. 8 includes resistors R10, R11 and capacitors C10, C11, C12. As shown in FIG. 8, when the input is “1”, the charge pump CPt generates a positive current and the output voltage ft rises. When the input is “0”, the charge pump CPt generates a negative current and outputs it. Voltage ft drops. The loop filter TF is a kind of low-pass filter, and cuts a high-frequency component of the current generated by the charge pump. Accordingly, the smaller the total capacitance value of the capacitors C10, C11, C12, the higher the cutoff frequency.

  FIG. 9 is a diagram illustrating another circuit example of the charge pump CPt and the temperature compensation loop filter TF. The charge pump CPt in FIG. 9 is a circuit corresponding to 2-bit input. When the input 34 is “1”, the switch SW1 is conducted. When the input 34 is “2”, the switches SW1 and SW3 are conducted. When the input 34 is “0”, none of the switches are conducted. When SW34 is “−1”, the switch SW2 becomes conductive.

  Accordingly, the charge pump CPt has a positive current 2 × I1 if the input is “2”, a positive current I1 if the input is “1”, no current if the input is “0”, and negative if the input is “−1”. Each current I1 is output.

  The temperature compensation loop filter TF in FIG. 9 is composed of one capacitor. Of course, the temperature compensation loop filter TF shown in FIG. 8 may be used. Also in this case, the cutoff frequency increases as the capacitance value of the capacitor decreases.

  Since the digital output 32 of the digital filter DF is converted into a high-frequency digital signal 34 by using the ΔΣ modulators 10 and 12, the cutoff frequency of the temperature compensation loop filter TF shown in FIGS. It can be set higher than the filter. That is, the high frequency component of the digital output 32 of the digital filter DF to be cut is shifted to a higher frequency band by upsampling by the ΔΣ modulator. As a result, the cutoff frequency of the temperature compensation loop filter TF can be increased, and the capacitance value of the temperature compensation loop filter TF can be reduced. This means that the temperature compensation loop filter TF can be easily provided in the same chip as the PLL synthesizer.

  FIG. 10 is a diagram for explaining the frequency characteristics of the temperature compensation loop filter TF. The solid line is the characteristic of the conventional temperature compensation loop filter. On the other hand, the broken line is the characteristic of the temperature compensation loop filter TF in the present embodiment. It can be seen that the broken line has a higher cutoff frequency.

  As described above, according to the first embodiment, the comparison signal of the comparator is integrated by the digital filter DF and converted into the M-bit digital output signal 32, so that the response of the temperature compensation filter is delayed. The time constant can be increased. Further, the M-bit digital output signal 32 of the digital filter is up-sampled by the ΔΣ modulator and converted into an N (<M) -bit digital output signal 34. As a result, the higher frequency digital output signal 34 is converted, so that the cutoff frequency of the temperature compensation loop filter TF, which is an analog filter, can be set higher, and the capacitor of the temperature compensation loop filter TF is correspondingly increased. By reducing the capacitance value, the chip area can be reduced.

[Second Embodiment]
By reducing the capacitance value of the temperature compensation loop filter TF, it is possible to reduce the charging current during the sleep mode, and it is possible to shorten the time until the PLL synthesizer lock-on when returning from the sleep mode. This point will be described below.

  FIG. 11 is a diagram illustrating the temperature compensation loop filter. FIG. 11A shows the OTA, the temperature compensation loop filter TF, and the voltage controlled oscillator VCO in the temperature compensation loop shown in FIG. OTA is a combination of the comparator CMP and the charge pump CPt, and the temperature compensation loop filter TF is a circuit having the capacitors shown in FIGS.

  As shown in FIG. 11B, when the PLL synthesizer is built in the communication device, the sleep mode is controlled between communication time slots. In sleep mode, the operation of the PLL synthesizer stops and output clock generation stops. On the other hand, the loop filter TF cannot output the frequency control voltage ft during normal operation unless a certain amount of charge is accumulated in the capacitor. Therefore, it is necessary to provide a precharge circuit 60 to supply current to the capacitor in the loop filter TF even during the sleep mode.

  FIG. 12 is a diagram for explaining the operation when the PLL synthesizer returns. FIG. 12A shows an operation at the time of starting or returning from the sleep mode. At start-up or return, the capacitor in the loop filter TF is precharged from the precharge circuit 60 (time t1), and then frequency control is performed by the main loop and temperature compensation loop of the PLL synthesizer (time t2). In that case, the time t1 + t2 may exceed the time limit TLimit until the PLL locks up.

  Therefore, as shown in FIG. 12B, by continuously supplying the precharge current from the precharge circuit 60 even during the sleep mode, only the time t2 until the lock by the frequency control of the PLL synthesizer is achieved after the return. It becomes necessary, and it becomes possible to be locked by the time limit TLimit until lock-up. However, in this case, it is necessary to supply the precharge current even during the sleep mode, which is contrary to the power saving of the sleep mode.

  FIG. 13 is a configuration diagram of a temperature compensation loop of the PLL synthesizer according to the second embodiment. The temperature compensation loop configuration is stored in the memory 62 for storing the digital output 32 of the digital filter DF when entering the sleep state and the memory 62 when returning from the sleep state in addition to the temperature compensation loop of FIG. And a precharge circuit 60 for precharging a capacitor in the temperature compensation loop filter TF in accordance with the value of the digital output 32.

  That is, when shifting to the sleep state, the capacitor in the temperature compensation loop filter TF is charged with a charge corresponding to the value of the M-bit digital output 32 of the digital filter DF. Therefore, when shifting to the sleep state, the digital output 32 is stored in the memory 62. The memory 62 is a nonvolatile memory in which stored data is not lost even in the sleep state. During the sleep state, the precharge current is not supplied from the precharge circuit 60 to the loop filter TF.

  When returning from the sleep mode, the precharge circuit 60 reads the digital output 32 stored in the memory 62 and charges the capacitor in the loop filter TF to a voltage corresponding to the digital output value. Since the capacitance value of the capacitor in the loop filter TF is configured to be small, the time required for this precharge is short.

  FIG. 14 is a diagram illustrating a return operation from the sleep state of the temperature compensation loop of the PLL synthesizer according to the second embodiment. As described with reference to FIG. 13, in the second embodiment, the precharge current is not supplied to the temperature compensation loop filter TF in the sleep state. Instead, when returning from the sleep state, the precharge circuit 60 supplies a charge amount corresponding to the digital output value stored in the memory 62 to the capacitor of the temperature compensation loop filter TF. However, since the capacitance of the capacitor is small, the precharge time t1 can be shortened as shown in FIG.

  As a result, the sum of this short precharge time t1 and the subsequent time t2 until lock-on by frequency control by the PLL can be made less than the limit time TLimit until lock-on.

  As described above, according to the second embodiment, consumption of the precharge current during the sleep period is eliminated, and power saving can be achieved.

PD: Phase comparator CPm: Main loop charge pump
LF: PLL loop filter VCO: Voltage controlled oscillator
Vt: Frequency control voltage DIV1: Divider
CKout: Output clock CMP: Comparator
DF: Digital filter 10, 12: ΔΣ modulator
CPt: Temperature compensation loop charge pump
TF: Temperature compensation loop filter ft: Temperature compensation control voltage

Claims (4)

A phase comparator that compares the phase of the output clock with the reference clock;
A PLL loop filter that generates a frequency control voltage according to a phase comparison result of the phase comparator;
A voltage controlled oscillator for generating the output clock having a frequency controlled according to the frequency control voltage;
A comparator that outputs a comparison signal having first and second levels when the frequency control voltage is out of a control voltage range;
A digital filter that integrates the comparison signal in synchronization with a first control clock to generate an M-bit first digital signal;
The first digital signal is input, and is synchronized with a second control clock having a frequency higher than that of the first control clock, and is a second digital signal having N bits less than the M bits. A ΔΣ modulator for generating a second digital signal corresponding to the signal;
A temperature compensated charge pump for converting the second digital signal into a current signal;
A capacitor charged and discharged by the current signal, and a temperature compensation loop filter for converting the current signal into a temperature compensation control voltage,
The voltage controlled oscillator is a PLL synthesizer that controls the frequency of the output clock based on the temperature compensation control voltage. In claim 1,
The voltage-controlled oscillator is a PLL synthesizer that suppresses the frequency of the output clock from being out of a predetermined control frequency range based on the temperature compensation control voltage. In claim 1 or 2,
A memory for storing a first digital signal generated by the digital filter when the sleep mode is entered;
A precharge circuit that supplies a charge amount corresponding to the first digital signal stored in the memory to the capacitor in the temperature compensation loop filter when returning from the sleep mode;
The precharge circuit is a PLL synthesizer that does not supply charge to a capacitor in the temperature compensation loop filter during the sleep mode. In any one of Claims 1-3,
A PLL synthesizer formed in the same chip except for the PLL loop filter.

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