JP2005259896A - Semiconductor substrate and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-definition semiconductor substrate where the crystal defect of a single crystal semiconductor layer caused by the difference of a grating constant and a coefficient of thermal expansion is reduced. <P>SOLUTION: After forming a large number of protrusion 2 in the state of micro-tablelands on the upper surface of a single crystal semiconductor substrate 1, a buffer layer 3 is laminated on the upper surface of the single crystal semiconductor layer, and a single crystal semiconductor layer 4 of a kind different from the single crystal semiconductor layer is laminated on the buffer layer for manufacturing the semiconductor substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor substrate formed by laminating a single crystal semiconductor layer of a different type from this substrate on a single crystal semiconductor substrate by vapor phase growth or the like in order to make a semiconductor light emitting element or an electronic device, and a method for manufacturing the same.

A semiconductor substrate formed by laminating a single crystal semiconductor layer of a different type from this substrate on a single crystal semiconductor substrate by vapor phase growth or the like is usually silicon (Si), sapphire (Al ₂ O ₃ ), gallium arsenide (GaAs). On a single crystal semiconductor substrate such as gallium nitride (GaN) or silicon carbide (SiC).

However, the semiconductor substrate is a high-quality semiconductor due to crystal defects in the single crystal semiconductor layer caused by a difference in lattice constant and thermal expansion coefficient between the single crystal semiconductor substrate and the single crystal semiconductor layer which are different materials. It is difficult to provide a substrate.
This tendency is particularly noticeable in GaN, SiC, etc., which are said to be wide band gap materials, and crystal defects caused by differences in lattice constants and thermal expansion coefficients cause element deterioration and current leakage when formed into devices. Yes.

  Conventionally, in order to solve the above-described problems, a buffer layer 32 made of aluminum nitride (AlN) crystal is laminated on a single crystal semiconductor substrate 31 made of Si by vapor phase growth as shown in FIG. A semiconductor substrate is known in which a single crystal semiconductor layer 33 made of GaN different from the single crystal semiconductor substrate 31 is stacked on the layer 32 by vapor phase growth.

However, since the semiconductor substrate basically takes over the information of the underlying single crystal semiconductor substrate and the interface, it is difficult to reduce the influence particularly when a high-density crystal defect occurs.
Further, since the buffer layer becomes a dopant, it may be difficult to control the carrier concentration.
JP-A-2-275682

  An object of the present invention is to provide a high-quality semiconductor substrate in which crystal defects of a single crystal semiconductor layer caused by a difference between a lattice constant and a thermal expansion coefficient are reduced, and a manufacturing method thereof.

  According to the first method of manufacturing a semiconductor substrate of the present invention, when a semiconductor substrate is manufactured by stacking a single crystal semiconductor layer of a different type from the substrate on the single crystal semiconductor substrate, a fine plateau is formed on the upper surface of the single crystal semiconductor substrate. After forming a large number of protrusions, a buffer layer is stacked on the upper surface of the single crystal semiconductor substrate so as to fill the gaps between the protrusions, and then a single crystal semiconductor of a different type from the single crystal semiconductor substrate is formed on the buffer layer. It is characterized by laminating layers.

  The second method for manufacturing a semiconductor substrate is to manufacture a semiconductor substrate by stacking a single crystal semiconductor layer of a different type from the substrate on the semiconductor single crystal substrate. After forming the protrusions, a buffer layer is stacked on the upper surface of the single crystal semiconductor substrate without filling the gaps between the protrusions, and then a single crystal semiconductor layer of a different type from the single crystal semiconductor substrate is stacked on the buffer layer. It is characterized by that.

  According to a third method for manufacturing a semiconductor substrate, in the first or second method, after the single crystal semiconductor layer is stacked, the single crystal semiconductor layer is separated from the single crystal semiconductor substrate.

  On the other hand, the semiconductor substrate is manufactured by any one of the first to third methods for manufacturing a semiconductor substrate.

  According to the first semiconductor substrate and the method for manufacturing the same, even if distortion due to the difference in lattice constant and thermal expansion coefficient between the single crystal semiconductor substrate and the single crystal semiconductor layer occurs, it is formed on the upper surface of the single crystal semiconductor substrate. Concentrated on the interface between the large number of fine plate-like (mesa-shaped) protrusions and the buffer layer, and the upper surface of the single crystal semiconductor substrate on which the many fine plate-like protrusions are formed is broken crystalline. Therefore, crystal defects in the single crystal semiconductor layer can be reduced, and a high-quality semiconductor substrate can be obtained.

  According to the second semiconductor substrate and the method for manufacturing the same, even if distortion occurs due to a difference in lattice constant and thermal expansion coefficient between the single crystal semiconductor substrate and the single crystal semiconductor layer, it is formed on the upper surface of the single crystal semiconductor substrate. The upper surface of the single crystal semiconductor substrate on which a large number of fine plate-like protrusions and a plurality of fine plate-like protrusions are concentrated is crystallized more than the first and method. Since stress concentration is thereby eliminated, crystal defects in the single crystal semiconductor layer can be remarkably reduced as compared with the first and method, and a higher quality semiconductor substrate can be obtained.

  In addition, according to the third semiconductor substrate and the manufacturing method thereof, in addition to the effects of the first or second substrate and method, there is no difference in lattice constant and thermal expansion coefficient from the single crystal semiconductor substrate. Crystal defects that are reintroduced in the cooling process can be particularly suppressed in the thermal cycle (for example, the sacrificial oxidation or alloy process after electrode formation) at the time of fabrication.

As the single crystal semiconductor substrate, a substrate made of Si, GaAs, gallium phosphide (GaP), indium phosphide (InP), SiC, GaN, sapphire, or other semiconductors is used.
Buffer layers and single crystal semiconductor layers include SiC, GaN, nitrides such as aluminum nitride (AlN), oxides such as GaAs, InP, germanium (Ge), and zinc oxide (ZnO), diamond thin films, gallium aluminum A ternary system such as arsenic (GaAlAs), a quaternary system such as gallium arsenide aluminum phosphorus (GaAsAlP), or other semiconductors different from a single crystal semiconductor substrate is used.
The buffer layer may be single crystal, but there is no particular problem even if it is amorphous or polycrystalline.
Note that the single crystal semiconductor substrate, the buffer layer, and the single crystal semiconductor layer are not limited to those described above as long as they meet the purpose. For example, from a metal such as quartz, nickel (Ni), or platinum (Pt) It does not matter.

The area of one of the fine plate-like protrusions formed on the upper surface of the single crystal semiconductor substrate is preferably 0.15 to 7E-19 mm ² , more preferably 6E-5 to 7E-13 mm ² .
When the area of one protrusion is less than 7E-19 mm ² or exceeds 0.15 mm ² , the defect reduction effect is lost.
In addition, the pitch and the depth of the gap between the adjacent many protrusions in the form of a fine plateau are preferably 0.001 to 500 μm, more preferably 50 to 0.1 μm.
When the pitch and the depth of the gap between adjacent pitches are less than 0.001 μm or more than 500 μm, the defect reduction effect is lost.
Furthermore, the inclination angle of the side surface of the protrusion is preferably 30 to 150 °, more preferably 50 to 70 °.
If the inclination angle of the side surface of the protrusion is less than 30 ° or exceeds 150 °, the defect reduction effect is lost.

To form a large number of fine plateau protrusions on the top surface of a single crystal semiconductor substrate, a fine mask pattern is cut on the top surface of the single crystal semiconductor substrate and then reactive ion etching (RIE) is performed. Or by an anisotropic (anisotropic) etching, a combination with chemical mechanical polishing (CMP), etc., or by island growth using epitaxial growth, anodizing, etc. Good.
Note that mechanical polishing may be used as long as the cleanliness and uniformity of the upper surface of the single crystal semiconductor substrate can be maintained.

  For vapor phase growth of buffer layer and single crystal semiconductor layer, MOCVD (Metal Organic Chemical Vapor Deposition) method, MBE (Molecular Bean Epitaxy) method, LPE (Liquid Phase Epitaxy) method, sublimation method (modified Lelv method), etc. The method is used.

The single crystal semiconductor layer is separated from the single crystal semiconductor substrate by chemically or mechanically removing the single crystal semiconductor substrate.
Fluorine nitric acid and other etchants are used to remove the chemical single crystal semiconductor substrate, and a polishing machine or the like is used to remove the mechanical single crystal semiconductor substrate.

  FIG. 1 is a conceptual diagram of a main part showing a first embodiment of a semiconductor substrate according to the present invention.

In the figure, reference numeral 1 denotes a single crystal semiconductor substrate made of (100) Si and having a thickness of 645 μm. On the upper surface of the single crystal semiconductor substrate 1, a number of fine plate-like or island-like projections 2 are formed.
The area of one of the fine plate-like protrusions 2 is 1E-5 mm ² , and the number of fine plate-like protrusions 2 has a pitch of 1 μm and a gap depth of 1 μm, and The inclination angle of the side surface is 60 °.
On the upper surface of the single crystal semiconductor substrate 1, a buffer layer 3 made of polycrystalline SiC and having a thickness of 0.1 μm is laminated so as to fill the gaps between the protrusions 2. A single crystal semiconductor layer 4 made of crystalline SiC and having a thickness of 20 μm is stacked.

In order to manufacture the semiconductor substrate, first, a fine mask pattern is cut on the upper surface of the (100) Si substrate having a thickness of 645 μm, and a number of fine plate-like protrusions are subsequently formed on the upper surface of the (100) Si substrate by the RIE method. Formed.
Next, an SiC buffer layer was laminated on the upper surface of the (100) Si substrate by MOCVD so as to fill the gaps between the protrusions, and then an SiC single crystal semiconductor layer was laminated.
The film forming conditions of the SiC buffer layer and the SiC single crystal semiconductor layer according to this example are as follows.
1. The Si substrate is annealed in a H ₂ atmosphere at 1000 ° C. to remove the natural oxide film.
2. The substrate temperature is set to 400 to 600 ° C., and the SiC buffer layer is formed to a thickness of about 50 to 100 nm. In this example, monomethylsilane (CH ₃ SiH ₃ ) was used as a raw material.
3. Next, the substrate temperature is set to 800 to 1000 ° C., and a SiC single crystal layer is formed to a thickness of 5 μm or more. In this example, monomethylsilane was used as a raw material.
Note that although the (100) plane is given as the single crystal semiconductor substrate surface, it may be another plane such as a (111) plane.
Further, the flatness of the SiC single crystal semiconductor layer could be controlled by the growth conditions of the SiC buffer layer grown immediately before.

  When the dislocation density of the above-described semiconductor substrate was examined, it became as shown by a straight line A in FIG. 2, and surface defects, twins, stacking faults, and the like were found in a conventional semiconductor substrate ((100) Si shown by a straight line B in FIG. Compared to those obtained by forming a SiC buffer layer and a SiC semiconductor layer on a mirror wafer), it was confirmed that the number was reduced by one digit or more.

  FIG. 3 is a conceptual diagram of a main part showing a second embodiment of a semiconductor substrate according to the present invention.

In the semiconductor plate of Example 1, the buffer layer 3 was formed on the upper surface of the single crystal semiconductor substrate 1 so as to fill the gap between the protrusions 2, whereas the buffer layer 3 ′ was formed on the protrusion 2. It is formed on the upper surface of the single crystal semiconductor substrate 1 without filling the gap between them, and is parallel to the upper surface of the (100) Si substrate in order to grow the buffer layer 3 ′ without filling the gap between the protrusions 2. The film was formed by the MOCVD method under the following conditions that selectively promote growth in various directions.
The deposition conditions for the SiC buffer layer were basically the same as in Example 1, but in this example, the furnace pressure was 10% lower than in Example 1. This encouraged growth in a direction parallel to the top surface of the Si substrate.
Since other configurations are the same as those in the first embodiment, the same reference numerals are given to the same components and the description thereof is omitted, and other manufacturing methods are the same as those in the first embodiment. The description is omitted.

  When the dislocation density of the above-described semiconductor substrate was examined, it was as shown by a straight line C in FIG. 2, and it was confirmed that the dislocation density was reduced by two orders of magnitude or more compared to the conventional one.

  FIG. 4 is a conceptual diagram of a main part showing a third embodiment of a semiconductor substrate according to the present invention.

  This semiconductor substrate is the same as that of Example 1 and Example 2 described above from the single crystal semiconductor substrate 1, buffer layers 3, 3 'and single crystal semiconductor layer 4 having a large number of fine trapezoidal protrusions 2 on the upper surface. A buffer layer 3 ″ having a thickness of 0.1 μm made of polycrystalline SiC and a single crystal semiconductor having a thickness of 20 μm made of single crystal SiC stacked on the buffer layer 3 ″. It has a two-layer structure with the layer 4.

  In order to manufacture the semiconductor substrate, the single crystal semiconductor layer 4 and the buffer layer 3 (3 ′) of the semiconductor substrate of Example 1 or Example 2 are separated from the single crystal semiconductor substrate 1 by using single nitric acid. The crystalline semiconductor substrate 1 is chemically removed.

When the dislocation density of the semiconductor substrate was examined, it was almost the same as that of Example 2.
It was also confirmed that defects introduced again during the cooling process can be suppressed in the thermal cycle during device fabrication, and can be reduced by an order of magnitude or more from the conventional one.

It is a conceptual diagram of the principal part which shows Example 1 of the semiconductor substrate which concerns on this invention. FIG. 3 is an explanatory diagram showing the dislocation density of the semiconductor substrate of Example 1. It is a conceptual diagram of the principal part which shows Example 2 of the semiconductor substrate which concerns on this invention. It is a conceptual diagram of the principal part which shows Example 3 of the semiconductor substrate which concerns on this invention. It is a conceptual diagram of the principal part which shows the conventional semiconductor substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Single crystal semiconductor substrate 2 Protrusion 3 Buffer layer 3 'Buffer layer 3 "Buffer layer 4 Single crystal semiconductor layer

Claims (4)

  When a semiconductor substrate is manufactured by stacking a single crystal semiconductor layer of a different type from the substrate on the single crystal semiconductor substrate, a large number of fine plateau-shaped protrusions are formed on the upper surface of the single crystal semiconductor substrate, and then the single crystal semiconductor A buffer layer is stacked on the upper surface of the substrate so as to fill a gap between the protrusions, and then a single crystal semiconductor layer of a different type from the single crystal semiconductor substrate is stacked on the buffer layer. Method.   When a semiconductor substrate is manufactured by stacking a single crystal semiconductor layer of a different type from the substrate on the single crystal semiconductor substrate, a large number of fine plateau-shaped protrusions are formed on the upper surface of the single crystal semiconductor substrate, and then the single crystal semiconductor A method of manufacturing a semiconductor substrate, comprising: laminating a buffer layer on an upper surface of the substrate without filling a gap between protrusions; and then laminating a single crystal semiconductor layer of a different type from the single crystal semiconductor substrate on the buffer layer. .   3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the single crystal semiconductor layer is separated from the single crystal semiconductor substrate after the single crystal semiconductor layer is stacked. A semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 1.

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