JP2005259772A - Laminated ceramic capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic capacitor in which generations of a defective withstand voltage and a defective short circuit between an internal electrode and a terminal electrode is reduced, and which can be increased in electrostatic capacitance by increasing the area of the internal electrode to the maximum. <P>SOLUTION: The internal electrode is bent at a corner facing a connecting part with the terminal electrode, and a laminate has a curved surface at its ridge. The radius of the curvature Rd of the corner of the internal electrode, the radius of the curvature Rs of the ridge of the laminate, and a gap G in a straight line between the internal electrode and a dielectric layer are adjusted to meet a relation of Rs≤Rd+G. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a multilayer ceramic capacitor.

The multilayer ceramic capacitor is composed of a ceramic laminate in which a plurality of internal electrodes and dielectric layers are alternately laminated, and one end of the internal electrode extends, and terminal electrodes formed on both ends of the multilayer chip body respectively A plurality of them are electrically connected alternately. Except for the connection with the terminal electrode, a predetermined gap is provided on the outer peripheral edge of the internal electrode and the dielectric layer, and the ridgeline part (peripheral part and corner part) of the ceramic body and the corner part of the internal electrode have an arc shape. A multilayer ceramic capacitor having a rounded shape is disclosed in the following document.
JP 2000-126404 A JP 2000-114097 A JP-A-9-129416 Japanese Utility Model Publication No. 4-92624 Japanese Utility Model Publication No. 58-56431

  In recent years, multilayer ceramic capacitors have many needs for miniaturization and increased capacitance. Therefore, the number of dielectric layers is increased by reducing the thickness of each dielectric layer and the thickness of the protective layer as much as possible. Furthermore, the area of the internal electrode is increased as much as possible to cope with the increase in capacitance. On the other hand, in the manufacturing process of a chip capacitor, in order to prevent cracks, chips, cracks, and the like due to collisions between stacked bodies, it is known to round the cross-section arc shape at the ridge line portion of the stacked body.

  However, when the roundness applied to the laminated body is increased, the distance between the terminal electrode and the internal electrode is reduced at the corner portion of the internal electrode, which causes a breakdown voltage failure or a short-circuit failure. In addition, since the current concentrates at the corners of the internal electrodes, a withstand voltage failure tends to occur particularly at the corners of the internal electrodes.

  In order to solve the above-mentioned problem, a method of providing an arcuate roundness at the corner of the internal electrode is taken, but if the roundness at the corner of the internal electrode is too large, the area of the internal electrode is reduced and a large capacitance is generated. I can't get it.

  On the other hand, a constant gap is provided between the internal electrode connected to the terminal electrode and the opposing terminal electrode. However, if this gap is too small, a withstand voltage failure or a short-circuit failure occurs, and conversely, the gap is large. If it is too large, the area of the internal electrode is reduced and a large capacitance cannot be obtained.

  Therefore, the present invention provides a multilayer ceramic capacitor that has less withstand voltage failure and short-circuit failure between the internal electrode and the terminal electrode, and can cope with an increase in capacitance by maximizing the internal electrode area. Objective.

  In order to solve the above problems, a multilayer ceramic capacitor of the present invention includes a multilayer body in which a plurality of dielectric layers and internal electrodes are alternately stacked, and a pair of terminal electrodes connected to the internal electrodes at both ends of the multilayer body. The internal electrode is curved at the corner facing the connection with the terminal electrode, and the laminate has a curved surface at the ridgeline. Further, when the radius of curvature of the corner portion of the internal electrode is Rd, the radius of curvature of the ridge portion of the multilayer body is Rs, and the gap in the linear portion between the internal electrode and the dielectric layer is G, Rs ≦ Rd + G (Rd is 1 to 25% of the short side of the internal electrode).

  Another multilayer ceramic capacitor according to the present invention is characterized in that the gap between the linear portions of the internal electrode and the dielectric layer is not less than twice the thickness per dielectric layer and not more than 5% of the long side of the laminate. It is said.

  According to the multilayer ceramic capacitor of the present invention, the withstand voltage failure and short-circuit failure of the multilayer ceramic capacitor can be reduced, and the internal electrode area can be increased as much as possible to increase the capacitance.

The multilayer ceramic capacitor of the present invention will be described in detail below with reference to the drawings.
1 and 2 are plan sectional views of a multilayer body portion of a multilayer ceramic capacitor according to an embodiment of the present invention, FIG. 3 is a longitudinal sectional view of the multilayer ceramic capacitor, and FIG. 4 is a partially broken view of the multilayer ceramic capacitor. It is a perspective view.

  The laminate 1 is configured by laminating a plurality of dielectric layers 2 and 2 'made of a dielectric ceramic material mainly composed of barium titanate. The first internal electrodes 3 and the second internal electrodes 4 are alternately arranged between the layers of the laminate. The first and second internal electrodes 3 and 4 are made of, for example, a base metal material such as Ni or a noble metal material such as Pd or an Ag—Pd alloy.

A first terminal electrode 5 and a second terminal electrode 6 are formed on both end faces of the laminate 1.
The first internal electrode 3 is formed on the dielectric layer 2 and has gaps G1, G2, and G3 in addition to the connection portion with the terminal electrode 5, respectively. The second internal electrode 4 is disposed between the dielectric layer on which the first internal electrode 3 is formed and the adjacent layer. The second internal electrode 4 is formed on the dielectric layer 2 ′, and has gaps G 4, G 5, G 6 in addition to the connection portion with the terminal electrode 6.

  The first internal electrode 3 has a roundness with a radius of curvature Rd at the corner facing the first terminal electrode 5. Further, the second internal electrode 4 has a roundness with a radius of curvature Rd at a corner facing the second terminal electrode 6. And the ridgeline part (corner | corner part, corner part) of the laminated body 1 is equipped with the roundness of the curvature radius Rs in order to prevent a crack, a chip, and a crack.

  The terminal electrodes 5 and 6 are composed of a base conductor film and a plating layer. The first terminal electrode 5 is connected to the plurality of first internal electrodes 3 and is formed from one end face of the multilayer body 1, that is, the left end face, from the end portions of the four faces adjacent to the end face. Has been.

  The second terminal electrode 6 is connected to the plurality of second inner electrodes 4 and is formed from the other end face of the multilayer body 1, that is, the end face of the four faces adjacent to the end face, centering on the right end face. Has been.

  In the present embodiment, the radius of curvature at the ridge portion of the laminate is Rs, the radius of curvature provided at the internal electrode is Rd, and the gap at the linear portion between the internal electrode and the dielectric layer is G (G1, G2, G3, G4, G5, G6), Rs ≦ Rd + G for all G, and the radius of curvature Rd of the corner portions of the internal electrodes 3 and 4 is 1 to 25% of the internal electrode short side Wd.

  Furthermore, in this embodiment, when the gap in the straight line portion between the internal electrode and the dielectric layer is G (G1, G2, G3, G4, G5, G6), all G are thicknesses per dielectric layer. It is at least twice t and 5% or less of the ceramic body long side L.

  The multilayer ceramic capacitor 10 having the above configuration is manufactured as follows.

  First, two types of ceramic green sheets made of a dielectric material are prepared. One ceramic green sheet is a green sheet serving as the dielectric layers 2a and 2z of the protective layer, and the other ceramic green sheet is a ceramic green sheet serving as the dielectric layers 2 and 2 'sandwiched between the protective layers.

  Here, in each ceramic green sheet, element regions to be a plurality of multilayer ceramic capacitors are arranged vertically and horizontally. One element region will be described.

  First, except for the ceramic green sheets that become the dielectric layers 2a and 2z of the protective layer, the conductor film that becomes the first internal electrode 3 or the second film on the green sheets that become the dielectric layers 2 and 2 ' A conductor film to be the internal electrode 4 is formed by printing a conductive paste having metal powder, for example. Here, the internal electrodes 3 and 4 are printed in the green sheet surface with a gap smaller than the area of the green sheet. Further, the internal electrode 3 is printed by rounding at a corner portion that is not connected to the terminal electrode. Similarly, the second internal electrode 4 is printed by forming a roundness at a corner portion that is not connected to the terminal electrode.

  Next, green sheets on which the first and second internal electrodes 3 and 4 are printed are sequentially stacked alternately. That is, a green sheet having a dielectric layer 2z serving as a protective layer is used on the lowermost surface, and a conductive film serving as the second internal electrode 4 is formed thereon, and further, the first internal electrode 3 and The green sheets on which the conductive films to be formed are alternately stacked, and the green sheet of the dielectric layer 2a serving as the protective layer is stacked on the uppermost surface and pressure-bonded.

  Next, this green sheet laminate is cut into a predetermined dimension according to a predetermined element region to form an unfired chip-like laminate that becomes a laminate.

  Next, this unfired chip-shaped laminate is fired at a predetermined atmosphere and temperature. As a result, the green sheets, the protective layers 2a and 2z, and the internal electrodes 3 and 4 serving as the dielectric layers constituting the unfired chip-like laminate are fired to form an integrally sintered laminate.

  Thereafter, the fired integral sintered laminate is subjected to barrel polishing. Thereby, the ridge line part of the laminated body 1 becomes a curved surface.

  Next, the terminal electrode 5 is formed on the end surface where the first internal electrode of the laminate 1 is exposed, and the terminal electrode 6 is formed on the end surface where the second internal electrode 4 is exposed. Specifically, the end surface portion of the laminated body 1 is immersed (dipped) in a conductive paste tank of Ag, Ag—Pd alloy, Cu or the like, and the conductive paste is applied in the vicinity of the end surface of the laminated body 1. Then, the applied conductive paste is baked to form a base conductor film, and a plating layer made of a material such as Ni, Sn, or Sn—Pb alloy is formed on the surface thereof.

  Although the present embodiment has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Hereinafter, the present invention will be described based on further detailed examples, but the present invention is not limited to these examples.

(Example 1)
A multilayer ceramic capacitor having a 2012 shape (2.00 × 1.25 × 1.25 mm) is manufactured, the dielectric layer thickness is 2.5 μm, and all gaps G (G1, G1, G2, G3, G4, G5, G6) are set to 10 μm, the curvature radius Rd of the internal electrode is set to 200 μm, and a sample in which the curvature radius Rs of the laminated body is changed to 50 to 230 μm is manufactured. The capacitance was examined.

  Specifically, a ceramic powder mainly composed of barium titanate and a firing aid, a dispersing agent, a binder, etc. are added to prepare a dielectric paste, and a ceramic green sheet is prepared by a normal sheet manufacturing method using this. An internal electrode (Ni paste) was formed on this green sheet by a screen printing method. 300 layers of ceramic green sheets on which internal electrodes were formed were laminated, thermocompression bonded, and cut to obtain a chip-shaped laminated body in an unfired state. Here, green sheets on which no internal electrode was formed as a protective layer were stacked above and below in the stacking direction.

  Next, this unfired chip-like laminate was degreased at 300 ° C. for 10 hours, and then integrally fired at 1100 to 1400 ° C. in a reducing atmosphere.

  And the barrel grinding | polishing process was performed so that the ridgeline part of this sintered laminated body might become the curvature radius shown in Table 1. Thereafter, the terminal electrode (Cu paste) was printed and baked on the end face portion of the laminate, and Ni and Sn plating were deposited by a normal electrolytic plating method.

表１より、積層体の稜線部分における曲率半径Ｒｓが、内部電極に設けた曲率半径Ｒｄと、内部電極と誘電体層との直線部分のギャップＧの合計（２１０μｍ）以下の場合には、ショート不良及び耐電圧不良は発生しなかった。しかし、２１０μｍを超えるとこれらの不良が発生した。

From Table 1, when the radius of curvature Rs at the ridge portion of the laminate is less than the sum (210 μm) of the radius of curvature Rd provided on the internal electrode and the gap G of the linear portion between the internal electrode and the dielectric layer, short There was no failure or withstand voltage failure. However, these defects occurred when the thickness exceeded 210 μm.

  Next, the dielectric layer thickness is 2.5 μm, all the gaps G (G1, G2, G3, G4, G5, G6) in the linear portion between the internal electrode and the dielectric layer and the gap in the curved portion are 10 μm, Samples with the curvature radius Rd of the internal electrode varied from 8 to 400 μm were prepared, and the short-circuit failure rate, withstand voltage failure rate, and capacitance were examined.

表２より、内部電極の角部分の曲率半径Ｒｄが内部電極の短辺Ｗｄ（１２３０μｍ）の１．０％未満では、内部電極の角部分に電流が集中し、コンデンサの耐電圧不良が大きく増加した。一方、内部電極の角部分の曲率半径Ｒｄが内部電極の短辺の２５％を超えると、静電容量は大幅に低下した。

From Table 2, when the radius of curvature Rd of the corner portion of the internal electrode is less than 1.0% of the short side Wd (1230 μm) of the internal electrode, current concentrates on the corner portion of the internal electrode and the withstand voltage failure of the capacitor greatly increases. did. On the other hand, when the radius of curvature Rd of the corner portion of the internal electrode exceeds 25% of the short side of the internal electrode, the capacitance is greatly reduced.

From the above, by setting the radius of curvature Rs at the ridge line portion of the laminate to Rs ≦ Rd + G, and further setting the radius of curvature Rd at the corner portion of the internal electrode to be in the range of 1 to 25% of the short side Wd of the internal electrode. It was also found that the withstand voltage failure can be reduced and the necessary capacitance can be secured.
(Example 2)
Next, the radius of curvature Rd of the corner portion of the internal electrode is set to 120 μm, and all the gaps G (G1, G2, G3, G4, G5, G6) in the linear portion between the internal electrode and the dielectric layer and the gaps of the curved portion are set. Samples with a thickness of 3 to 200 μm were prepared, and the short-circuit failure rate, withstand voltage failure rate, and capacitance were examined.

表３より、内部電極と誘電体層との直線部分におけるすべてのギャップＧが、誘電体層厚みｔの２倍よりも小さいと、ショート不良や耐電圧不良が大きくなり、ギャップＧが積層体長さL（２０００μｍ）の５％を超えると、静電容量は大幅に低下した。

From Table 3, when all the gaps G in the linear portion between the internal electrode and the dielectric layer are smaller than twice the dielectric layer thickness t, the short circuit failure and the withstand voltage failure become large, and the gap G is the length of the laminate. When it exceeded 5% of L (2000 μm), the capacitance was greatly reduced.

  From the above, all the gaps G in the linear portion between the internal electrode and the dielectric layer are not less than twice the dielectric layer thickness t and within a range of 5% or less of the laminate length L (2000 μm), It was found that the withstand voltage failure can be reduced and the necessary capacitance can be secured.

It is a plane sectional view of the layered product part in which the 1st internal electrode was formed of the multilayer ceramic capacitor in one embodiment of the present invention. It is a plane sectional view of the layered product part in which the 2nd internal electrode was formed of the multilayer ceramic capacitor in one embodiment of the present invention. It is a longitudinal cross-sectional view of the multilayer ceramic capacitor in one Embodiment of this invention. It is a partially broken perspective view of the multilayer ceramic capacitor in one embodiment of the present invention.

Explanation of symbols

1: laminated body 2, 2 ': dielectric layer 2a, 2z: protective layer 3: first internal electrode 4: second internal electrode 5: first terminal electrode 6: second terminal electrode 10: laminated ceramic Capacitors G1 to G6: Gap between the linear portions of the internal electrode and the dielectric layer L: Long side of the laminated body t: Thickness per dielectric layer Rd: Radius of curvature of the internal electrode Rs: Radius of curvature of the laminated body Wd: Internal The short side of the electrode

Claims (2)

A laminate in which a plurality of dielectric layers and internal electrodes are alternately laminated;
A multilayer ceramic capacitor including a pair of terminal electrodes respectively connected to the internal electrodes at both ends of the multilayer body,
The radius of curvature of the corner in the laminated surface of the internal electrode is Rd,
The radius of curvature of the ridge line portion of the laminate is Rs,
When the gap in the straight line portion in the laminated surface of the internal electrode and the dielectric layer is G,
Rs ≦ Rd + G,
Rd is 1 to 25% of the short side in the laminated surface of the internal electrode
A multilayer ceramic capacitor characterized in that The gap G is at least twice the thickness of the dielectric layer;
2. The multilayer ceramic capacitor according to claim 1, wherein the multilayer ceramic capacitor is 5% or less of the long side of the multilayer body.

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