JP2005259772A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor Download PDF

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JP2005259772A
JP2005259772A JP2004065511A JP2004065511A JP2005259772A JP 2005259772 A JP2005259772 A JP 2005259772A JP 2004065511 A JP2004065511 A JP 2004065511A JP 2004065511 A JP2004065511 A JP 2004065511A JP 2005259772 A JP2005259772 A JP 2005259772A
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internal electrode
electrode
ceramic capacitor
laminate
curvature
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Akira Kobayashi
亮 小林
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Tdk Corp
Tdk株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic capacitor in which generations of a defective withstand voltage and a defective short circuit between an internal electrode and a terminal electrode is reduced, and which can be increased in electrostatic capacitance by increasing the area of the internal electrode to the maximum. <P>SOLUTION: The internal electrode is bent at a corner facing a connecting part with the terminal electrode, and a laminate has a curved surface at its ridge. The radius of the curvature Rd of the corner of the internal electrode, the radius of the curvature Rs of the ridge of the laminate, and a gap G in a straight line between the internal electrode and a dielectric layer are adjusted to meet a relation of Rs≤Rd+G. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、積層セラミックコンデンサに関するものである。   The present invention relates to a multilayer ceramic capacitor.
積層セラミックコンデンサは、内部電極と誘電体層とを複数交互に積層させたセラミック積層体からなり、内部電極の一端は延出しており、積層チップ素体の両端部に形成された端子電極とそれぞれ複数交互に電気的に接続されている。端子電極との接続部分を除き、内部電極と誘電体層との外周縁に所定のギャップが設けられ、セラミック素体の稜線部分(外周部及び角部)や内部電極の角部には円弧状の丸みを付けた積層セラミックコンデンサが下記の文献に開示されている。
特開2000−124064号公報 特開2000−114097号公報 特開平9−129416号公報 実開平4−92624号公報 実開昭58−56431号公報
The multilayer ceramic capacitor is composed of a ceramic laminate in which a plurality of internal electrodes and dielectric layers are alternately laminated, and one end of the internal electrode extends, and terminal electrodes formed on both ends of the multilayer chip body respectively A plurality of them are electrically connected alternately. Except for the connection with the terminal electrode, a predetermined gap is provided on the outer peripheral edge of the internal electrode and the dielectric layer, and the ridgeline part (peripheral part and corner part) of the ceramic body and the corner part of the internal electrode have an arc shape. A multilayer ceramic capacitor having a rounded shape is disclosed in the following document.
JP 2000-126404 A JP 2000-114097 A JP-A-9-129416 Japanese Utility Model Publication No. 4-92624 Japanese Utility Model Publication No. 58-56431
近年、積層セラミックコンデンサは、小型化,静電容量の大容量化のニーズが多いことから、誘電体1層当りの厚みや保護層の厚みを出来るだけ薄くして誘電体層の積層数を増やし、さらに内部電極の面積を可能な限り大きくして静電容量の大容量化に対応している。一方、チップコンデンサの製造工程中において、積層体同志の衝突による角部の割れ、欠け、クラックなどを防止するため、積層体の稜線部分に断面円弧状の丸みを付けることが知られている。   In recent years, multilayer ceramic capacitors have many needs for miniaturization and increased capacitance. Therefore, the number of dielectric layers is increased by reducing the thickness of each dielectric layer and the thickness of the protective layer as much as possible. Furthermore, the area of the internal electrode is increased as much as possible to cope with the increase in capacitance. On the other hand, in the manufacturing process of a chip capacitor, in order to prevent cracks, chips, cracks, and the like due to collisions between stacked bodies, it is known to round the cross-section arc shape at the ridge line portion of the stacked body.
しかし、積層体に付ける丸みが大きくなると、内部電極の角部分において端子電極と内部電極との距離が近くなり、耐電圧不良やショート不良の原因となる。また、内部電極の角部には電流が集中するため、特に内部電極の角部において耐電圧不良が発生しやすい。   However, when the roundness applied to the laminated body is increased, the distance between the terminal electrode and the internal electrode is reduced at the corner portion of the internal electrode, which causes a breakdown voltage failure or a short-circuit failure. In addition, since the current concentrates at the corners of the internal electrodes, a withstand voltage failure tends to occur particularly at the corners of the internal electrodes.
上記課題を解決するために、内部電極の角部にも円弧状の丸みを設ける手法がとられるが、内部電極の角部における丸みが大きすぎると内部電極面積が減少して大きな静電容量が得られない。   In order to solve the above-mentioned problem, a method of providing an arcuate roundness at the corner of the internal electrode is taken, but if the roundness at the corner of the internal electrode is too large, the area of the internal electrode is reduced and a large capacitance is generated. I can't get it.
一方、端子電極と接続する内部電極と対向する端子電極との間には一定のギャップを設けているが、このギャップが小さすぎると耐電圧不良やショート不良が発生し、逆に、ギャップが大きすぎると内部電極面積が減少して大きな静電容量が得られない。   On the other hand, a constant gap is provided between the internal electrode connected to the terminal electrode and the opposing terminal electrode. However, if this gap is too small, a withstand voltage failure or a short-circuit failure occurs, and conversely, the gap is large. If it is too large, the area of the internal electrode is reduced and a large capacitance cannot be obtained.
そこで、本発明は、内部電極と端子電極間における耐電圧不良やショート不良が少なく、かつ内部電極面積を最大限大きくして静電容量の大容量化に対応出来る積層セラミックコンデンサを提供することを目的とする。   Therefore, the present invention provides a multilayer ceramic capacitor that has less withstand voltage failure and short-circuit failure between the internal electrode and the terminal electrode, and can cope with an increase in capacitance by maximizing the internal electrode area. Objective.
上記課題を解決するための本発明の積層セラミックコンデンサは、誘電体層と内部電極とが複数交互に積層された積層体と、積層体の両端部で内部電極とそれぞれ接続された端子電極対で構成され、内部電極は端子電極との接続部に対向する角部が湾曲しており、さらに積層体は稜線部に曲面を有している。また、内部電極の角部の曲率半径をRd、積層体の稜線部の曲率半径をRs、内部電極と前記誘電体層との直線部分におけるギャップをGとしたとき、Rs≦Rd+G(Rdは、前記内部電極短辺の1〜25%)であることを特徴とする。   In order to solve the above problems, a multilayer ceramic capacitor of the present invention includes a multilayer body in which a plurality of dielectric layers and internal electrodes are alternately stacked, and a pair of terminal electrodes connected to the internal electrodes at both ends of the multilayer body. The internal electrode is curved at the corner facing the connection with the terminal electrode, and the laminate has a curved surface at the ridgeline. Further, when the radius of curvature of the corner portion of the internal electrode is Rd, the radius of curvature of the ridge portion of the multilayer body is Rs, and the gap in the linear portion between the internal electrode and the dielectric layer is G, Rs ≦ Rd + G (Rd is 1 to 25% of the short side of the internal electrode).
本発明の他の積層セラミックコンデンサは、内部電極と誘電体層との直線部分のギャップが、誘電体1層当りの厚みの2倍以上であり、積層体長辺の5%以下であることを特徴としている。   Another multilayer ceramic capacitor according to the present invention is characterized in that the gap between the linear portions of the internal electrode and the dielectric layer is not less than twice the thickness per dielectric layer and not more than 5% of the long side of the laminate. It is said.
本発明の積層セラミックコンデンサにより、積層セラミックコンデンサの耐電圧不良やショート不良が少なくなり、かつ内部電極面積を可能な限り大きくして静電容量の大容量化を図ることが出来る。   According to the multilayer ceramic capacitor of the present invention, the withstand voltage failure and short-circuit failure of the multilayer ceramic capacitor can be reduced, and the internal electrode area can be increased as much as possible to increase the capacitance.
以下、本発明の積層セラミックコンデンサを図面に基づいて詳説する。
図1および図2は、本発明の一実施形態である積層セラミックコンデンサの積層体部分における平面断面図、図3はその積層セラミックコンデンサの縦断面図、図4はその積層セラミックコンデンサの一部破断斜視図である。
The multilayer ceramic capacitor of the present invention will be described in detail below with reference to the drawings.
1 and 2 are plan sectional views of a multilayer body portion of a multilayer ceramic capacitor according to an embodiment of the present invention, FIG. 3 is a longitudinal sectional view of the multilayer ceramic capacitor, and FIG. 4 is a partially broken view of the multilayer ceramic capacitor. It is a perspective view.
積層体1は、チタン酸バリウムを主成分とした誘電体セラミック材料から成る複数の誘電体層2、2′が積層されて構成されている。そして、この積層体の層間には、第1の内部電極3および第2の内部電極4が交互に配置されている。第1及び第2の内部電極3,4は、例えばNiなどの卑金属材料、あるいはPdやAg−Pd合金などの貴金属材料などからなる。   The laminate 1 is configured by laminating a plurality of dielectric layers 2 and 2 'made of a dielectric ceramic material mainly composed of barium titanate. The first internal electrodes 3 and the second internal electrodes 4 are alternately arranged between the layers of the laminate. The first and second internal electrodes 3 and 4 are made of, for example, a base metal material such as Ni or a noble metal material such as Pd or an Ag—Pd alloy.
積層体1の両端面には、第1の端子電極5、第2の端子電極6がそれぞれ形成される。
そして、第1の内部電極3は誘電体層2上に形成され、端子電極5との接続部以外にそれぞれギャップG1、G2、G3を有している。また、第2の内部電極4は、第1の内部電極3が形成された誘電体層間と隣接する層間に配置される。そして、第2の内部電極4は誘電体層2′上に形成され、端子電極6との接続部以外にそれぞれギャップG4、G5、G6を有している。
A first terminal electrode 5 and a second terminal electrode 6 are formed on both end faces of the laminate 1.
The first internal electrode 3 is formed on the dielectric layer 2 and has gaps G1, G2, and G3 in addition to the connection portion with the terminal electrode 5, respectively. The second internal electrode 4 is disposed between the dielectric layer on which the first internal electrode 3 is formed and the adjacent layer. The second internal electrode 4 is formed on the dielectric layer 2 ′, and has gaps G 4, G 5, G 6 in addition to the connection portion with the terminal electrode 6.
第1の内部電極3は、第1の端子電極5に対向する角部に曲率半径Rdの丸みを備えている。また、第2の内部電極4は、第2の端子電極6に対向する角部に曲率半径Rdの丸みを備えている。そして、積層体1の稜線部分(角部、隅部)は、割れや欠けやクラックを防止するため、曲率半径Rsの丸みを備えている。   The first internal electrode 3 has a roundness with a radius of curvature Rd at the corner facing the first terminal electrode 5. Further, the second internal electrode 4 has a roundness with a radius of curvature Rd at a corner facing the second terminal electrode 6. And the ridgeline part (corner | corner part, corner part) of the laminated body 1 is equipped with the roundness of the curvature radius Rs in order to prevent a crack, a chip, and a crack.
端子電極5,6は、下地導体膜とめっき層とで構成されている。第1の端子電極5は、複数の第1の内部電極3と接続し、積層体1の一方の端面、即ち左側の端面を中心に、その端面と隣接する4つの面の端部よりに形成されている。   The terminal electrodes 5 and 6 are composed of a base conductor film and a plating layer. The first terminal electrode 5 is connected to the plurality of first internal electrodes 3 and is formed from one end face of the multilayer body 1, that is, the left end face, from the end portions of the four faces adjacent to the end face. Has been.
第2の端子電極6は、複数の第2の内部電極4と接続し、積層体1の他方の端面、即ち右側の端面を中心に、その端面と隣接する4つの面の端部よりに形成されている。   The second terminal electrode 6 is connected to the plurality of second inner electrodes 4 and is formed from the other end face of the multilayer body 1, that is, the end face of the four faces adjacent to the end face, centering on the right end face. Has been.
本実施形態においては、積層体の稜線部分における曲率半径をRs、内部電極に設けた曲率半径をRd、内部電極と誘電体層との直線部分におけるギャップをG(G1、G2、G3、G4、G5、G6)としたとき、すべてのGに対してRs≦Rd+Gであり、内部電極3、4の角部分の曲率半径Rdは、内部電極短辺Wdの1〜25%である。   In the present embodiment, the radius of curvature at the ridge portion of the laminate is Rs, the radius of curvature provided at the internal electrode is Rd, and the gap at the linear portion between the internal electrode and the dielectric layer is G (G1, G2, G3, G4, G5, G6), Rs ≦ Rd + G for all G, and the radius of curvature Rd of the corner portions of the internal electrodes 3 and 4 is 1 to 25% of the internal electrode short side Wd.
さらに、本実施形態においては、内部電極と誘電体層との直線部分におけるギャップをG(G1、G2、G3、G4、G5、G6)としたとき、すべてのGは誘電体1層当たりの厚みtの2倍以上であり、かつセラミック素体長辺Lの5%以下である。   Furthermore, in this embodiment, when the gap in the straight line portion between the internal electrode and the dielectric layer is G (G1, G2, G3, G4, G5, G6), all G are thicknesses per dielectric layer. It is at least twice t and 5% or less of the ceramic body long side L.
上記構成の積層セラミックコンデンサ10は、以下のように作製する。   The multilayer ceramic capacitor 10 having the above configuration is manufactured as follows.
まず、誘電体材料からなる2種類のセラミックグリーンシートを用意する。1つのセラミックグリーンシートは、保護層の誘電体層2a、2zとなるグリーンシートであり、もう1つのセラミックグリーンシートは保護層に挟まれる誘電体層2、2′となるセラミックグリーンシートである。   First, two types of ceramic green sheets made of a dielectric material are prepared. One ceramic green sheet is a green sheet serving as the dielectric layers 2a and 2z of the protective layer, and the other ceramic green sheet is a ceramic green sheet serving as the dielectric layers 2 and 2 'sandwiched between the protective layers.
ここで、各セラミックグリーンシートは、複数の積層セラミックコンデンサとなる素子領域が縦横に配列されているが、1つの素子領域について説明する。   Here, in each ceramic green sheet, element regions to be a plurality of multilayer ceramic capacitors are arranged vertically and horizontally. One element region will be described.
初めに、保護層の誘電体層2a、2zとなるセラミックグリーンシートを除いて、誘電体層2、2′となるグリーンシート上に、第1の内部電極3となる導体膜、または第2の内部電極4となる導体膜を、例えば金属粉末を有する導電性ペーストの印刷などにより形成する。ここで、内部電極3,4はグリーンシート面内に、グリーンシート面積よりも小さく、ギャップをもって印刷される。また、内部電極3は端子電極と接続しない角部において丸みを形成して印刷する。同様に、第2の内部電極4は端子電極と接続しない角部において丸みを形成して印刷する。   First, except for the ceramic green sheets that become the dielectric layers 2a and 2z of the protective layer, the conductor film that becomes the first internal electrode 3 or the second film on the green sheets that become the dielectric layers 2 and 2 ' A conductor film to be the internal electrode 4 is formed by printing a conductive paste having metal powder, for example. Here, the internal electrodes 3 and 4 are printed in the green sheet surface with a gap smaller than the area of the green sheet. Further, the internal electrode 3 is printed by rounding at a corner portion that is not connected to the terminal electrode. Similarly, the second internal electrode 4 is printed by forming a roundness at a corner portion that is not connected to the terminal electrode.
次に、第1及び第2の内部電極3,4が印刷されたグリーンシートを、順次交互に積層する。すなわち、最下面には保護層となる誘電体層2zのグリーンシートを用い、その上に第2の内部電極4となる導体膜を形成したグリーンシート、さらにその上に第1の内部電極3となる導体膜を形成したグリーンシートを交互に積層し、最上面には、保護層となる誘電体層2aのグリーンシートを積層し、圧着する。   Next, green sheets on which the first and second internal electrodes 3 and 4 are printed are sequentially stacked alternately. That is, a green sheet having a dielectric layer 2z serving as a protective layer is used on the lowermost surface, and a conductive film serving as the second internal electrode 4 is formed thereon, and further, the first internal electrode 3 and The green sheets on which the conductive films to be formed are alternately stacked, and the green sheet of the dielectric layer 2a serving as the protective layer is stacked on the uppermost surface and pressure-bonded.
次に、このグリーンシートの積層体を、所定素子領域に応じて所定寸法に切断して積層体となる未焼成のチップ状積層体を形成する。   Next, this green sheet laminate is cut into a predetermined dimension according to a predetermined element region to form an unfired chip-like laminate that becomes a laminate.
次に、この未焼成のチップ状積層体を所定の雰囲気、温度で焼成する。これによって、未焼成のチップ状積層体を構成する誘電体層となるグリーンシート、保護層2a、2z、内部電極3,4は焼成処理され、一体焼結積層体となる。   Next, this unfired chip-shaped laminate is fired at a predetermined atmosphere and temperature. As a result, the green sheets, the protective layers 2a and 2z, and the internal electrodes 3 and 4 serving as the dielectric layers constituting the unfired chip-like laminate are fired to form an integrally sintered laminate.
その後、焼成された一体焼結積層体をバレル研磨加工する。これによって積層体1の稜線部分は曲面になる。   Thereafter, the fired integral sintered laminate is subjected to barrel polishing. Thereby, the ridge line part of the laminated body 1 becomes a curved surface.
次に、積層体1の第1の内部電極が露出した端面に端子電極5を、第2の内部電極4が露出した端面に端子電極6を形成する。具体的には、積層体1の端面部分をAg、Ag−Pd合金、Cuなどの導電性ペースト槽内に浸漬(ディッピング)して、積層体1の端面付近に導電性ペーストを塗布する。そして塗布した導電性ペーストを焼き付けて下地導体膜を形成し、その表面にNi、Sn、Sn−Pb合金などの材料からなるめっき層を形成する。   Next, the terminal electrode 5 is formed on the end surface where the first internal electrode of the laminate 1 is exposed, and the terminal electrode 6 is formed on the end surface where the second internal electrode 4 is exposed. Specifically, the end surface portion of the laminated body 1 is immersed (dipped) in a conductive paste tank of Ag, Ag—Pd alloy, Cu or the like, and the conductive paste is applied in the vicinity of the end surface of the laminated body 1. Then, the applied conductive paste is baked to form a base conductor film, and a plating layer made of a material such as Ni, Sn, or Sn—Pb alloy is formed on the surface thereof.
以上、本実施形態について説明してきたが、本発明は上述した実施形態に何等限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々に改変することが出来る。以下、本発明をさらに詳細な実施例に基づき説明するが、本発明はこれら実施例に限定されない。   Although the present embodiment has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Hereinafter, the present invention will be described based on further detailed examples, but the present invention is not limited to these examples.
(実施例1)
2012形状(2.00×1.25×1.25mm)の積層セラミックコンデンサを作製し、誘電体層厚みを2.5μm、内部電極と誘電体層との直線部分におけるすべてのギャップG(G1、G2,G3、G4、G5、G6)を10μm、内部電極の曲率半径Rdを200μmとして、積層体の曲率半径Rsを50〜230μmに変化させた試料を作製し、ショート不良率、耐電圧不良率、静電容量を調べた。
(Example 1)
A multilayer ceramic capacitor having a 2012 shape (2.00 × 1.25 × 1.25 mm) is manufactured, the dielectric layer thickness is 2.5 μm, and all gaps G (G1, G1, G2, G3, G4, G5, G6) are set to 10 μm, the curvature radius Rd of the internal electrode is set to 200 μm, and a sample in which the curvature radius Rs of the laminated body is changed to 50 to 230 μm is manufactured. The capacitance was examined.
具体的には、チタン酸バリウムを主成分とするセラミック粉末と焼成助材、分散剤、バインダ等を添加して誘電体ペーストを調製し、これを用いて通常のシート作製方法によりセラミックグリーンシートを作製し、このグリーンシート上に内部電極(Niペースト)をスクリーン印刷方法により形成した。内部電極形成したセラミックグリーンシートを300層積層し、熱圧着、切断し、未焼成状態のチップ状積層体を得た。ここで積層方向の上下には保護層として内部電極を形成していないグリーンシートを積層した。   Specifically, a ceramic powder mainly composed of barium titanate and a firing aid, a dispersing agent, a binder, etc. are added to prepare a dielectric paste, and a ceramic green sheet is prepared by a normal sheet manufacturing method using this. An internal electrode (Ni paste) was formed on this green sheet by a screen printing method. 300 layers of ceramic green sheets on which internal electrodes were formed were laminated, thermocompression bonded, and cut to obtain a chip-shaped laminated body in an unfired state. Here, green sheets on which no internal electrode was formed as a protective layer were stacked above and below in the stacking direction.
次に、この未焼成状態のチップ状積層体を300℃×10時間で脱脂した後、還元雰囲気中、1100〜1400℃で一体焼成した。   Next, this unfired chip-like laminate was degreased at 300 ° C. for 10 hours, and then integrally fired at 1100 to 1400 ° C. in a reducing atmosphere.
そして、この焼結された積層体の稜線部分が表1に示す曲率半径となるようにバレル研磨加工を施した。その後、積層体の端面部分に端子電極(Cuペースト)の印刷焼付けを行い、通常の電解めっき法によりNiおよびSnめっきを被着させた。   And the barrel grinding | polishing process was performed so that the ridgeline part of this sintered laminated body might become the curvature radius shown in Table 1. Thereafter, the terminal electrode (Cu paste) was printed and baked on the end face portion of the laminate, and Ni and Sn plating were deposited by a normal electrolytic plating method.
表1より、積層体の稜線部分における曲率半径Rsが、内部電極に設けた曲率半径Rdと、内部電極と誘電体層との直線部分のギャップGの合計(210μm)以下の場合には、ショート不良及び耐電圧不良は発生しなかった。しかし、210μmを超えるとこれらの不良が発生した。 From Table 1, when the radius of curvature Rs at the ridge portion of the laminate is less than the sum (210 μm) of the radius of curvature Rd provided on the internal electrode and the gap G of the linear portion between the internal electrode and the dielectric layer, short There was no failure or withstand voltage failure. However, these defects occurred when the thickness exceeded 210 μm.
次に、誘電体層厚みを2.5μm、内部電極と誘電体層との直線部分のすべてのギャップG(G1、G2、G3、G4、G5、G6)および曲線部分のギャップを10μmにして、内部電極の曲率半径Rdを8〜400μmと変化させた試料を作製し、ショート不良率、耐電圧不良率、静電容量を調べた。   Next, the dielectric layer thickness is 2.5 μm, all the gaps G (G1, G2, G3, G4, G5, G6) in the linear portion between the internal electrode and the dielectric layer and the gap in the curved portion are 10 μm, Samples with the curvature radius Rd of the internal electrode varied from 8 to 400 μm were prepared, and the short-circuit failure rate, withstand voltage failure rate, and capacitance were examined.
表2より、内部電極の角部分の曲率半径Rdが内部電極の短辺Wd(1230μm)の1.0%未満では、内部電極の角部分に電流が集中し、コンデンサの耐電圧不良が大きく増加した。一方、内部電極の角部分の曲率半径Rdが内部電極の短辺の25%を超えると、静電容量は大幅に低下した。 From Table 2, when the radius of curvature Rd of the corner portion of the internal electrode is less than 1.0% of the short side Wd (1230 μm) of the internal electrode, current concentrates on the corner portion of the internal electrode and the withstand voltage failure of the capacitor greatly increases. did. On the other hand, when the radius of curvature Rd of the corner portion of the internal electrode exceeds 25% of the short side of the internal electrode, the capacitance is greatly reduced.
以上より、積層体の稜線部分における曲率半径RsをRs≦Rd+Gとし、さらに内部電極の角部分の曲率半径Rdが、内部電極における短辺Wdの1〜25%の範囲にすることによって、ショート不良及び耐電圧不良を低減し、なおかつ必要な静電容量を確保出来ることがわかった。
(実施例2)
次に、内部電極の角部分の曲率半径Rdを120μmにして、内部電極と誘電体層との直線部分におけるすべてのギャップG(G1、G2、G3、G4、G5、G6)および曲線部分のギャップを3〜200μmと変化させた試料を作製し、ショート不良率、耐電圧不良率、静電容量を調べた。
From the above, by setting the radius of curvature Rs at the ridge line portion of the laminate to Rs ≦ Rd + G, and further setting the radius of curvature Rd at the corner portion of the internal electrode to be in the range of 1 to 25% of the short side Wd of the internal electrode. It was also found that the withstand voltage failure can be reduced and the necessary capacitance can be secured.
(Example 2)
Next, the radius of curvature Rd of the corner portion of the internal electrode is set to 120 μm, and all the gaps G (G1, G2, G3, G4, G5, G6) in the linear portion between the internal electrode and the dielectric layer and the gaps of the curved portion are set. Samples with a thickness of 3 to 200 μm were prepared, and the short-circuit failure rate, withstand voltage failure rate, and capacitance were examined.
表3より、内部電極と誘電体層との直線部分におけるすべてのギャップGが、誘電体層厚みtの2倍よりも小さいと、ショート不良や耐電圧不良が大きくなり、ギャップGが積層体長さL(2000μm)の5%を超えると、静電容量は大幅に低下した。 From Table 3, when all the gaps G in the linear portion between the internal electrode and the dielectric layer are smaller than twice the dielectric layer thickness t, the short circuit failure and the withstand voltage failure become large, and the gap G is the length of the laminate. When it exceeded 5% of L (2000 μm), the capacitance was greatly reduced.
以上より、内部電極と誘電体層との直線部分におけるすべてのギャップGが、誘電体層厚みtの2倍以上であり、積層体長さL(2000μm)の5%以下の範囲において、ショート不良及び耐電圧不良を低減し、なおかつ必要な静電容量を確保出来ることがわかった。   From the above, all the gaps G in the linear portion between the internal electrode and the dielectric layer are not less than twice the dielectric layer thickness t and within a range of 5% or less of the laminate length L (2000 μm), It was found that the withstand voltage failure can be reduced and the necessary capacitance can be secured.
本発明の一実施形態における積層セラミックコンデンサの、第1の内部電極が形成された積層体部分の平面断面図である。It is a plane sectional view of the layered product part in which the 1st internal electrode was formed of the multilayer ceramic capacitor in one embodiment of the present invention. 本発明の一実施形態における積層セラミックコンデンサの、第2の内部電極が形成された積層体部分の平面断面図である。It is a plane sectional view of the layered product part in which the 2nd internal electrode was formed of the multilayer ceramic capacitor in one embodiment of the present invention. 本発明の一実施形態における積層セラミックコンデンサの縦断面図である。It is a longitudinal cross-sectional view of the multilayer ceramic capacitor in one Embodiment of this invention. 本発明の一実施形態における積層セラミックコンデンサの一部破断斜視図である。It is a partially broken perspective view of the multilayer ceramic capacitor in one embodiment of the present invention.
符号の説明Explanation of symbols
1: 積層体
2,2′ : 誘電体層
2a,2z: 保護層
3: 第1の内部電極
4: 第2の内部電極
5: 第1の端子電極
6: 第2の端子電極
10: 積層セラミックコンデンサ
G1〜G6: 内部電極と誘電体層との直線部分のギャップ
L: 積層体の長辺
t: 誘電体1層当りの厚み
Rd: 内部電極の曲率半径
Rs: 積層体の曲率半径
Wd: 内部電極の短辺


















1: laminated body 2, 2 ': dielectric layer 2a, 2z: protective layer 3: first internal electrode 4: second internal electrode 5: first terminal electrode 6: second terminal electrode 10: laminated ceramic Capacitors G1 to G6: Gap between the linear portions of the internal electrode and the dielectric layer L: Long side of the laminated body t: Thickness per dielectric layer Rd: Radius of curvature of the internal electrode Rs: Radius of curvature of the laminated body Wd: Internal The short side of the electrode


















Claims (2)

  1. 誘電体層と内部電極とが複数交互に積層された積層体と、
    前記積層体の両端部で前記内部電極とそれぞれ接続する端子電極対とを含む積層セラミックコンデンサであって、
    前記内部電極の積層面内の角部の曲率半径をRd、
    前記積層体の稜線部の曲率半径をRs、
    前記内部電極と前記誘電体層との積層面内の直線部におけるギャップをGとしたとき、
    Rs≦Rd+Gであり、
    Rdは前記内部電極の積層面内における短辺の1〜25%
    であることを特徴とする積層セラミックコンデンサ。
    A laminate in which a plurality of dielectric layers and internal electrodes are alternately laminated;
    A multilayer ceramic capacitor including a pair of terminal electrodes respectively connected to the internal electrodes at both ends of the multilayer body,
    The radius of curvature of the corner in the laminated surface of the internal electrode is Rd,
    The radius of curvature of the ridge line portion of the laminate is Rs,
    When the gap in the straight line portion in the laminated surface of the internal electrode and the dielectric layer is G,
    Rs ≦ Rd + G,
    Rd is 1 to 25% of the short side in the laminated surface of the internal electrode
    A multilayer ceramic capacitor characterized in that
  2. 前記ギャップGが、前記誘電体1層当りの厚みの2倍以上であり、
    前記積層体長辺の5%以下であることを特徴とする請求項1記載の積層セラミックコンデンサ。















    The gap G is at least twice the thickness of the dielectric layer;
    2. The multilayer ceramic capacitor according to claim 1, wherein the multilayer ceramic capacitor is 5% or less of the long side of the multilayer body.















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