JP2005258607A - Processor capable of executing software short of synchronization instruction - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To acquire normal execution results acquirable unless synchronization instructions are missed, from software missing synchronization instructions. <P>SOLUTION: A processor 301 that provides synchronization instructions for both reading and writing makes the behavior of the writing synchronization instruction variable, and changes the behavior of the writing synchronization instruction to enable normal software execution (the same operation as with the synchronization instruction unmissed on the reading side) if only the writing side has the synchronization instruction even if the reading side misses the synchronization instruction. Specifically, the writing synchronization instruction has two operation modes. One (normal operation mode) enables normal software execution only if both reading and writing sides have the synchronization instructions, and the other (emergency operation mode) enables normal software execution if only the writing side has the synchronization instruction. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a microprocessor which is a kind of electronic circuit.

  A problem to be solved when implementing a multiprocessor computer system using a processor equipped with a cache memory is inconsistency in the cache memory. The cache memory is a storage area for speeding up the memory reference of the processor. When the processor performs memory reference, it takes a long time to refer to the main memory because the memory element of the main memory is slow in operation instead of having a large capacity. Therefore, recent processors have a high-speed and small-capacity storage element called a cache memory in order to speed up memory reference, and a part of the stored contents of the main memory is copied to the cache memory. When referring to the memory, first, the cache memory is checked for a copy of the value stored at the address to be referred to. If there is, the value is read from the high-speed cache memory, and if not, the low-speed main memory is referenced. When the main memory is referenced, the referenced value is stored in the cache memory so that it can be referenced from the cache memory the next time the same address is referenced. When the referenced value is stored in the cache memory, some area of the cache memory is overwritten. Assuming that the erasure area holds a copy of the contents stored at the address α in the main memory, as a result of the erasure, the processor will refer to the main memory the next time it refers to the address α. Writing a new value into the cache memory and crushing the old value is referred to as replacing the contents of the cache memory.

  Cache memory inconsistency, which is a problem in computers with multiple processors, occurs when different values are stored in each cache memory as values stored in the same main memory address by each processor. . The following is an example of this problem. First, in the computer system composed of the processor A and the processor B, it is assumed that the processor A stores the value at the address α in the main memory in the cache memory. Here, if the processor B writes a value at the address α, a problem occurs due to inconsistency of the cache memory when the following condition is satisfied.

  The condition is that the processor B only writes a value to the cache memory. In recent years, in order to speed up writing to the memory, the processor may write to the memory only once and then write to the main memory when replacing the contents of the cache memory. . In this way, for example, when writing to the same address occurs in succession, writing to the main memory requires only the last written value, so writing to the main memory can be reduced and memory reference can be speeded up. On the other hand, if the writing to the main memory is delayed, the fact that the value has been written is not transmitted to other processors, so that inconsistency of the cache memory occurs. If the cache memory inconsistency is not resolved, the execution result of the program may be wrong.

  In order to eliminate the inconsistency of the cache memory, the processor B has only to write the value into the main memory. In order to force the processor to write to the main memory, an instruction “synchronous instruction on the writing side” may be executed. The synchronous instruction on the writing side plays a role of writing the value written only in the cache to the main memory. Modern processors generally have a function of peeping (snooping) references to main memory. When one processor executes a write-side synchronization instruction and writes to main memory, The processor detects the writing by the snoop function, checks whether the old value before writing is held in the cache memory, and discards the old value if held. As a result, the cache memory inconsistency is resolved.

  The term “synchronous instruction” refers to all instructions for the purpose of solving problems arising from mutual interference between processors in a multiprocessor computer system. There are various implementations of synchronous instructions, and there are processors that provide "synchronous instructions on the read side" in addition to "synchronous instructions on the write side" that resolve cache memory inconsistencies.

  The synchronous instruction on the reading side is intended to avoid problems that arise from out-of-order execution of instructions. Out-of-order execution means that instructions arranged in an instruction sequence are executed in an order different from the order of arrangement. For example, if instruction sequences m1 and m2 are executed out of order, m2 may be executed first and m1 may be executed later. Problems that arise from out-of-order execution will be described using the program of FIG. The program of FIG. 1 is intended for communication between processors, and is divided into a side for writing data corresponding to communication contents in a variable data and a side for reading. In the program that writes data, after writing data to the variable data, execute the synchronous instruction sync on the write side to transmit the written data to the processor on the reading side, and then set the variable flag to read the data. to approve. On the other hand, the reading program refers to the variable flag, waits until the variable flag is reached, and then reads the data written in the variable data.

  When the program shown in FIG. 1 is executed by a processor having a function for executing out-of-order execution, data written by the writing side may not be transmitted to the reading side in the order of writing. The cause is that, as a result of out-of-order execution, the reader can refer to the variable data before referring to the variable flag. Specifically, when the memory reference order is as shown in FIG. 2, the reading side refers to the contents of the variable data before the data is written, and the data written by the writing side is not transmitted to the reading side. .

  In the program shown in FIG. 1, the method in which the writing side reliably transmits the content written in the variable data to the reading side differs depending on the processor. The problem-solving method for the processor (Non-Patent Document 1) that provides the synchronization instruction on the reading side is that the synchronization instruction on the reading side is read between the reading of the variable flag and the reading of the variable data. Is to insert. The synchronous instruction on the reading side has the effect of suppressing the out-of-order execution of the instruction, and if it is inserted between the reading of the variable flag and the reading of the variable data, it guarantees that the reading of the variable data will be executed first. Thus, the content written in the variable data by the writer can be surely transmitted to the reader.

  On the other hand, in a processor (Non-Patent Document 2) that does not provide a synchronous instruction on the reading side, the contents written in the variable data are surely transmitted to the reading side without any modification to the program of FIG. This is because in a processor that does not provide a reading-side synchronization instruction, the writing-side synchronization instruction has the effect of canceling the reading-side out-of-order execution.

  Different implementations of synchronous instructions for each processor is an obstacle to porting software to different processors. Specifically, when porting software developed for a processor that provides only a synchronous instruction on the writing side to a processor that provides a synchronous instruction on the reading side and the writing side (both sides), the synchronous instruction is sent to the reading side. You may forget to insert. For example, when porting the program of FIG. 1 developed for a processor that provides only the synchronization instruction on the writing side, forgetting to insert the synchronization instruction on the reading side between reading the flag and reading the data. This forgetting to insert is difficult to automatically detect and insert the position in the program where the reading-side synchronization instruction should be inserted. Due to the decision. Even if you forget to insert a synchronization command, the software often works normally. This is because whether or not a failure occurs due to forgetting to insert a synchronous instruction depends largely on the timing. For example, in order to cause a problem from the program of FIG. 1, it is necessary to refer to the memory at the timing of FIG.

  As a result of software that has forgotten to insert a synchronization instruction at first glance functioning normally, it is sold after passing the quality inspection of the company that transplanted the software. There are still some cases where the If a defect is found in the software that has started operation, the operation is stopped during the period until the correction, and a huge economic loss can occur. For this reason, for problems that are difficult to find until operation begins, such as forgetting to insert a synchronous instruction, it is important to take measures to quickly deal with the problem when it is revealed.

IBM Microelectronics, MOTOROLA: "PowerPC Microprocessor Family: The Programming Environments," 1996 Gerry Kane: "PA-RISC 2.0 ARCHITECTURE," Prentice-Hall, 1996

  An object of the present invention is to provide a processor that can normally execute software for which a synchronization instruction on the reading side is forgotten to be inserted.

In a processor that provides synchronous instructions on both sides, by changing the behavior of the synchronous instruction on the writing side and changing the behavior of the synchronous instruction on the writing side, if there is a synchronous instruction only on the writing side, the synchronous instruction on the reading side Make the software run correctly even if it is missing (make sure it works as if the synchronization instruction on the reading side is not missing). Specifically, there are two operation modes for the write side synchronous instruction, and one (normal operation mode) can execute the software normally only when there is a synchronous instruction for both reading and writing, and the other (emergency operation mode). ) If there is a synchronization instruction only on the writing side, the software can be executed normally. If a defect is found in the software that is missing the synchronization instruction on the reading side, the processor operation mode is switched to the emergency operation mode as specified by the user. In order to make the behavior of the synchronous instruction on the writing side variable, a storage area for specifying the behavior of the synchronous instruction on the writing side is provided in the processor. The processor refers to the storage area when executing the write side synchronous instruction, and if the value of the storage area is in the emergency operation mode, the delay until the execution of the write side synchronous instruction is extended. To do.
Here, the delay until the execution of the write side synchronous instruction is completed, the time elapsed from the start of execution of the write side synchronous instruction until the execution is completed (how many clocks are passed) And its length varies depending on the operation mode. In the present invention, the delay when the “emergency operation mode” is set is set longer than the delay when the “normal operation mode” is set.

  By extending the delay, if the cache memory has a snoop mechanism, it is possible to secure the time until the written value is transmitted to the cache memory of another processor and to maintain the consistency of the cache memory. Further, due to the extension of the delay, it becomes possible to wait for the completion of the execution of the read instruction being executed out of order by another processor. As a result, even when software that lacks the synchronization instruction on the reading side is executed, it is possible to obtain the same execution result as when there is a synchronization instruction on the reading side.

  Software that has forgotten to insert a synchronization instruction can be executed normally.

  In the processor, the behavior of the synchronous instruction on the writing side is made variable so that the software that has forgotten to insert the synchronous instruction can be executed normally.

  FIG. 3 shows an example of a computer including the processor 301 of the present invention. In the computer of FIG. 3, an external storage device such as a processor 301, a main memory 303, and a DVD-ROM reader 304 is connected on a bus 302, and a program recorded in an external storage such as a DVD-ROM 305 is loaded on the bus 302. Then, the data is read into the main memory 303 and executed by the processor 301.

  The processor 301 includes a memory interface 306, an instruction interpretation unit 307, a register group 308, and an instruction execution unit 309. The processor uses these elements and proceeds to execute the program in the following procedure. First, the instruction interpretation unit 307 acquires the value stored in the register PC 310 that holds the address of the next instruction to be executed via the wiring 311, and acquires the instruction at the acquired address via the memory interface 306. Then, the contents of the acquired instruction are interpreted, and according to the contents, the instruction execution unit 309 is instructed to execute the instruction and waits for an instruction execution completion report. For example, if the instruction is an instruction that records a value in a storage area that designates the operation of the synchronous instruction, the instruction execution unit 309 is instructed to execute the instruction. The synchronous mode designation instruction execution circuit 312 can be realized by a logic circuit similar to an existing logic circuit that executes an instruction for reading a value into a register. The synchronous mode designation command execution circuit 312 sets a value in the synchronous mode designation register 314, that is, the above-described storage area via the wiring 313. In this embodiment, since two operation modes (normal operation mode and emergency operation mode) are provided for the write-side synchronization instruction, the synchronization mode designation register 314 is a storage area that can store 1-bit information. Good.

  If the acquired instruction is a synchronous instruction sync on the writing side, the instruction interpretation unit 307 instructs the synchronous instruction executing circuit 315 on the writing side to execute the instruction in the instruction executing unit 309. The write side synchronous instruction execution circuit 315 changes its operation with reference to the value of the synchronous mode designation register 314 of the present invention via the wiring 313.

  A method for realizing the synchronous instruction execution circuit 315 on the writing side according to this embodiment will be described with reference to FIGS.

  First, the operation content of the write side synchronous instruction execution circuit 315 (the operation content of the function for changing the delay until the execution of the synchronous instruction is completed) is shown in FIG. In FIG. 4, the synchronous instruction execution circuit 315 on the writing side first executes a process 401 that does not depend on the value of the synchronous mode designation register 314, and then the process of the present invention that depends on the value of the synchronous mode designation register 314. 402 is executed. The operation contents of the independent process 401 are the same as the process contents when executing the write-side synchronization instruction in the existing processor that provides the synchronization instructions on both sides. In the process 402 of the present invention, which depends on the value of the synchronization mode specification register 314, first, the value of the synchronization mode specification register 314 is referred to in a decision 403 to determine whether or not the value is normal. If it is not normal, a delay process 404 is executed. To set the value of the synchronization mode specification register 314, an instruction for setting the internal state of the processor including the synchronization mode specification register 314 is executed. In the delay process 404, first, in process 405, the value of the delay counter c is initialized to the number of delay clocks. The number of delay clocks is a value specific to the processor. When the processor executes a write instruction to the memory, the write is transmitted to the other processor, and when the other processor executes the read instruction next time, the old value before the write is performed. Is given as the worst number of clocks it takes to guarantee that Next, in decision 406, it is checked whether the value of the counter c is greater than 0. If it is larger, the process proceeds to process 407, and if not larger, the delay process 404 is terminated. In process 407, the value of the counter c is decremented by 1, and in the subsequent process 408, the clock line 316 is referred to wait for the next clock, and then the process returns to decision 406. Note that the process 402 of the present invention can be realized by a simple sequential circuit.

  In the processor 101 of the present invention having the synchronous instruction execution circuit 315 that performs the operation of FIG. 4, if the value of the synchronous mode designation register 314 is in the emergency operation mode, the writer writes in the variable data in the program of FIG. The data can be reliably communicated to the reader. This is because, in the program of FIG. 1, the condition in which the data written to the variable data is not transmitted to the reading side is that reading and writing occur in the order of FIG. 2, but in the emergency operation mode, reading and writing occur in the order of FIG. Because it does not. In FIG. 2, first, the reading side reads out the contents of the variable data by executing out-of-order execution (process 201), and the next writing side performs two writes (process 202 and process 203). , There is a synchronization instruction sync on the writing side. In the emergency operation mode, since it takes a long time to finish the sync, the reading side always completes the reading of the variable flag before the sync ends. FIG. 8 shows the order of memory reference in the emergency operation mode. First, the reading side reads data from the variable data by out-of-order execution (processing 801), and the writing side executes writing to the variable data (processing 802). Thereafter, the synchronous instruction sync on the writing side is executed. This synchronous instruction is delayed by a delay counter c set for each processor, and the reading of the variable flag on the reading side is surely completed during this time (process 804). At this time, the value of the variable flag read by the reading side is false. As can be seen from the program of FIG. 1, that the value of the read variable flag is “false” means that the reading side is not yet permitted to read the value of the variable “data”. Therefore, the program on the reading side goes to the variable flag again. Returning to FIG. 8, the writing program writes a true value in the variable flag after a predetermined time based on the delay counter c has elapsed (process 803). After that, when the program on the reading side is executed out of order, the reading side reads the value of the variable data (process 805), and the reading side reads the value of the variable flag (process 806). When the reading side reads the value of the variable flag (processing 806), the value becomes a true value. At this time, the reading side reads the value of the variable data read in the processing 805, but the writing side surely writes the value written in the processing 802. It has become. Even when the instruction of the process 805 is executed before the instruction of the process 803 due to out-of-order execution, the value of the variable data read by the process 805 on the reading side becomes the value written by the process 802 on the reading side and operates correctly.

  As a result, reading / writing does not occur at the timing of FIG. 2, and the writing side is surely transmitted to the reading side of the data written in the variable data.

  In the process 404 of FIG. 4, a delay is generated by a constant (number of delay clocks) times, but the length of the delay can be determined by arbitrating between processors. For example, a processor that executes sync requests another processor via the bus 302 to return a read instruction during execution of out-of-order, and completes the execution of the sync when the reply is received. You can also

  Next, FIG. 5 shows the operation content of the write side synchronous instruction execution circuit 315 (operation content of a function that generates a hardware trap).

  FIG. 5 is obtained by replacing the delay process 404 of FIG. 4 with a trap generation process 504. The realization of the trap generation process 504 is in accordance with the existing realization of the instruction that generates a trap. The write side synchronous instruction execution circuit 315 that performs the operation of FIG. 5 generates a trap if the value of the synchronous mode designation register 314 is not normal. When the trap is generated, if the operating system captures the trap and generates a delay, and then resumes execution from the instruction next to the sync that generated the trap, the synchronous instruction execution circuit 315 according to the operation of FIG. Even with the implementation of, there will be no problem due to the lack of synchronization instructions on the reading side.

  Next, FIG. 6 shows an embodiment of software for recording a value in a storage area for designating the operation of the synchronous instruction. The software shown in FIG. 6 includes an initialization process 601 and the remaining process 602. The initialization process 601 includes a command line option analysis process 603. In a synchronous mode designation process 604 inside the command line option analysis process 603, a command (synchronous mode designation command) for recording a value indicating the operation mode in a storage area for designating the operation of the synchronous command is executed. FIG. 7 shows an embodiment of the synchronization mode designation processing 604. In the process of FIG. 7, first, in the determination 701, it is checked whether or not the user has specified the command line option -Emergency at the time of starting the application, and if so, the process proceeds to the process 702 and the synchronization mode specification register is used. If the value is set to “emergency” and not specified, the process proceeds to step 703, and the value of the synchronization mode specification register is set to “normal” using a synchronization mode specification command. As a result of executing the processing of FIG. 7, if the user has specified the command line option -Emergency at the time of starting the application, there is a portion forgetting to insert the reading-side synchronization instruction in the processing 602 of FIG. Even so, the software shown in FIG. 6 can perform the same operation as when the reading-side synchronization instruction is properly inserted.

  By utilizing the present invention in the server, it becomes possible to repair software defects.

Communication program between processors Memory reference order in which the problem occurs Computer utilizing the present invention Behavior of synchronous instruction on write side Behavior of synchronous instruction on write side Application software with a function to specify the synchronization mode Synchronization mode specification processing Memory reference order by delay processing

Explanation of symbols

301 Processor 302 Bus 303 Main Memory 304 DVD-ROM Reader 305 DVD-ROM
306 Memory interface 307 Instruction interpretation unit 308 Register group 309 Instruction execution unit 310 Program counter PC
311 Wiring 312 Synchronous instruction execution circuit 313 Wiring 314 Synchronization mode designation register 315 Clock signal line

Claims (7)

A processor having a storage area for specifying an operation of a synchronous instruction used for communication between processors. The processor of claim 1, wherein
A processor having a function of providing an instruction for recording a value in a storage area for designating the operation of the synchronous instruction and executing the instruction. A program for recording a value in a storage area in accordance with an instruction for recording a value in a storage area for designating an operation of a synchronous instruction used for communication between processors of the processor. The processor of claim 1, wherein
A processor having a function of referring to the storage area when executing a synchronous instruction and changing a delay until the execution of the synchronous instruction is completed according to a value recorded in the storage area. The processor of claim 1, wherein
A processor having a function of referring to the storage area and generating a hardware trap according to a value recorded in the storage area when executing a synchronous instruction. The processor of claim 1, wherein
2. The processor according to claim 1, wherein the operation of the synchronization instruction has a plurality of modes, and the number of cycles required for the synchronization processing in each operation mode is different. The processor of claim 1, wherein
The operation of the synchronous command has a plurality of modes, and in one of the operation modes, the number of cycles required for the synchronous processing is variable.

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