JP2005258007A - Manufacturing method of liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a liquid crystal display device having high product yield. <P>SOLUTION: An array substrate provided with a plurality of pixels 26 each includes an SRAM 60 and an SRAM driving circuit constituted of a second thin film transistor 53 having a gate electrode, a semiconductor film and first and second electrodes connected to the semiconductor film and a third thin film transistor 54 is formed. When existence of a defect is inspected by applying driving voltage to each pixel 26 of the array substrate, voltage higher than usually driving voltage is applied to the first electrode of the second thin film transistor 53 which is a constituent of the SRAM driving circuit 50. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a liquid crystal display device.

  In recent years, liquid crystal display devices have been widely used as display devices. Since the liquid crystal display device is small and lightweight, it is used as a display device for a portable electronic device such as a PDA (personal digital assistant), a mobile phone, or a tablet PC (personal computer). For this reason, liquid crystal display devices are required to have low power consumption.

  In general, the liquid crystal display device includes an array substrate, a counter substrate facing the array substrate, and a liquid crystal layer sandwiched between the substrates. The array substrate has a plurality of scanning lines and a plurality of signal lines crossing these scanning lines, and each region surrounded by two adjacent scanning lines and two adjacent signal lines has a pixel. Is formed.

  In each pixel, a thin film transistor (hereinafter referred to as a pixel TFT) as a switching element connected to the scanning line and the signal line, and a pixel electrode are formed. Furthermore, each pixel is formed with an SRAM (Static Random Access Memory) for reducing power consumption and an SRAM driving circuit for connecting the SRAM and the pixel electrode (see, for example, Patent Document 1). ). The pixel TFT is connected to the pixel electrode. The SRAM drive circuit includes a first drive TFT and a second drive TFT for driving connected in parallel to the pixel electrode.

  When an image is displayed using the above-described liquid crystal display device, a specific voltage is applied to the scanning line and the signal line. As a result, the voltage applied to the signal line is applied to the pixel electrode via the pixel TFT. When the SRAM is driven, the SRAM driving circuit operates in a conductive state, so that a voltage is applied to the pixel electrode and also to the SRAM via the SRAM driving circuit.

  The SRAM holds the applied voltage. Therefore, even after the application of the voltage to the signal line is stopped, the SRAM is driven, so that the voltage held by the SRAM is applied to the pixel electrode via the SRAM driving circuit. As described above, when a static image display is performed, the image display can be performed without frequently applying a voltage to the signal wiring, and the power consumption can be reduced.

  Here, a manufacturing method of each TFT will be described. First, a glass substrate is prepared, and a semiconductor film is formed as a channel layer on the glass substrate. Subsequently, after forming a gate insulating film over the glass substrate and the semiconductor film, a gate electrode is formed over the gate insulating film in a region overlapping with the semiconductor film.

Thereafter, an insulating film is formed over the gate insulating film and the gate electrode. Next, contact holes are formed in the gate insulating film and the insulating film overlapping with the semiconductor film. Thereby, two contact holes reaching the source region and the drain region of the semiconductor film are formed. Thereafter, electrodes are formed in the two contact holes, respectively.
JP 2003-228336 A

However, in the step of forming the contact hole of each TFT described above, a thin insulator may adhere to the surface of the source region and the drain region of the semiconductor film. In this case, contact failure occurs where the insulator is attached. Therefore, a minute shortage of on-current for driving the TFT occurs. In the SRAM, there is a problem that due to this small shortage of on-current, charges cannot be held and a point defect is caused when the SRAM is driven.
The present invention has been made in view of the above points, and an object thereof is to provide a method of manufacturing a liquid crystal display device having a high product yield.

  In order to solve the above problems, a method of manufacturing a liquid crystal display device according to an aspect of the present invention includes a pixel electrode, a static memory unit that holds a voltage applied to the pixel electrode, and a pixel electrode and a static memory unit that are connected to each other. A plurality of static memory section driving circuits each including a gate electrode, a channel layer, and a plurality of thin film transistors each having a first electrode and a second electrode connected to the channel layer, connected in parallel In a method of manufacturing a liquid crystal display device having an array substrate including a plurality of pixels, an array substrate including a plurality of pixels including a static memory unit and a static memory unit driving circuit is formed, and a driving voltage is applied to each pixel of the array substrate. Is applied to inspect for the presence of defects, and when inspecting for the presence of defects, The first electrode of the at least one thin film transistor of the plurality of thin film transistors constituting a circuit is characterized by applying a voltage higher than the normal voltage for driving.

  The method of manufacturing a liquid crystal display device according to another aspect of the present invention includes a pixel electrode, a static memory unit that holds a voltage applied to the pixel electrode, and a parallel connection to the pixel electrode and the static memory unit. A plurality of pixels each including a gate electrode, a channel layer, and a static memory unit driving circuit including a plurality of thin film transistors each having a first electrode and a second electrode connected to the channel layer. In a method for manufacturing a liquid crystal display device having an array substrate, an array substrate including a plurality of pixels including a static memory unit and a static memory unit driving circuit is formed, and a driving voltage is applied to each pixel of the array substrate. When the presence of defects is inspected and the presence of defects is inspected, the static memory unit drive circuit is configured. The first electrode of the at least one thin film transistor of the plurality of thin film transistors, is characterized by applying a plurality of times voltage.

  According to the present invention, a method for manufacturing a liquid crystal display device with a high product yield can be provided.

Hereinafter, a method for manufacturing a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to the drawings.
As shown in FIG. 3, the liquid crystal display device includes an array substrate 1, a counter substrate 2 disposed opposite to the array substrate with a predetermined gap, and a liquid crystal layer 3 sandwiched between the two substrates. It is equipped with. The array substrate 1 includes, for example, a glass substrate 10 as a transparent insulating substrate.

  As shown in FIG. 2, on a glass substrate 10, a pixel portion 11, a scanning line driving circuit 12 and a signal line driving circuit 13 located outside the pixel portion, and a plurality of scanning lines extending in the first direction. 21 and a plurality of signal lines 22 extending in a second direction intersecting the first direction are arranged. Each scanning line 21 is connected to the scanning line driving circuit 12, and each signal line 22 is connected to the signal line driving circuit 13.

  A plurality of first polarity switching lines 24 and a plurality of second polarity switching lines 25 connected to the scanning line driving circuit 12 and extending in the first direction are disposed on the glass substrate 10. . A pixel 26 is formed in each region surrounded by two adjacent scanning lines 21 and two signal lines 22.

Next, the pixel 26 will be described.
Each pixel 26 includes a TFT (hereinafter referred to as a first thin film transistor) 30 as a switching element, an auxiliary capacitance element 40, an SRAM 60 as a static memory unit, and an SRAM driving circuit 50 as a static memory unit driving circuit. Have.

  As shown in FIG. 3, the first thin film transistor 30 is configured by, for example, an N-channel thin film transistor having a double gate structure. A semiconductor film 31 made of, for example, polysilicon (p-Si) is formed on the glass substrate 10 as a channel layer, and a gate insulating film 32 is formed on the glass substrate and the semiconductor film. Gate electrodes 33 and 34 are formed on the gate insulating film 32 in a region overlapping with the semiconductor film 31.

On the gate insulating film 32 and the gate electrodes 33 and 34, for example, an insulating film 35 made of SiO ₂ having a high hydrogen content is deposited. A first contact hole 36 reaching the source region Rs of the semiconductor film 31 and a second contact hole 37 reaching the drain region Rd are formed in the gate insulating film 32 and the insulating film 35.

  On the insulating film 35, the first contact hole 36, and the second contact hole 37 formed as described above, the signal line 22 and the contact wiring 39 are formed. The source region Rs of the semiconductor film 31 is connected to the signal line 22, and the drain region Rd thereof is connected to the contact wiring 39. Here, the signal line 22 in the first contact hole 36 is referred to as a first electrode E1, and the contact wiring 39 in the second contact hole 37 is referred to as a second electrode E2.

  As shown in FIGS. 1 and 3, in the first thin film transistor 30 configured as described above, the gate electrodes 33 and 34 are formed by extending a part of the scanning line 21. The drain region Rd (first node n1) of the semiconductor film 31 is connected to the second node n2. The first node n1 is connected to the third node n3 (a pixel electrode 72 described later) via the contact wiring 39 described above. The third node n3 is connected to the auxiliary capacitance element 40 configured by the auxiliary capacitance line 23.

  When the first thin film transistor 30 is driven by a scanning signal (hereinafter referred to as a scanning voltage) from the scanning line 21, a voltage for normal driving (hereinafter referred to as a driving voltage) on the signal line 22 is applied to the pixel electrode 72. It is comprised so that it may apply.

  The auxiliary capacitance element 40 will be described. The capacity of the auxiliary capacitive element is charged and discharged by the drive voltage applied to the pixel electrode 72. When the auxiliary capacitive element 40 holds the driving voltage by this charge / discharge, even when the first thin film transistor 30 is non-conductive during normal driving, the pixel electrode is driven by the driving voltage held by the auxiliary capacitive element. 72 and the potential difference between the counter electrodes 81 described later are maintained.

  As shown in FIG. 1, the SRAM 60 includes a first inverter 61, a second inverter 62, and a fourth thin film transistor 63 as a switching element for controlling a current that loops through these inverters. In this embodiment, the fourth thin film transistor 63 is a P-channel thin film transistor, and its gate electrode is formed by extending a part of the scanning line 21.

  When the scanning voltage from the scanning line 21 is at the H (high) level, the fourth thin film transistor 63 is not conductive during the period in which the first thin film transistor 30 is conductive. The fourth thin film transistor 63 becomes conductive when the scanning voltage is at L (low) level.

  The sixth node n6 is connected to the input terminal of the first inverter 61, and the output terminal of the first inverter is connected to the input terminal of the second inverter 62 via the seventh node n7. The output terminal of the second inverter 62 is connected to the input terminal of the first inverter 61 via the fourth thin film transistor 63 controlled by the scanning voltage.

  The SRAM drive circuit 50 includes a first drive unit 51 and a second drive unit 52. In this embodiment, the first driving unit 51 includes a second thin film transistor 53 as an N-channel thin film transistor having a double gate structure, and the second driving unit 52 is also a third N channel thin film transistor having a double gate structure. A thin film transistor 54 is used. Here, the second thin film transistor 53 and the third thin film transistor 54 are configured in the same manner as the first thin film transistor 30 described above.

  The gate electrode of the second thin film transistor 53 is formed by extending a part of the first polarity switching line 24. The gate electrode of the third thin film transistor 54 is formed by extending a part of the second polarity switching line 25.

  The second thin film transistor 53 is connected to the second node n2 and the sixth node n6, and the third thin film transistor 54 is connected to the second node n2 and the seventh node n7, respectively. As described above, the second thin film transistor 53 and the third thin film transistor 54 are connected to the pixel electrode 72 and the SRAM 60 in parallel with each other.

  The SRAM drive circuit 50 controls the electrical connection between the pixel electrode 72 and the SRAM 60 and also contributes to the control of the output polarity of the drive voltage held in the SRAM. In the still image display mode, the second thin film transistor 53 and the third thin film transistor 54 are controlled by, for example, alternately applying an H level voltage to the first polarity switching line 24 and the second polarity switching line 25 every frame. The Here, one frame is a time from when all the pixels are sequentially scanned and the same pixel is scanned again.

  As shown in FIGS. 2 and 3, a colored layer 71 is formed in the pixel portion 11 on the glass substrate 10 on which a plurality of thin film transistors, auxiliary capacitance elements 40, SRAM driving circuits 50, SRAM 60, and various wirings are formed. Has been. A pixel electrode 72 is formed of a transparent conductive film such as ITO (Indium Tin Oxide) on the colored layer 71 in a region surrounded by two adjacent scanning lines 21 and two signal lines 22. .

  Here, it goes without saying that the pixel electrode 72 is connected to the first thin film transistor 30 via the contact wiring 39 and also connected to the auxiliary capacitance element 40 and the SRAM drive circuit 50. An alignment film 73 is formed on the coloring layer 71 and the pixel electrode 72.

  On the other hand, the counter substrate 2 includes, for example, a glass substrate 80 as a transparent insulating substrate. On the glass substrate 80, a counter electrode 81 made of a transparent conductive film such as ITO and an alignment film 82 are sequentially formed.

  The array substrate 1 and the counter substrate 2 are arranged to face each other with a predetermined gap held by a plurality of spacers (not shown), and are joined by a seal material (not shown) disposed on the periphery of the pixel portion 11. A liquid crystal layer 3 is formed in a region surrounded by the array substrate 1, the counter substrate 2, and the sealing material. Note that the liquid crystal injection port formed in a part of the sealing material is sealed with a sealing material (not shown). A backlight (not shown) is disposed on the outer surface side of the array substrate 1. The liquid crystal display device is configured as described above.

Next, the operation of the above-described liquid crystal display device will be described.
First, a normal display mode in which an image is displayed without using the SRAM 60 will be described.
First, in a state where the first polarity switching line 24 and the second polarity switching line 25 are maintained at the L level, the scanning line driving circuit 12 sequentially applies the scanning voltage to the plurality of scanning lines 21 every frame period. Each scanning line 21 is maintained at the H level or the L level for one horizontal scanning period by the scanning voltage. The signal line driving circuit 13 applies a driving voltage for one row whose level is inverted every horizontal scanning period to each of the plurality of signal lines 22.

  The first thin film transistor 30 is turned on by the H level scanning voltage from the corresponding scanning line 21, takes in the driving voltage applied to the corresponding signal line 22, and applies it to the pixel electrode 72. When the first thin film transistor 30 is turned off after one horizontal scanning period and the pixel electrode 72 is brought into an electrically floating state, the drive voltage is held by the auxiliary capacitance element 40 until the first thin film transistor is turned on again. As a result, image display is performed using the voltage held by the auxiliary capacitive element 40.

Next, a still image display mode for displaying an image using the SRAM 60 will be described.
When shifting to the still image display mode, first, the first polarity switching line 24 is maintained at the H level for the still image writing period which is the first one frame period, and the second polarity switching line 25 is maintained at the L level. As described above, the signal voltage 22 is applied for each horizontal scanning period in the frame period while the driving voltage for the still image is maintained at the H level or the L level.

  In the subsequent still image holding period, an H level voltage is alternately applied to the first polarity switching line 24 and the second polarity switching line 25 every frame period in order to invert the output polarity of the SRAM 60.

  As described above, in the first frame period corresponding to the still image writing period in the still image display mode, the H level voltage is applied to the first polarity switching line 24 and the first polarity switching line is maintained at the H level. A driving voltage corresponding to binary still image information is applied to the pixel electrode 72 via the first thin film transistor 30 and to the SRAM 60 via the second thin film transistor 53.

  In the still image holding period, for example, when an L level voltage is applied to the first polarity switching line 24 and an H level voltage is applied to the second polarity switching line 25, the drive voltage described above is inverted by the first inverter 61 and output driven. A voltage is applied to the pixel electrode 72 via the third thin film transistor 54. As described above, the display characteristics can be stabilized by alternately applying H level and L level voltages to the pixel electrode 72 during the still image display mode.

Next, a normal display mode and a still image display mode when an L level drive voltage is applied to the signal line 22 will be described.
In a state where an L level voltage is applied to the first polarity switching line 24 and the second polarity switching line 25, an H level scanning voltage is applied to the scanning line 21, and the first thin film transistor 30 becomes conductive. For this reason, the L level drive voltage applied to the signal line 22 is applied to the pixel electrode 72 via the first thin film transistor 30.

  Further, an L level driving voltage is applied to the first inverter 61 by applying an H level voltage to the first polarity switching line 24 and making the second thin film transistor 53 conductive. Thereafter, an L level scanning voltage is applied to the scanning line 21 to make the first thin film transistor 30 non-conductive, and at the same time, the fourth thin film transistor 63 is made conductive. As a result, the first inverter 61 and the second inverter 62 start storing and storing the L-level drive voltage applied to the pixel electrode 72, and thus enter the still image display mode (SRAM drive mode). Thereby, image display is performed using the voltage stored and held in the SRAM 60.

Next, a method for manufacturing the above-described liquid crystal display device will be described.
As shown in FIG. 3, first, a glass substrate 10 is prepared, and film formation and patterning are repeated on the prepared glass substrate to form a first thin film transistor 30 and various wirings.

  More specifically, the semiconductor film 31 is formed on the glass substrate 10. Subsequently, after forming a gate insulating film 32 on the glass substrate 10 and the semiconductor film 31, gate electrodes 33 and 34 are formed on the gate insulating film in a region overlapping with the semiconductor film. Thereafter, an insulating film 35 is formed on the gate insulating film 32 and the gate electrodes 33 and 34. Next, a first contact hole 36 and a second contact hole 37 are formed in the gate insulating film 32 and the insulating film 35 overlapping with the semiconductor film 31.

  When forming the first contact hole 36 and the second contact hole 37 of each thin film transistor, the insulating film 35 containing hydrogen is removed by using a dry etching method. Examples of the dry etching method include a method of removing the insulating film 35 by irradiating an ion beam.

  When the dry etching method is used as described above, the residue of the insulating film 35 may become an insulator 38 and adhere to the source region Rs and the drain region Rd of the semiconductor film 31 as shown in FIG.

  Thereafter, the first electrode E1 is formed in the first contact hole 36, and the second electrode E2 is formed in the second contact hole 37. Therefore, when the insulator 38 is attached as described above, for example, in the first thin film transistor 30, the actual signal line 22 is connected to the semiconductor film 31 through the insulator 38. A contact wiring 39 (not shown) is also connected to the semiconductor film 31 through an insulator 38. As a result, contact failure occurs at the connection point between the semiconductor film 31 and the signal line 22 and the contact wiring 39. When the first thin film transistor 30 is formed, other thin film transistors such as the second thin film transistor 53 and the third thin film transistor 54 are formed at the same time.

  Needless to say, the insulator 38 is not limited to the first thin film transistor 30 and may adhere to other thin film transistors such as the second thin film transistor 53 and the third thin film transistor 54. Next, as shown in FIG. 3, the array substrate 1 is completed by sequentially forming the colored layer 71, the pixel electrode 72, and the alignment film 73 on the glass substrate 10.

  Here, the point that contact failure occurs in the thin film transistor will be described. When forming each thin film transistor, for example, the first thin film transistor 30, the first contact hole 36 and the second contact hole 37 are formed by dry etching the insulating film 35. For this reason, when the dry etching method is used, the insulator 38 may adhere to the semiconductor film 31. The above is peculiar to the dry etching method, and the insulator 38 does not adhere to the semiconductor film 31 when the wet etching method is used. Further, when the insulating film 35 contains hydrogen, the insulator 38 often adheres to the semiconductor film 31 due to the nature of hydrogen that is easily recombined.

On the other hand, the counter substrate 2 is completed by preparing the glass substrate 80 in the counter substrate 2 and sequentially forming the counter electrode 81 and the alignment film 82 on the prepared glass substrate.
Next, a sealing material is applied to the peripheral edge of the pixel portion 11 of the array substrate 1. When this sealing material is applied, it is applied except for the liquid crystal injection port. Subsequently, the array substrate 1 and the counter substrate 2 are arranged to be opposed to each other while holding a predetermined gap with a plurality of spacers, and the array substrate 1 and the counter substrate 2 are bonded together with a sealing material.

  Next, after injecting liquid crystal from a liquid crystal injection port formed in a part of the sealing material, the liquid crystal injection port is sealed. As a result, the liquid crystal is sealed between the array substrate 1 and the counter substrate 2 to form the liquid crystal layer 3. Thereafter, a backlight is disposed on the outer surface side of the array substrate 1.

As a process of the manufacturing process, the above-described pixel 26 is inspected for defects, and if there is a point defect, a repair process is performed.
In the inspection process, first, normal display is performed on the scanning line 21, the signal line 22, the auxiliary capacitance line 23, the first polarity switching line 24, and the second polarity switching line 25 through the scanning line driving circuit 12 and the signal line driving circuit 13, respectively. A voltage for mode is applied to charge the pixel 26 with electric charge.

  Then, the presence or absence of point defects in each pixel 26 is inspected. More specifically, each pixel 26 except for the SRAM drive circuit 50 and the SRAM 60 is inspected for defects. When charging each pixel 26, for example, a black display voltage is applied. Thus, each pixel 26 is displayed in black, but the defective pixel is displayed in white because light from the backlight is lost. Therefore, for example, the presence or absence of the defective pixel 26 can be determined by viewing the pixel unit 11 (display screen) in the normal display mode.

  When the insulator 38 is attached on the semiconductor film 31 of the first thin film transistor 30, it is considered that the pixel 26 to which the insulator is attached becomes a defective pixel in the normal display mode. However, since the insulator 38 is thin, its electrical resistance is low. Therefore, even when the insulator 38 is attached to the first thin film transistor 30, the pixel 26 to which the insulator is attached does not become a defective pixel in the normal display mode.

  In this embodiment, it is assumed that each pixel 26 has no point defect. Needless to say, when a defective pixel 26 is detected in the normal display mode, it is repaired in this repair process.

  Subsequently, the scanning line 21, the signal line 22, the auxiliary capacitance line 23, the first polarity switching line 24, and the second polarity switching line 25 are used for the still image display mode through the scanning line driving circuit 12 and the signal line driving circuit 13, respectively. Is applied to charge the pixel 26 with electric charges.

  Then, the driving state of the SRAM 60 is inspected. When charging each pixel 26, first, an H level scanning voltage is applied to the scanning line 21, an H level voltage is applied to the first polarity switching line 24, and an L level voltage is applied to the second polarity switching line 25. As a result, an H level voltage is applied to the gate electrode of the first thin film transistor 30 and the gate electrode of the second thin film transistor 53, and the first thin film transistor and the second thin film transistor are turned on.

  In this state, for example, an L level voltage is applied to the signal line 22 as a drive voltage. Thus, the L level voltage applied to the signal line 22 is applied to the input terminal of the first inverter 61 via the first thin film transistor 30 and the second thin film transistor 53.

  After that, the SRAM 60 stores and holds the L level voltage by inverting the scanning voltage from the H level to the L level. The L level voltage stored and held in the SRAM 60 is applied to the pixel electrode 72 via the second thin film transistor 53.

  As described above, in the still image display mode, an L level voltage is applied to the pixel electrode 72, and a potential difference is generated between the pixel electrode and the counter electrode 81, so that white display is performed. As a result, each pixel 26 is displayed in white, but only defective pixels are displayed in black. Therefore, in the still image display mode, for example, the presence or absence of the defective pixel 26 can be determined by viewing the pixel unit 11 (display screen). Therefore, when the presence or absence of the defective pixel 26 is determined in the still image display mode, 12 defective pixels are detected in the pixel portion 11.

  Here, when the insulator 38 is attached on the semiconductor film 31 of the second thin film transistor 53 constituting the first drive unit 51, the pixel 26 to which the insulator is attached becomes a defective pixel in the still image display mode. Can be considered. That is, when the drive voltage is applied to the first inverter 61, if the second thin film transistor 53 is in a minute contact failure state, it is difficult to apply a sufficiently low drive voltage to the input terminal of the first inverter 61. is there. This may cause a display defect in the still image display mode (SRAM drive mode).

  When a defective pixel is detected in the still image display mode, a voltage of, for example, 10 V is instantaneously applied to the signal line 22 as a voltage higher than the normal drive voltage (5 V) while the first thin film transistor 30 and the second thin film transistor 53 are conductive. Apply the power. As a result, a voltage higher than the normal driving voltage is applied to the first electrode E1 of the second thin film transistor 53 in the conductive state, and a higher voltage is also applied to the second electrode E2 connected through the semiconductor film 31. .

Thereafter, for example, an L-level voltage is applied to the signal line 22 as a drive voltage in a state where the first thin film transistor 30 and the second thin film transistor 53 are conductive. As a still image display mode, the presence / absence of the defective pixel 26 was determined again, and 7 defective pixels out of 12 defective pixels detected by the pixel unit 11 were normalized.
Through the above process, the repair process is completed, and a liquid crystal display device is obtained.

  According to the method of manufacturing a liquid crystal display device configured as described above, a voltage higher than the normal drive voltage is instantaneously applied to the first electrode E1 and the second electrode E2 of the second thin film transistor 53 in the conductive state. Yes. For this reason, electrons are filled in the plurality of holes in the insulator 38 of the second thin film transistor 53. As a result, defective pixels due to contact failure of the second thin film transistor 53 are normalized. Since the normalized pixel 26 is semipermanently normal, a good image display can be performed in the still image display mode.

  When inspecting the driving state of the SRAM 60, the presence or absence of defects in each of the pixels 26 excluding the SRAM driving circuit 50 and the SRAM is inspected. Therefore, each pixel 26 and the driving state of the SRAM 60 can be inspected at the same time. Thereby, a liquid crystal display device can be manufactured efficiently.

  In the above-described embodiment, when a voltage higher than the voltage for normal driving is applied to the signal line 22, a voltage of 10V is applied. However, a voltage of 7V to 20V, more preferably 7V to 17V may be applied. . As a result, the voltage applied to the signal line 22 is also applied to the second thin film transistor 53 via the first thin film transistor 30, and the defective pixel due to the contact failure is normalized.

  When a voltage is applied to the gate electrodes of the first thin film transistor 30 and the second thin film transistor 53 to make them conductive, a voltage higher than the voltage normally applied to these gate electrodes may be applied. As a result, it is possible to supply a voltage to the first thin film transistor 30 and the second thin film transistor 53 in a state where the drive voltage applied to the signal line 22 is further maintained.

Here, in the still image display mode, if the voltage applied to the gate electrode of the second thin film transistor 53 is increased, the drive voltage is stored and retained in the SRAM 60, and the pixel electrode 72 is also good through the second thin film transistor. Can be applied. However, when a high voltage is constantly applied to the gate electrode, there is a risk of causing gate breakdown. For this reason, when a voltage higher than a normal voltage is applied to the gate electrode, it may be applied until the display defect in the still image display mode is eliminated in the manufacturing process.
As described above, a method for manufacturing a liquid crystal display device having a high manufacturing yield can be provided.

  The present invention is not limited to the above-described embodiment, and can be variously modified within the scope of the present invention. For example, in the above-described embodiment, a voltage higher than the voltage for normal driving is applied to the second thin film transistor 53 only once through the signal line 22, but it may be applied a plurality of times to display a still image. It may be applied until the display failure in the mode is resolved. As described above, when a voltage is applied to the second thin film transistor 53 a plurality of times via the signal line 22, even when a normal driving voltage is applied, it is effective in eliminating display defects in the still image display mode. It is.

  Here, when applying a voltage higher than the voltage for normal driving a plurality of times, normalization of the defective pixel due to the contact failure of the second thin film transistor 53 is monitored (for example, by visually observing the display screen, the defective pixel is detected). Therefore, the normal driving voltage and the voltage higher than the normal driving voltage may be alternately cycled and applied to the signal line 22. For this reason, when each pixel 26 and the driving state of the SRAM 60 are inspected at the same time, they can be inspected alternately. Here, as described above, when a voltage is applied to the second thin film transistor 53 a plurality of times, a voltage of 5 V (normal drive voltage) to 20 V may be applied.

  When inspecting the driving state of each pixel 26 and the SRAM 60, not only the visual inspection described above but also an electrical inspection may be performed. When electrically inspecting, it is also possible to inspect before joining the array substrate 1 and the counter substrate 2.

  In the above embodiment, the case where the second thin film transistor 53 is normalized has been described. However, the case where the third thin film transistor 54 is normalized is also effective for the still image display mode. This is effective when a voltage is applied to the third thin film transistor 54 in the still image display mode.

  The first driving unit 51 and the second driving unit 52 are each configured by a thin film transistor having a double gate structure, but these may be configured by arranging two thin film transistors in series, or by a single thin film transistor. You may do it.

The figure which showed the equivalent circuit of the pixel of the liquid crystal display device which concerns on embodiment of this invention. FIG. 2 is a diagram illustrating a circuit configuration of the liquid crystal display device illustrated in FIG. 1. 1 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention. FIG. 4 is an enlarged view showing a part of a contact hole of the liquid crystal display device shown in FIG. 3.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Counter substrate, 3 ... Liquid crystal layer, 10 ... Glass substrate, 11 ... Pixel part, 21 ... Scanning line, 22 ... Signal line, 24 ... 1st polarity switching line, 25 ... 2nd polarity switching line , 26 ... pixel, 30 ... first thin film transistor, 31 ... semiconductor film, 33 and 34 ... gate electrode, 35 ... insulating film, 36 ... first contact hole, 37 ... second contact hole, 38 ... insulator, 50 ... SRAM Driving circuit 53... Second thin film transistor 54... Third thin film transistor 60... SRAM 61. First inverter 62. Second inverter 63. Fourth thin film transistor 72. 1 electrode, E2 ... second electrode, Rs ... source region, Rd ... drain region.

Claims (9)

A pixel electrode, a static memory unit that holds a voltage applied to the pixel electrode, and the pixel electrode and the static memory unit are connected in parallel to each other, and are connected to the gate electrode, the channel layer, and the channel layer, respectively. In a method of manufacturing a liquid crystal display device having an array substrate including a plurality of pixels, including a static memory unit driving circuit configured by a plurality of thin film transistors having a first electrode and a second electrode,
Forming an array substrate including a plurality of pixels including a static memory unit and a static memory unit driving circuit;
Inspecting the presence or absence of defects by applying a driving voltage to each pixel of the array substrate,
A liquid crystal characterized by applying a voltage higher than a normal driving voltage to a first electrode of at least one thin film transistor of the plurality of thin film transistors constituting the static memory unit driving circuit when inspecting for the presence or absence of the defect. Manufacturing method of display device.   2. The method of manufacturing a liquid crystal display device according to claim 1, wherein when applying a voltage higher than the voltage for normal driving, a voltage of 7 to 20 volts is applied.   2. The method of manufacturing a liquid crystal display device according to claim 1, wherein when applying a voltage higher than the voltage for normal driving, a voltage is applied to the gate electrode of the thin film transistor and applied in a conductive state. A pixel electrode, a static memory unit that holds a voltage applied to the pixel electrode, and the pixel electrode and the static memory unit are connected in parallel to each other, and are connected to the gate electrode, the channel layer, and the channel layer, respectively. In a method of manufacturing a liquid crystal display device having an array substrate including a plurality of pixels, including a static memory unit driving circuit configured by a plurality of thin film transistors having a first electrode and a second electrode,
Forming an array substrate including a plurality of pixels including a static memory unit and a static memory unit driving circuit;
Inspecting the presence or absence of defects by applying a driving voltage to each pixel of the array substrate,
A method of manufacturing a liquid crystal display device, comprising: applying a voltage a plurality of times to a first electrode of at least one thin film transistor of the plurality of thin film transistors constituting the static memory unit driving circuit when inspecting the presence or absence of the defect.   5. The method of manufacturing a liquid crystal display device according to claim 4, wherein when the voltage is applied a plurality of times, a voltage of 5 to 20 volts is applied.   5. The method of manufacturing a liquid crystal display device according to claim 4, wherein, when the voltage is applied a plurality of times, a voltage is applied to the gate electrode of the thin film transistor to apply it in a conductive state.   The liquid crystal display device according to claim 3 or 6, wherein when a voltage is applied to the gate electrode of the thin film transistor to make it conductive, a voltage higher than a voltage normally applied to the gate electrode is applied. Method. When forming the array substrate, a substrate is prepared, the channel layer is formed on the substrate, an insulating film is formed on the substrate and the channel layer,
After forming the insulating film, contact holes reaching the channel layer are formed in two places in the insulating film using a dry etching method,
The plurality of thin film transistors are formed by forming the first electrode connected to the channel layer in one contact hole and forming the second electrode connected to the channel layer in the other contact hole. 5. The method of manufacturing a liquid crystal display device according to claim 1, wherein an array substrate is formed. When forming the plurality of thin film transistors, a contact hole reaching the channel layer is formed in the insulating film using a dry etching method,
When forming the first electrode and the second electrode, each of the plurality of thin film transistors is formed by forming the first electrode and the second electrode on the insulator attached on the channel layer,
The application of the voltage to the first electrode of the thin film transistor causes the plurality of holes in the insulator attached in the contact hole to be filled with electrons by applying the voltage to the first electrode of the thin film transistor. Item 9. A method for manufacturing a liquid crystal display device according to Item 8.

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