JP2005252953A - Crossbar switch and network transfer apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent performance from being deteriorated when an interface of a transfer capability different from that of a crossbar switch is coupled. <P>SOLUTION: A crossbar switch 35 transfers a packet inside a router. A cell inputted from a packet transfer engine or the like of throughput of a lower speed than the inside of the crossbar switch via a port 131 is held in a reception buffer 132. Reading from the reception buffer 132 is managed by a reception buffer management section 133. The reception buffer management section 133 judges whether or not a cell is to be read from the reception buffer 132 according to the number of final cells and the number of cells held by a threshold register 137 and the reception buffer 132. Cells input from a low-speed packet transfer engine or the like are held in the reception buffer 132 by a required number and then transferred or transferred after a final cell is held, thereby improving crossbar switch use efficiency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a crossbar switch and a network transfer device, and more particularly to a crossbar switch and a network transfer device that enable highly efficient buffer management in a network configured by combining a packet transfer engine and a crossbar switch having different transfer capabilities. .

  In general, in a network transfer apparatus, a plurality of packet transfer engines are connected via a crossbar switch to transfer a packet. The packet is transmitted after being divided into a set of data of a certain size called a cell, and is reconstructed into a packet by a packet transfer engine as a transfer destination. At this time, cells of different packets arrive in a mixed manner, or if cells arrive in the same packet in a different order, the overhead at the time of packet reconstruction increases. A packet transfer method is employed in which a transfer path from the transmission port to the reception port is secured when passing, and the secured transfer path is not released until the last cell of the packet passes.

  In a network transfer apparatus that performs control of such a packet transfer method, even if a packet transfer apparatus and a crossbar switch having the same transfer capability are connected, it is particularly difficult to limit both capabilities. However, for example, if a packet transfer engine having a low transfer capability is connected to a crossbar switch having a high transfer capability, the performance of the crossbar switch having a high transfer capability is limited to the performance of the packet transfer engine having a low transfer capability. This limitation affects the performance of the entire network transfer device.

  FIG. 5 shows a model of the crossbar switch. The crossbar switch 200 includes a plurality of reception buffers 132 and a switch 135 that selects and outputs the reception buffer 132. In a crossbar switch with an internal throughput of 2A, the packet transfer of the throughput A to one of the reception buffers 132 The example which connected the engine 45 is shown. The conventional crossbar switch 300 connected in this way cannot exhibit the capability of the throughput 2A, and the packet transfer efficiency of the other packet transfer engines 15 of the throughput 2A also decreases.

6 to 8 are diagrams showing a conventional packet transfer example (a) and a packet transfer example (b) of the present invention.
FIG. 6A shows an example in which a packet having a packet length equal to or smaller than the number of cells that can be held in the reception buffer 132 is transferred from the packet transfer engine 45. 7A and 8A show an example in which a packet having a packet length equal to or larger than the number of cells that can be held in the reception buffer 132 has been transferred from the packet transfer engine 45. FIG. FIG. 6B, FIG. 7B, and FIG. 8B will be described in detail later.

  6A, FIG. 7A, and FIG. 8A, the cells transferred from the packet transfer engine 45 having a low transfer capability (for example, throughput A) are held in the reception buffer 132. If the data is transferred to the output of the crossbar switch 300 having a high transfer capability (for example, a throughput of 2A), the crossbar switch 300 cannot make use of the original transfer capability and can only transfer with a gap between cells. Disappear. That is, although the crossbar switch 300 has a transfer capability of throughput 2A, in this case, cells are transferred at throughput A.

  For this reason, the occupied time of this line becomes long, and there is a long state in which transfer capacity is high in other reception buffers 132 (for example, throughput is 2A) and transfer is not possible even when a packet from another packet transfer engine 15 arrives. As a result, the performance of the entire network transfer device is degraded.

A determination means for determining whether or not untransmitted data read from the storage device is of a specified size in a data transmission device that reads data from the storage device into a buffer and transmits the data to another device; A data transmission device is disclosed that includes a transmission unit that transmits data of a specified size as a determination target to another device while adding header information each time the determination unit determines arrival at the specified size. (For example, refer to Patent Document 1).
JP-A-8-101818

  When a packet transfer engine and a switch having different transfer capacities are used in the same network transfer apparatus, the performance of the crossbar switch having a high transfer capability may be limited by the performance of the packet transfer engine having a low transfer capability. In order to improve the efficiency of packet transfer within a network transfer device, it is desirable that the packet transfer engine and crossbar switch with high transfer capability can exhibit their original performance without being limited by the performance of the packet transfer engine with low transfer capability. It is.

  In the conventional network transfer device, since the cells that have entered the buffer holding the packet provided at each port of the crossbar switch are sequentially transferred, the packet transfer from the packet transfer engine with a low transfer capability is the original transfer of the switch. Capabilities are limited. Further, when the packet transfer destination is a packet transfer engine having a high transfer capability, the capability of the packet transfer engine cannot be exhibited.

  The data transmission device disclosed in Patent Document 1 does not have a determination corresponding to the last cell, and determines the end of data transfer by comparison with a predetermined total data amount. Further, the size of data to be centrally transferred (processing unit size) is a predetermined size. The network described in Patent Document 1 is assumed to be able to multiplex and transfer a plurality of transfers between data transfer apparatuses. For example, if the transfer from the device A to the device B is X and the transfer from the device C to the device D is Y, it is assumed that the transfer can be alternately performed on the network like XYXYXY. In the above packet transfer method in which a plurality of packets are prohibited from entering and mixing on the same transmission line, it is difficult to perform efficient packet transfer using the transfer device described in Patent Document 1.

  For example, in the method described in Patent Document 1, data transmission overlaps with data read from the storage unit, so that the time from data read to data transmission completion is shortened. In the time from the start to the end, there is a gap between data transfers. In other words, the line occupation time from the start to the end of data transmission is not significantly shortened even when applied to a packet transfer method that does not release the transfer path secured until the last cell of the packet passes.

  In view of the above, the present invention suppresses the performance deterioration of a packet transfer engine and a crossbar switch having a high transfer capability even when a packet transfer engine and a crossbar switch having different transfer capabilities are used in the same network transfer device. An object of the present invention is to provide a crossbar switch and a packet transfer apparatus for increasing or maximizing the efficiency.

  The present invention provides a network transfer apparatus having the following configuration as a buffer control method for reducing a decrease in transfer capability of a crossbar switch having a high transfer capability when a packet transfer engine having a low transfer capability is connected to a crossbar switch having a high transfer capability. can do.

According to the first solution of the present invention,
A crossbar switch in a packet transfer system that secures a transfer path from a first port to a second port from the passage of a leading cell to the passage of a final cell of a packet having a plurality of cells,
A receive buffer holding each cell of the received packet;
A reception buffer management unit for controlling transfer of cells or packets held in the reception buffer;
The destination port of the packet is determined according to the output route information contained in the received packet or the output route information obtained based on the packet header information, and the cell or packet read from the reception buffer is determined. And a switch for forwarding to
The reception buffer management unit includes:
Detecting the writing of the last cell to the receiving buffer and outputting a signal for transferring the packet or cell; and detecting the reading of the last cell from the receiving buffer to stop the transfer of the packet or cell;
Even if it is not possible to detect the writing of the last cell to the reception buffer, if the number of cells held in the reception buffer is greater than or equal to a predetermined threshold, a signal for transferring a packet or cell is output, In addition, the crossbar switch for detecting the reading of the last cell from the reception buffer and stopping the packet or cell transfer is provided.

According to the second solution of the present invention,
In a packet transfer system that secures a transfer path from the first port to the second port from the passage of the first cell to the passage of the last cell of a packet having a plurality of cells, the same or almost the same transfer capability as that of the own crossbar switch A crossbar switch to be connected to a device having a lower transfer capability than the own crossbar switch,
A first receive buffer for holding each cell of a packet received from a device having the same or substantially the same transfer capability as the own crossbar switch;
A first reception buffer management unit corresponding to the first reception buffer, which controls transfer of cells or packets held in the first reception buffer;
A second receive buffer for holding each cell of a packet received from a device having a lower transfer capability than the own crossbar switch;
A second reception buffer management unit corresponding to the first reception buffer, which controls transfer of cells or packets held in the second reception buffer;
The destination port of the packet is determined according to the output route information included in the received packet or the output route information obtained based on the packet header information, and read from the first and second reception buffers. A switch for forwarding a cell or packet to a determined port;
When a signal for transferring a packet or cell output from the first and second reception buffer managers is input, the signal is held in the first and second reception buffers according to the transfer priority of the cell or packet. An arbitration circuit that sequentially sends cells or packets to the switch to transfer the cells or packets,
The first and second reception buffer managers are respectively
Detecting the writing of the last cell to the corresponding first and second receive buffers, outputting a signal for transferring a packet or cell, and the final from the corresponding first and second receive buffers Detect cell read and stop packet or cell transfer,
Even if the writing of the last cell to the corresponding first and second reception buffers cannot be detected, the number of cells held in the corresponding first and second reception buffers is the first and second When the threshold is equal to or higher than the first or second threshold corresponding to the reception buffer, a signal for transferring the packet or the cell is output, and the final cell is read from the corresponding first and second reception buffers. The crossbar switch is provided to detect packet and stop the packet or cell transfer.

According to the third solution of the present invention,
A plurality of packet transfer units having a sub crossbar switch configured by the crossbar switch;
A first packet transfer engine connected to any one of the sub crossbar switches and the line, for transferring a packet from the line to the sub crossbar switch, and sending a packet from the sub crossbar switch to the line; A plurality of line compatible units;
The crossbar switch, a device management processing unit for managing the entire device, and a second packet transfer engine for transferring a packet between the crossbar switch and the device management processing unit, and the plurality of packets A device management unit for transferring packets between the transfer unit and each of the second packet transfer engines;
A network transfer apparatus is provided in which at least one transfer capability of the first packet transfer engine and the second packet transfer engine is lower than the packet transfer capability of the connected crossbar switch or the sub crossbar switch.

  According to the present invention, even if a packet transfer engine and a crossbar switch having different transfer capacities are used in the same network device, performance degradation can be reduced. Especially when the reception buffer of the port of the crossbar switch connected to the packet transfer engine with low transfer capability has the same number of buffer planes as the maximum number of cells of the received packet, the transfer capability of the crossbar switch is reduced. It is possible to operate without.

  FIG. 1 is a schematic diagram of a network transfer apparatus. The network transfer apparatus includes a line correspondence unit 10 (NIF, Network Interface), a packet transfer unit 20 (PPU, Packet Processing Unit), and a device management unit 30 (RM, Routing Manager). The line corresponding unit 10 includes a packet forwarding engine 15 (PFP, Packet Forwarding Processor). The packet transfer unit 20 includes a sub crossbar switch 25 (Sub Crossbar Switch), a route search engine 26 (RCTL, Routing Control Processor), and a bus selection circuit 27 (BUSSEL, BUS Selector). The device management unit 30 includes a crossbar switch 35 (Crossbar Switch), a packet transfer engine 36 (PFP), and a device management CPU 37 (RM-CPU, Routing Manager CPU). Note that the network transfer apparatus is an example of a redundant redundant configuration including the active and standby system management units 30.

  The line corresponding unit 10 receives a packet from the line and transmits it to the packet transfer unit 20. When the packet transfer engine 15 of the line corresponding unit 10 receives a packet from the line, it extracts the output route information of the packet and transmits it to the route search engine 26 of the packet transfer unit 20. The packet transfer engine 15 (first packet transfer engine) stores the received packet in an appropriate buffer. When receiving the output route information indicating the packet transfer destination from the route search engine 26, the packet transfer engine 15 sets the output route information as a part of the corresponding packet stored in the buffer, and sends the packet to the sub crossbar switch 25. Send. Further, when receiving a packet from the sub crossbar switch 25, the packet transfer engine 15 outputs the packet to the line according to the output route information in the packet.

  The packet transfer unit 20 searches for the packet transfer destination from the header information of the packet received by the line corresponding unit 10, and transfers the packet to the transfer destination. The route search engine 26 of the packet transfer unit 20 stores, for example, output route information indicating a packet transfer destination corresponding to a destination address. For example, the route search engine 26 searches the output route information based on the destination address in the packet header received from the packet transfer engine 15, and sends the output route information to the packet transfer engine 15. As the output route information, for example, appropriate identification information indicating an output sub crossbar switch, an output packet transfer engine, and an output line can be used.

  The sub crossbar switch 25 transfers the packet including the output route information received from the packet transfer engine 15 to the output route according to the output route information designated by the route search engine 26. Further, the sub crossbar switch 25 receives the packet including the output route information from the crossbar switch 35 and transmits the received packet including the output route information to the packet transfer engine 15 according to the output route information. The sub crossbar switch 25 is selectively connected to the crossbar switch 35 of the active and standby device management units 30 by an internal selector. In addition, the sub crossbar switch 25 includes ports for connecting to different types of packet transfer engines (for example, different transfer capacities), and uses these ports according to the packet transfer engine so that different packet transfer engines can be used. Can be connected.

  The bus selection circuit 27 selects a bus (BUS) connected to the device management unit 30. The bus selection circuit 27 normally selects a bus connected to the active device management unit 30, and selects the bus connected to the standby system when the device management unit 30 switches to the standby system. The sub crossbar switch 25, the route search engine 26, and the packet transfer engine 15 of the line corresponding unit 10 can transmit and receive data to and from the device management CPU 37 via the bus selected by the bus selection circuit 27.

  The device management unit 30 is preset as an active system or a standby system, and manages network transfer devices. The crossbar switch 35 of the device management unit 30 transfers the packet to and from the sub crossbar switch 25 of the packet transfer unit 20. When the crossbar switch 35 receives the packet including the output route information from the sub crossbar switch 25, the crossbar switch 35 outputs the output route to the sub crossbar switch 25 or the packet transfer engine (second packet transfer engine) 36 corresponding to the output route information. Forward packets that contain information. In addition, the crossbar switch 35 of the device management unit 30 transfers the packet to and from the packet transfer engine 36 of the device management unit 30. When the crossbar switch 35 receives the packet including the output route information created by the device management CPU 37 from the packet transfer engine 36, the crossbar switch 35 sends the output route information to the sub crossbar switch 25 or the packet transfer engine 36 according to the output route information. Forward packets that contain The crossbar switch 35 and the sub crossbar switch 25 can use the crossbar switch 35 having the same structure.

  For example, the device management CPU 37 distributes route information to the route search engine 26 via the crossbar switch 35, the sub crossbar switch 25, and the packet transfer engine 15. Also, a system switching procedure for switching to the standby system is executed when a failure occurs in the device set as the active system. A signal in the system switching procedure is transmitted to the entire apparatus via the bus.

  FIG. 2 is a diagram illustrating a configuration example of a network transfer apparatus having a duplex configuration. The network transfer device includes a plurality of line correspondence units 10 or 40, a plurality of packet transfer units 20 or 50, and active and standby device management units 30. The device management unit 30 is preset as one working system and the other as a standby system.

  The packet transfer engine 15 of the line corresponding unit 10 is accommodated in any of the sub crossbar switches 25 of the plurality of packet transfer units 20. The port number is an identification number assigned in advance to each port of the sub crossbar switch 25. For example, port 0 is connected to the first packet transfer engine 15, the identification number of the connected packet transfer engine 15 is 0, port 1 is connected to the second packet transfer engine 15, and the connected packet transfer engine 15 is connected. The identification number is 1.

  Normally, transfer between the packet transfer engine 15 and the sub crossbar switch 25 selects the first mode in which the throughput is maximized. However, by setting the packet transfer engine 15 and the sub crossbar switch 25 in advance, the frequency is halved. It is also possible to select the second mode in which the throughput is halved.

  The packet transfer engine 45 of the line corresponding unit 40 has a low-speed interface having a transfer capability different from that of the packet transfer engine 15 and can be accommodated in, for example, the port 9 of the sub crossbar switch 25. In the example shown in FIG. 2, the packet transfer engine 45 is mounted with the same interface as the packet transfer engine 36. The packet transfer engine 45 is accommodated in one of the sub crossbar switches 25 of the plurality of packet transfer units 50. In this embodiment, the packet transfer unit 50 uses the port 9 of the sub crossbar switch 25 to accommodate the line correspondence unit 40, and the ports 0 and 1 used in the packet transfer unit 20 are unused. To do. Whether the sub-crossbar switch 25 is mounted in the packet transfer unit 20 or connected to the packet transfer unit 40 is set in advance, and the function is switched according to the setting.

  Each port corresponding to the active or standby system of each sub crossbar switch 25 is accommodated in the active or standby crossbar switch 35 in the device management unit 30. For example, the ports 4 and 6 are mounted on the 0-system crossbar switch 35, and the ports 5 and 7 are accommodated in the 1-system crossbar switch 35.

  The port number of the crossbar switch 35 is an identification number assigned in advance. For example, port 0 and port 4 are connected to port 4 and port 6 of the sub crossbar switch 25 of the packet transfer unit 20. For example, the port 9 is connected to the packet transfer engine 36. The packet transfer engine 36 has the same interface as the packet transfer engine 45, for example. That is, it has a low-speed interface to the packet transfer engine 15 and the crossbar switch 35.

  The sub crossbar switch 25 validates the ports (for example, port 4 and port 6) connected to the active system according to a predetermined setting. In addition, the sub crossbar switch 25 invalidates a predetermined port and validates standby ports (for example, port 5 and port 7) in response to, for example, a system switching signal from the device management CPU 37 in the device management unit 30. And These operations are the same even if they are installed in the packet transfer unit 20 or 50.

  2, the crossbar switch 35, the sub crossbar switch 25, and the packet transfer engine 15 having the same transfer capability, the packet transfer engine 36 having a transfer capability lower than those of the switches 35, 25, and the packet transfer engine 15, and 45 is connected. The configuration of FIG. 2 is an example, and the number of packet transfer units 20 and 50 can be changed and the number of packet transfer engines can be increased. In the example shown in FIG. 2, the packet transfer engines 36 and 45 having a low transfer capability are shown. However, at least one packet transfer engine or switch may be configured to have a transfer capability lower than that of other switches. .

  FIG. 3 is an explanatory diagram showing the internal structure of the crossbar switch 35. The sub-crossbar switch 25 has the same configuration, but will be described as a crossbar switch 35 here. The crossbar switch 35 includes a port 131, a reception buffer 132 for each port 131, a reception buffer management unit 133, a threshold register 137, a reception buffer write control unit 151, a reception buffer read control unit 152, an arbitration circuit 134, and a switch 135. And have.

  A packet received via the port 131 from the sub crossbar switch 25 or the packet transfer engine 36 is temporarily held in a reception buffer 132 provided corresponding to each port 131 in units of cells which are packet constituent units. Note that, for example, there are nine ports for inputting and outputting this packet, and in the following description, numbers [0] to [7] and [9] are attached as necessary.

  The reception buffer write control unit 151 writes a cell sent from the input / output port 131 to the reception buffer 132 and also outputs a cell write signal 153 indicating that one cell has been written to the reception buffer 132 to the reception buffer management unit 133. Issue (output). Also, the type of the cell written in the reception buffer is determined, and if the cell is the final cell, the final cell write signal 154 is issued together with the cell write signal.

  The reception buffer read control unit 152 issues an arbitration participation signal to the arbitration circuit 134 by receiving the arbitration participation instruction signal 157 from the reception buffer management unit 133. In addition, when the cell is read from the reception buffer 132 and the cell is transmitted to the switch 135, the cell read signal 155 is issued. When the transmitted cell type is the final cell, the final cell read signal 156 is issued. Note that the reception buffer write control unit 151 and the reception buffer read control unit 152 can determine the last cell by detecting, for example, packet end information or a blank bit at the end of the packet. In addition to this, an appropriate method may be used for determining the final cell.

  The cell held in the reception buffer 132 is read by the reception buffer read control unit 152 in accordance with the instruction from the reception buffer management unit 133 and the instruction from the arbitration circuit 134, and the output route information in the first cell is 134. The arbitration circuit 134 causes the switch circuit 135 to sequentially send packets or cells to the switch circuit 135 in accordance with the transfer priority for the packets input in parallel from the ports 131 and receiving the arbitration participation signal from the reception buffer read control unit 152. Play a function.

  The reception buffer management unit 133 manages the number of cells held in the reception buffer 132, and performs an arbitration participation instruction signal according to the state of the reception cell buffer 132 (for example, the number of cells stored in the buffer) and the value of the threshold register 137. 157 is generated. The reception buffer management unit 133 also manages the final number of cells held in the reception buffer 132 and generates an arbitration participation instruction signal 157 according to the final number of cells. The generated arbitration participation instruction signal 157 is output to the reception buffer read control unit 152, for example. A detailed configuration of the reception buffer 132 and a method for determining an arbitration participation instruction will be described later.

  The threshold value register 137 is a programmable nonvolatile memory that stores a threshold value input from the outside. For example, 1 is set in the threshold registers 137 [0] to 137 [7] corresponding to the ports 131 [0] to 131 [7], and reception is performed in the threshold register 137 [9] corresponding to the port 131 [9]. The maximum number of surfaces that can be stored in the buffer 132 can be set. In addition to this, an appropriate value can be set as the value set in the threshold register. For example, the threshold value register 137 [9] may have a value somewhat smaller than the maximum number of surfaces in consideration of various functions (such as back pressure).

  Normally, the transfer between the packet transfer engine 15 and the sub crossbar switch 25 selects the first mode in which the throughput is maximum. However, the second mode in which the frequency is halved and the throughput is halved is selected as the second mode. Even when the corresponding port of the crossbar switch 25 is set, for example, the maximum number of planes that can be stored in the reception buffer 132 is set in the threshold register 137 of the corresponding port of the sub crossbar switch 25.

  The switch circuit 135 switches the packet transfer destination according to the cell header information (output route information), and outputs the packet to the transmission buffer 136 corresponding to the designated port. The transmission buffer 136 outputs this packet from the port 131. For convenience of explanation, the ports 131 are shown on the reception side and the transmission side in the figure, respectively, but both are the same on the circuit of the crossbar switch 35.

  In this embodiment, the ports 131 [0] to 131 [7] (first port) and the port 131 [9] (second port) have interfaces having different transfer capabilities. For example, the ports 131 [0] to 131 [7] of the crossbar switch 35 can be connected to the ports 131 [0] to 131 [7] of the sub crossbar switch, and the port 131 [9] of the crossbar switch 35 is connected to the packet transfer engine 15. Connection to a slower packet transfer engine 36 is possible.

  Similarly, the ports 131 [0] to 131 [7] of the sub crossbar switch 25 can be connected to the ports 131 [0] to 131 [7] of the crossbar switch or the packet transfer engine 15 having the same speed as the sub crossbar switch 25. The port 131 [9] of the sub crossbar switch can be connected to the packet transfer engine 45 that is slower than the packet transfer engine 15.

FIG. 4 is an explanatory diagram showing the structure of the reception buffer management unit 133.
The reception buffer management unit 133 includes a cell counter 140, a first comparator 141, a transfer flag 142, a final cell counter 143, a second comparator 144, and an OR circuit 145.

  The cell counter 140 is a counter that counts the number of cells stored in the corresponding reception buffer 132. For example, when a cell is written to the corresponding reception buffer 132, the reception buffer write control unit 151 receives the cell write signal 153 transmitted from the reception buffer 132, for example, +1 and the cell is read from the reception buffer 132. For example, the reception buffer read control unit 152 is decremented by −1 by receiving the cell read signal 155 transmitted.

  The first comparator 141 is a comparator that compares the output (A) of the cell counter 140 with the value (B) of the threshold register 137. When the output of the cell counter 140 is equal to or greater than the value of the threshold register 137, the transfer flag 142 is set.

  The transfer flag 142 is a flag indicating whether or not to perform cell reading. When a cell is stored in the reception buffer 132 that is equal to or greater than the value of the threshold register 137, an arbitration participation instruction is output and the cell is transferred to the last cell. It is a flag for performing control to do. The transfer flag 142 is set by a signal from the first comparator 141 and is reset by a read signal 156 for the last cell from the reception buffer read control unit 152.

  The final cell counter 143 is a counter that counts the number of final cells stored in the corresponding reception buffer 132. When the last cell write signal 154 transmitted from the reception buffer write control unit 151 is received based on the last cell being written in the reception buffer 132, for example, +1 is added, and reception is performed based on the last cell being read from the reception buffer 132. By receiving the final cell read signal 156 transmitted by the buffer read control unit 152, for example, it is decremented by one.

  The second comparator 144 participates in arbitration when the output (C) of the final cell counter 143 is greater than or equal to a predetermined value D (for example, 1) set in advance, that is, when one or more final cells are stored in the reception buffer 132. Output instructions. When one or more final cells are stored in the reception buffer 132, this indicates that one packet's worth of cells have been stored in the reception buffer 132, indicating that packet transfer can be started. Note that the final cell counter 143 and the second comparator 144 are not limited to the counter and the comparator, and may have an appropriate configuration (final cell determination means) for determining the presence or absence of the final cell.

  The OR circuit 145 is a circuit for outputting an arbitration participation instruction when the transfer flag is set or the output of the second comparator 144 indicates that one or more final cells are stored in the reception buffer 132 It is. When the arbitration participation instruction is output to the arbitration circuit 134, the cells stored in the reception buffer 132 are sequentially read out by the reception buffer read control unit 152 according to the transfer priority, and the line is occupied until the final cell is transferred. Then, the data is transferred via the switch circuit 135.

  FIG. 4 shows an example of the circuit configuration of the reception buffer management unit 133. However, other circuit configurations may be used, and similar functions may be realized by software.

(Operation example)
FIG. 6B shows an example of the operation of the crossbar switch according to the present embodiment when a packet equal to or less than the number of cells that can be held in the reception buffer 132 is input compared to FIG. FIG. When the reception buffer management unit 133 detects that the last cell of the packet 200 is held in the reception buffer 132, packet transfer is started. With this control, the line occupation time can be shortened as in the transmission packet 251 in FIG. 6B without providing a gap between the packets as in the transmission packet 250 in FIG. That is, the crossbar switch 35 can maximize its own transfer capability, and the waiting time of packets input to other ports is shortened by shortening the line occupation time.

  In the figure, 1 of the received packet 200 is the first cell of the packet, 2 is the second cell, and the numbers below indicate the number of the cell. Only the last cell is indicated by E. The same applies to the following packets 250, 251, 210, 260, 261, 220, 270, and 271.

  FIG. 7B shows the operation of the crossbar switch according to the present embodiment when a packet exceeding the number of cells that can be held in the reception buffer 132 is input with respect to FIG. When the reception buffer management unit 133 detects that the cell of the reception packet 210 is held in the reception buffer 132 by the threshold register 137 or more, packet transfer is started. This control makes it possible to reduce the line occupation time as in the transmission packet 261 in FIG. 7B without leaving a gap between the packets as in the transmission packet 260 in FIG.

FIG. 7B shows an example in which the value held in the threshold register 137 is set to the same value as the number of cells that can be held in the reception buffer 132. In addition, the maximum number of cells (N) when packets are transferred without a gap as in the case of the transmission packet 261 is the throughput A of the packet transfer engine, the throughput B (B> A) of the crossbar switch, and the number of reception buffers. It can be calculated from For example,
N = M (1+ (A / B) + (A / B) ² + (A / B) ³ +...)
It can be expressed as In the case of M = 8 and B = 2A, N is about 16, but N = 15 because N and M are integers in practice.

  FIG. 8B is a diagram showing the present embodiment when the packet having the number of cells equal to or larger than the number N of cells that can be held in the reception buffer 132 is input compared to FIG. It is a figure which shows the operation example of the crossbar switch of a form. When the reception buffer management unit 133 detects that the cell of the reception packet 220 is held in the reception buffer 132 by the threshold register 137 or more, packet transfer is started. With this control, in the transmission packet 271 of FIG. 8B, up to N cells are transferred without leaving a gap between the packets, and after the (N + 1) th cell, the same gap as in the conventional transmission packet 270 is created and transferred. . Compared with the conventional transmission packet 270, the transmission packet 271 of this embodiment can shorten the line occupation time.

  6 to 8 have been described as the crossbar switch 35 in the above description, the same applies to the sub crossbar switch 25.

  The present invention can be used in industries related to communication devices that perform packet transfer.

1 is a schematic diagram of a network transfer device. The figure which shows the structural example of the network transfer apparatus which accommodated the different line | wire corresponding | compatible part. Explanatory drawing which shows the internal structure of the crossbar switch. 3 is an explanatory diagram showing an internal structure of a reception buffer management unit 133. FIG. Crossbar switch model. The figure which shows the operation example (1) of a crossbar switch. The figure which shows the operation example (2) of a crossbar switch. The figure which shows the operation example (3) of a crossbar switch.

Explanation of symbols

10 Line support section (1)
15 Packet forwarding engine (1)
20 Packet transfer unit (1)
25 Sub-crossbar switch 26 Route search engine 27 Bus selection circuit 30 Device management unit 35 Crossbar switch 36 Packet transfer engine (3)
37 Device management CPU
40 Line support section (2)
45 Packet forwarding engine (2)
50 Packet transfer unit (2)
131 I / O Port 132 Reception Buffer 133 Reception Buffer Manager 134 Arbitration Circuit 135 Switch 136 Transmission Buffer 137 Threshold Register 140 Cell Counter 141 First Comparator 142 Transfer Flag 143 Last Cell Counter 144 Second Comparator 145 OR Circuit 151 Write to Reception Buffer Control unit 152 Reception buffer read control unit 153 Cell write signal 154 Final cell write signal 155 Cell read signal 156 Final cell read signal 157 Arbitration participation instruction signal 158 Threshold 200, 210, 220 Receive packets 250, 251, 260, 261, 270, 271 Transmission packet

Claims (7)

A crossbar switch in a packet transfer system that secures a transfer path from a first port to a second port from the passage of a leading cell to the passage of a final cell of a packet having a plurality of cells,
A receive buffer holding each cell of the received packet;
A reception buffer management unit for controlling transfer of cells or packets held in the reception buffer;
The destination port of the packet is determined according to the output route information contained in the received packet or the output route information obtained based on the packet header information, and the cell or packet read from the reception buffer is determined. And a switch for forwarding to
The reception buffer management unit includes:
Detecting the writing of the last cell to the receiving buffer and outputting a signal for transferring the packet or cell; and detecting the reading of the last cell from the receiving buffer to stop the transfer of the packet or cell;
Even if it is not possible to detect the writing of the last cell to the reception buffer, if the number of cells held in the reception buffer is greater than or equal to a predetermined threshold, a signal for transferring a packet or cell is output, And the crossbar switch that detects reading of the last cell from the reception buffer and stops packet or cell transfer. The signal for transferring the packet or cell is an arbitration participation signal,
When an arbitration participation signal is output from the reception buffer management unit, cells or packets held in the reception buffer are sequentially sent to the switch according to the priority order of cell or packet transfer among a plurality of arbitration participation signals. The crossbar switch according to claim 1, further comprising an arbitration circuit that transfers cells or packets. A write control unit for writing a received cell to the reception buffer, detecting a final cell of a packet, and writing a final cell to the reception buffer to output a final cell write signal;
A read control unit that reads a cell from the reception buffer and detects a final cell of a packet and outputs a final cell read signal by reading the final cell from the reception buffer;
The reception buffer management unit includes:
3. The crossbar switch according to claim 1, wherein writing of a final cell is detected by a final cell write signal from the write control unit, and reading of the final cell is detected by a final cell read signal from the read control unit. The reception buffer management unit includes:
Based on the final cell write signal from the write control unit and the final cell read signal from the read control unit, the presence or absence of the final cell held by the reception buffer is determined, and if there is a final cell, the packet or cell is transferred. A final cell discrimination means for outputting a signal for stopping the packet transfer when there is no last cell;
Based on a cell write signal output when the write controller writes a cell to the receive buffer and a read signal output when the read controller reads a cell from the receive buffer, the receive buffer A cell counter that counts the number of cells held by
A comparator that compares the value of the cell counter with a predetermined threshold and outputs a signal when the value of the cell counter is greater than or equal to the threshold;
A transfer flag that is set by the output of the comparator and reset by a final cell read signal from the read control unit;
Even if the final cell determination means determines that there is no final cell, the transfer flag is set to output a signal for transferring a packet or a cell, and the transfer flag is reset to transfer the packet. The crossbar switch according to claim 3 to be stopped. A threshold register for storing the threshold;
The crossbar switch according to any one of claims 1 to 4, wherein control of packet or cell transfer in the reception buffer management unit can be changed according to a connected device by a threshold stored in the threshold register. In a packet transfer system that secures a transfer path from the first port to the second port from the passage of the first cell to the passage of the last cell of a packet having a plurality of cells, the same or almost the same transfer capability as that of the own crossbar switch is obtained. A crossbar switch to be connected to a device having a lower transfer capability than the own crossbar switch,
A first receive buffer for holding each cell of a packet received from a device having the same or substantially the same transfer capability as the own crossbar switch;
A first reception buffer management unit corresponding to the first reception buffer, which controls transfer of cells or packets held in the first reception buffer;
A second receive buffer for holding each cell of a packet received from a device having a lower transfer capability than the own crossbar switch;
A second reception buffer management unit corresponding to the first reception buffer, which controls transfer of cells or packets held in the second reception buffer;
The destination port of the packet is determined according to the output route information included in the received packet or the output route information obtained based on the packet header information, and read from the first and second reception buffers. A switch for forwarding a cell or packet to a determined port;
When a signal for transferring a packet or cell output from the first and second reception buffer management units is input, the signal is held in the first and second reception buffers according to the transfer priority of the cell or packet. An arbitration circuit that sequentially sends cells or packets to the switch to transfer the cells or packets,
The first and second reception buffer managers are respectively
Detecting the writing of the last cell to the corresponding first and second receive buffers, outputting a signal for transferring a packet or cell, and the final from the corresponding first and second receive buffers Detect cell read and stop packet or cell transfer,
Even if the writing of the last cell to the corresponding first and second reception buffers cannot be detected, the number of cells held in the corresponding first and second reception buffers is the first and second When the threshold is equal to or higher than the first or second threshold corresponding to the reception buffer, a signal for transferring the packet or the cell is output, and the final cell is read from the corresponding first and second reception buffers. The crossbar switch for detecting a packet and stopping the transfer of a packet or a cell. A plurality of packet transfer units having a sub crossbar switch configured by the crossbar switch according to any one of claims 1 to 6;
A first packet transfer engine connected to any one of the sub crossbar switches and the line, for transferring a packet from the line to the sub crossbar switch, and sending a packet from the sub crossbar switch to the line; A plurality of line compatible units;
The crossbar switch according to any one of claims 1 to 6, a device management processing unit that manages the entire device, and a second packet transfer for transferring a packet between the crossbar switch and the device management processing unit And an apparatus management unit for transferring packets between each of the plurality of packet transfer units and the second packet transfer engine,
A network transfer apparatus in which at least one transfer capability of the first packet transfer engine and the second packet transfer engine is lower than the packet transfer capability of the crossbar switch or the sub crossbar switch to be connected.

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