JP2005252909A - Highly voltage-resistant semiconductor relay - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly voltage-resistant semiconductor relay which decreases the number of components, reduces a mounting area, and is adaptible to a safety standard. <P>SOLUTION: The highly voltage-resistant semiconductor relay comprises two LEDs and two dielectric separation chips wherein a plurality of DMOSFETs formed around a dielectric-separated substrate are connected in series, voltage output type photo-diode arrays as many as DMOSFETs receiving output lights of the LEDs are formed in the center of the substrate, and a voltage output type photo-diode array and a shunt resistor adjacent to the DMOSFET are connected in parallel between the source and gate of the DMOSFET. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor relay used for an input multiplexer switch of a recorder such as a recorder, and more particularly to a high voltage semiconductor relay capable of reducing the number of parts and mounting area and complying with safety standards.

  Prior art documents related to semiconductor relays used for input multiplexer switches of recorders such as conventional recorders include the following.

Japanese Patent Laid-Open No. 05-167712 JP 09-213926 A Japanese Patent Laid-Open No. 09-312392 JP 10-1117011 A JP-A-10-126239

  FIG. 8 is a block diagram showing an example of a conventional semiconductor relay having a withstand voltage of 3000 V class. In FIG. 8, 1 is an LED (Light Emitting Diode), 2 is a double-diffused metal oxide semiconductor field effect transistor (hereinafter simply referred to as a DMOSFET), and 3 is a gate. Protective diodes for protection, 4 is a control circuit, and 5 is a voltage output type photodiode array.

  In FIG. 8, two LEDs 1 etc. are connected in series between the input terminals indicated by “IT01” and “IT02”, and four are connected in series between the output terminals indicated by “OT01” in FIG. The drain of is connected. Further, the drains of four DMOSFETs connected in series are connected between the output terminals indicated by “OT02” in FIG. 8, and the sources of the DMOSFETs connected in series are connected to each other.

  A protective diode 3, a control circuit 4, and a voltage output type photodiode array 5 are connected in parallel between the gate and source of each DMOSET2.

  Here, the operation of the conventional example shown in FIG. 8 will be described with reference to FIGS. FIG. 9 is a structural cross-sectional view showing an example of a DMOSFET having a breakdown voltage of 750 V class, and FIG. 10 is a structural cross-sectional view showing an example of the voltage output type photodiode array 5.

  The conventional relay shown in FIG. 8 having a withstand voltage of 3000 V class does not realize a high withstand voltage of 3000 V by using a special structure or a compound semiconductor such as SiC, but uses a plurality of existing DMOSFETs with a withstand voltage of 750 V. These are connected in series to achieve a withstand voltage of 3000V.

  For example, in the 750V class DMOSFET shown in FIG. 9, 6 is a p-type substrate, 7 is an n-type drift channel layer, 8 is a p-type base layer, 9 and 10 are n + layers, 11 is a p− layer, 12 is LOCOS (local-oxidation-of-silicon), 13 and 16 are floating field plates, 14 is an insulating film, 15 is a drain electrode, 17 is a source field plate, 18 is a gate electrode, and 19 is a source electrode.

  A drift channel layer 7 and a base layer 8 are formed on the substrate 6, and an n + layer 9 and a LOCOS 12 are formed in the drift channel layer 7. In the base layer 8, an n + layer 10 and a p + layer 11 are formed.

  A floating field plate 13 is formed on the LOCOS 12, and a gate electrode 18 is formed from the base layer 8 to the LOCOS 12. Further, an insulating film 14 is formed on these, and a drain electrode 15 is formed on the n + layer 9 from which the insulating film 14 has been removed.

  A floating field plate 16 and a source field plate 17 are formed on the insulating film 14, and a source electrode 19 is formed across the n + layer 10 and the p + layer 11.

  Incidentally, since the DMOSFET shown in FIG. 9 is an existing one, a detailed description of the operation of the DMOSFET itself is omitted.

  In FIG. 8, when a current is passed in the forward direction of the LED 1 etc. connected between “IT01” and “IT02”, the LED 1 etc. emits light, and a voltage output type which is a light receiving element arranged adjacent to the LED 1 etc. Light is received by the photodiode array 5 or the like.

  For example, in the voltage output type photodiode array shown in FIG. 10, 20 is a ceramic substrate, 21 and 22 are wirings, 23 and 24 are metal, 25 is a photodiode array in which a plurality of photodiodes are connected in series, and 26 and 27 are It is a conductive adhesive.

  Wirings 21 and 22 are formed on the ceramic substrate 20, a metal array 23 and 24 are formed at both ends, and a photodiode array 25 in which a plurality of photodiodes are connected in series is formed, and the metal 23 and 24 at both ends are connected to the wirings 21 and 22. The photodiode array 25 is fixed to the ceramic substrate 20 with conductive adhesives 26 and 27 at the contact portions.

  The photocurrent generated in the voltage output type photodiode array 5 or the like which is such a light receiving element is charged in the gate of the DMOSFET 2 or the like. When the gate voltage exceeds a threshold value of the DOMSFET 2 or the like, the DMOSFET 2 or the like transitions from the “OFF state” to the “ON state”, and the output terminals indicated by “OT01” and “OT02” in FIG. 8 are short-circuited.

  On the other hand, when the supply of forward current to the LED 1 or the like is stopped, the LED 1 or the like stops emitting light, and the charge accumulated in the gate of the DMOSFET 2 or the like is discharged by the control circuit 4 or the like, and the DMOSFET 2 when the gate voltage falls below the threshold value of the DOMSFET 2 or the like. Transition from the “ON state” to the “OFF state” and the output terminals indicated by “OT01” and “OT02” in FIG. 8 are opened.

  In addition, in order to handle bipolar signals in the semiconductor relay, two four 750 V class DMOSFETs that realize a withstand voltage of 3000 V are connected and used.

  As described above, the semiconductor relay having a withstand voltage of 3000 V is used for an input multiplexer switch of a recorder such as a recorder. FIG. 11 is a block diagram showing an example of a recorder that records a thermocouple signal.

  In FIG. 11, 28 is an amplifier circuit, 29 is an A / D conversion circuit, 30 is an arithmetic circuit, and 31 is a control circuit. In FIG. 11, “SC21” is a switch circuit using a semiconductor relay with a withstand voltage of 3000 V, and 28, 29, 30, 31 and “SC21” constitute the recorder 200.

  The thermocouples indicated by “TC11”, “TC12”, and “TC13” in FIG. 11 are respectively connected to a plurality of input terminals of the switch circuit indicated by “SC21” in FIG. 11, and the thermocouple indicated by “SC21” in FIG. The output terminal is connected to the A / D conversion circuit 29 via the amplifier circuit 28.

  The output of the A / D conversion circuit 29 is connected to the arithmetic circuit 30, and the control signal of the control circuit 31 is connected to the control input terminal of the switch circuit indicated by “SC21” in FIG.

  The thermocouple outputs indicated by “TC21”, “TC22” and “TC23” in FIG. 11 are appropriately selected based on the control signal of the control circuit 31 in the switch circuit indicated by “SC21” in FIG. It is input to the A / D conversion circuit 29.

  The A / D conversion circuit 29 converts the input thermocouple signal amplified appropriately into a digital signal, and the arithmetic circuit 30 records the thermocouple signal converted into a digital signal on a recording sheet or storage means (not shown). )Record.

  That is, since a semiconductor relay having a withstand voltage of 3000 V is used in the switch circuit indicated by “SC21” in FIG. 11, a withstand voltage of 3000 V can be realized even with a signal having both polarities.

  However, when recording the thermocouple signal indicated by “TC31” in FIG. 11 on which the power supply voltage indicated by “AP21” in FIG. 11 is superimposed, the conventional IEC (International Electrotechnical Commission) or In the safety standard such as JIS (Japan Industrial Standard), the withstand voltage of the recorder is “1000 Vrms” in the 250 VAC line, so if it is a semiconductor relay with a withstand voltage of 1500 VDC, it can be adapted to the 250 VAC line. With the recent revision of safety standards, semiconductor relays with a withstand voltage of 1500 VDC can only be used up to 125 VAC lines.

  For this reason, in order to use a semiconductor relay in a 250 VAC line, a demand has arisen that a withstand voltage of 3000 VDC is required. Therefore, in Japanese Patent Application No. 2003-295909 related to the application of the present applicant, a 3000 V withstand voltage semiconductor relay is provided. Is described.

  FIG. 12 is a plan view showing a mounting example of a 3000 V breakdown voltage semiconductor relay described in “Japanese Patent Application No. 2003-295909”.

  In FIG. 12, 32 is a ceramic substrate, 33 is an LED, 34 is a voltage output type photodiode array, 35 is a 750 V class DMOSFET, 36 is an epoxy resin, and 37 is a transparent silicon rubber.

  The circuit configuration is the same as that of the configuration block diagram shown in FIG. 8, and by supplying current to the input terminals indicated by “IT31” and “IT32” in FIG. 12, the LED 33 etc. emits light and is adjacent to the LED 33 etc. The light is received by the voltage output type photodiode array 34 or the like, which is a light receiving element arranged in this manner.

  Then, the photocurrent generated in the voltage output type photodiode array 34 or the like which is a light receiving element is charged to the gate of the DMOSFET 35 or the like. When the gate voltage exceeds the threshold value of the DOMSFET 35 or the like, the DMOSFET 35 or the like transitions from the “OFF state” to the “ON state”, and the output terminals indicated by “OT31” and “OT32” in FIG. 12 are short-circuited.

  On the other hand, when the supply of current to the LED 33 or the like is stopped, the LED 33 or the like stops emitting light, and the charge accumulated in the gate of the DMOSFET 35 or the like is discharged by a control circuit (not shown), and the gate voltage falls below the threshold value of the DOMSFET 35 or the like. And the DMOSFET 35 and the like transition from the “ON state” to the “OFF state”, and the output terminals indicated by “OT31” and “OT32” in FIG. 12 are opened.

However, the 3000V withstand voltage semiconductor relay shown in FIG. 12 has a problem that it has a large number of parts and may increase the number of assembly steps. Specifically, the mounting example of the 3000V withstand voltage semiconductor relay described in Japanese Patent Application No. 2003-295909 has 16 parts.
Therefore, the problem to be solved by the present invention is to realize a high voltage semiconductor relay capable of reducing the number of parts, reducing the mounting area and complying with safety standards.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In high voltage semiconductor relays,
Two LEDs and a plurality of DMOSFETs formed in the peripheral part of the substrate separated from the dielectric are connected in series, and the same number of voltage output type photo diodes as the DMOSFETs that receive the output light of the LED in the central part of the substrate A diode array is formed, and a voltage output type photodiode array adjacent to the DMOSFET and two dielectric isolation chips each having a shunt resistor connected in parallel between the source and gate of the DMOSFET are provided. This reduces the mounting area and enables compliance with safety standards.

The invention according to claim 2
In the high voltage semiconductor relay which is the invention according to claim 1,
By filling the transparent silicon resin between the LED and the voltage output photodiode array that receives the output light of the LED, the number of components is reduced, the mounting area is reduced, and the safety standard can be met.

The invention described in claim 3
In the high voltage semiconductor relay which is the invention according to claim 1,
The dielectric separated substrate is
A thermal oxide film is grown on a silicon wafer, the silicon wafer is bonded to the surface on which the thermal oxide film is grown, and a groove is formed on one silicon wafer by etching up to the thermal oxide film. The organic polymer dielectric film is filled with a molecular dielectric material, and the surface of the formed organic polymer dielectric film is polished until it reaches the one silicon wafer. This reduces the mounting area and enables compliance with safety standards.

The invention according to claim 4
In the high voltage semiconductor relay which is the invention according to claim 1,
The number of DMOSFETs is
Since the number is necessary to satisfy a predetermined withstand voltage, the number of parts can be reduced, the mounting area can be reduced, and safety standards can be met.

The invention according to claim 5
In the high voltage semiconductor relay which is the invention according to claim 1,
The voltage output type photodiode array includes:
Since a plurality of photodiodes capable of obtaining an output sufficient to drive the DMOSFET are connected in series, the number of components is reduced, the mounting area is reduced, and the safety standard can be met.

The invention described in claim 6
In the high voltage semiconductor relay which is the invention according to any one of claims 1 to 5,
The DMOSFET is
By using a horizontal DMOSFET, the number of components can be reduced, the mounting area can be reduced, and safety standards can be met.

The present invention has the following effects.
According to the first, second, third, fourth, and fifth aspects of the present invention, four lateral DMOSFETs are formed in the peripheral portion of the dielectric-isolated substrate, and the source of each lateral DMOSFET is the adjacent lateral DMOSFET. Four lateral DMOSFETs are connected in series by connecting to the drain with wires, and four voltage output photodiode arrays are formed in the central portion of the substrate separated from the dielectric, and the voltage output photodiodes adjacent to each lateral DMOSFET are formed. By mounting a high voltage semiconductor relay using two dielectric isolation chips each having a diode array and a shunt resistor connected in parallel between the source and gate of the horizontal DMOSFET, in other words, driving a high voltage lateral DMOSFET and this By forming a voltage output type photodiode array on the same dielectric isolation substrate It becomes available to the safety standards while reducing reduced by mounting area the number of parts. In addition, by using an organic polymer dielectric film for dielectric separation for ensuring the withstand voltage between elements, a long-time heat treatment is unnecessary, and the warpage of the wafer can be reduced.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration plan view showing an embodiment of a dielectric isolation chip used in a high voltage semiconductor relay according to the present invention, and FIGS. 2 and 3 are plan views showing mounting examples of the high voltage semiconductor relay according to the present invention. 3 is a cross-sectional view taken along the line AA ′ of FIG.

  The dielectric isolation chip shown in FIG. 1 is obtained by serially connecting four 750 V class horizontal DMOSFETs formed on a dielectric isolation substrate. However, the LED connected to the input terminal is not shown in FIG.

  In FIG. 1, reference numeral 38 denotes a lateral DMOSFET formed on a dielectric isolation substrate, 39 denotes a voltage output type photodiode array built on the dielectric isolation substrate, 40 denotes a shunt resistor built into the dielectric isolation substrate, 41 Is an aluminum wiring wired on the dielectric isolation substrate.

  In FIG. 1, “SC41”, “GT41”, and “DR41” indicate the source, gate, and drain of the lateral DMOSFET 38, respectively. In FIG. 1, “WR41” indicates a wire that connects between the source and drain of each lateral DMOSFET 38. It is.

  Four lateral DMOSFETs 38 are formed in the peripheral portion (four sides) of the dielectric isolation substrate, and the source of each lateral DMOSFET is connected to the drain of the adjacent lateral DMOSFET by a wire, so that the four lateral DMOSFETs are connected in series. The

  On the other hand, 36 voltage output photodiodes are formed in the central portion of the dielectric separation substrate, and nine voltage output photodiodes adjacent to each other are connected in series by an aluminum wiring 41 or the like to form four voltage output photodiodes. An array 39 is formed.

  At this time, since the voltage output type photodiode array 39 can generate a voltage of about “5.5 V”, the threshold voltage of the lateral DMOSFET 38 is set to “about 1.5 V”. Further, between the anode and the cathode of each voltage output type photodiode array, a polysilicon high resistance is disposed by utilizing the space between the elements separated by dielectric.

  A voltage output photodiode array 39 and a shunt resistor 40 adjacent to each lateral DMOSFET 38 are connected in parallel between the source and gate of the lateral DMOSFET 38.

  On the other hand, in FIG. 2, 42 is a mold resin, 43 is a dielectric separation chip as shown in FIG. 1, 44 is a transparent silicon resin, 45 is a lead frame, and 46 is for connecting the dielectric separation chip 43 and the lead frame 45. It is a wire. In FIG. 3, reference numerals 42, 43, 44, 45 and 46 are assigned the same reference numerals as in FIG. 3, and 47 is an LED.

  In order to realize a withstand voltage of ± 3000 V, two dielectric isolation chips 43 are used as shown in FIG. 2, and serially connected lateral DMOSFETs (four lateral DMOSFETs connected in series) formed on the dielectric isolation chips. ) Are connected to each other by wires, and the drains of series-connected lateral DMOSFETs (four lateral DMOSFETs connected in series) are connected to the lead frame 45 and the like by wires 46 and the like.

  Further, as shown in FIG. 3, the LED 47 is mounted so as to be positioned immediately above the central portion of the region where the four voltage output type photodiode arrays are formed, and between the LED 47 and the voltage output type photodiode array. Is filled with a transparent silicon resin 44 and efficiently guides the output light of the LED 47 to a voltage output type photodiode array which is a light receiving element.

  Incidentally, the basic operation of the high voltage semiconductor relay shown in FIGS. 2 and 3 is the same as that of the conventional example shown in FIG.

  A method for manufacturing the dielectric isolation chip shown in FIG. 1 will be described with reference to FIGS. 4 to 6 are cross-sectional views showing the manufacturing process of the dielectric isolation chip. In FIGS. 4 to 6, 48 and 50 are p-type silicon wafers, 49 is a thermal oxide film, and 51 is an organic polymer dielectric film. It is.

  In the first step, a thermal oxide film 49 is grown on a p-type silicon wafer 48, and a p-type silicon wafer is bonded to the surface on which the thermal oxide film 49 is grown to manufacture the wafer. At this time, the thickness of the thermal oxide film indicated by “TH51” in FIG. 4 is set to about “3 μm” in order to realize a withstand voltage of 3000V. The silicon wafer on the side where the lateral DMOSFET is to be formed has a substrate specific resistance “ρ = 100 Ω · cm”.

  In the second step, grooves as shown by “DT61”, “DT62”, and “DT63” in FIG. 5 are formed by etching up to the thermal oxide film 49, and the formed grooves are formed with an organic polymer dielectric material. The organic polymer dielectric film 51 is formed by filling with

  In the third step, the surface of the formed organic polymer dielectric film 51 is polished until it reaches the p-type silicon wafer 50, thereby manufacturing a dielectric separated substrate.

  In the fourth step, a horizontal DMOSFET is formed in a region indicated by “DM71” in FIG. 6, in other words, in a region separated by an organic polymer dielectric film, using a normal IC process step. A voltage output type photodiode array is formed in a region indicated by “DD71”, in other words, in a region separated by an organic polymer dielectric film. However, the width of the organic polymer dielectric film 51 indicated by “TH71” in FIG. 6 is set to a width sufficient to obtain a breakdown voltage of 3000 V or more.

  Further, as the high breakdown voltage DMOSFET shown in FIG. 1 or the like, a horizontal DMOSFET is used. When a vertical DMOSFET is used (the substrate is n-type), the photodiode anode and cathode and the DMOSFET are used. When the gate and source are connected in the dielectric isolation chip, the guard ring that secures the withstand voltage of the vertical DMOSFET is short-circuited by the inversion layer formed directly under the gate and source wirings, so that a predetermined withstand voltage cannot be secured. Because.

  Such a situation will be described with reference to FIG. FIG. 7 is a cross-sectional view for explaining the breakdown voltage degradation when a vertical DMOSFET is used as the DMOSFET. In FIG. 7, 52 is a p-type guard ring, 53 is a p-type inversion layer, 54 is an insulating layer, 55 is polysilicon, and 56 is aluminum wiring.

  As can be seen from FIG. 7, the p-type inversion layer 53 formed immediately below the aluminum wiring 56 due to the aluminum wiring 56 short-circuits the p-type guard ring 52 that secures the withstand voltage of the vertical DMOSFET. The guard ring will not function, and a predetermined breakdown voltage cannot be secured.

  As a result, four lateral DMOSFETs are formed in the peripheral part of the substrate separated from the dielectric, the source of each lateral DMOSFET is connected to the drain of the adjacent lateral DMOSFET by a wire, and the four lateral DMOSFETs are connected in series and dielectrically connected. Four voltage output type photodiode arrays are formed in the central part of the substrate separated from each other, and the voltage output type photodiode array adjacent to each lateral DMOSFET and the shunt resistor are connected in parallel between the source and gate of the lateral DMOSFET. By mounting a high breakdown voltage semiconductor relay using two dielectric isolation chips, in other words, by forming a high breakdown voltage lateral DMOSFET and a voltage output photodiode array for driving it on the same dielectric isolation substrate In addition to reducing the number of parts and mounting area It becomes available to all standards.

  Specifically, in the 3000 V withstand voltage semiconductor relay described in “Japanese Patent Application No. 2003-295909” shown in FIG. 12, the number of parts is 16 (when a 750 V class DMOSFET is used). In the high voltage semiconductor relay according to the above, since only two dielectric isolation chips are required, the number of parts is reduced to 1/8.

  Although the mounting area of the DMOSFET and the voltage output type photodiode array is not different from the conventional example, the wiring area is greatly reduced due to the integration efficiency of the dielectric separation technology, and the mounting area is smaller than that of the conventional example. About 1/2.

  Further, by using the organic polymer dielectric film for dielectric separation for ensuring the withstand voltage between the elements, a long-time heat treatment becomes unnecessary, and the warpage of the wafer can be reduced.

  In the description of FIG. 1 and the like, the number of horizontal DMOSFETs formed on the dielectric isolation chip is exemplified as four 750V class horizontal DMOSFETs, but of course, the number is not limited to this number. For example, if a predetermined breakdown voltage is 3000V, two 1500V class horizontal DMOSFETs may be connected in series.

  The voltage output type photodiode array shown in FIG. 1 and the like is configured by connecting nine voltage output type photodiodes in series. Of course, the number is not limited to this number, and a lateral DMOSFET is driven. As long as a sufficient output can be obtained, a voltage output photodiode array may be constituted by an arbitrary number of voltage output photodiodes.

1 is a configuration plan view showing an embodiment of a dielectric isolation chip used in a high voltage semiconductor relay according to the present invention. It is a top view which shows the example of mounting of the high voltage | pressure-resistant semiconductor relay which concerns on this invention. It is A-A 'sectional drawing which shows the mounting example of the high voltage | pressure-resistant semiconductor relay which concerns on this invention. It is sectional drawing which shows the manufacturing process of a dielectric isolation | separation chip | tip. It is sectional drawing which shows the manufacturing process of a dielectric isolation | separation chip | tip. It is sectional drawing which shows the manufacturing process of a dielectric isolation | separation chip | tip. It is sectional drawing explaining the pressure | voltage resistant deterioration at the time of using vertical DMOSFET as DMOSFET. It is a block diagram showing an example of a conventional semiconductor relay having a withstand voltage of 3000 V class. It is a cross-sectional view showing an example of a DMOSFET having a breakdown voltage of 750 V class. It is a structure sectional view showing an example of a voltage output type photodiode array. It is a block diagram which shows an example of the recorder which records a thermocouple signal. It is a top view which shows the example of mounting of the 3000V pressure | voltage resistant semiconductor relay.

Explanation of symbols

1,33,47 LED
2,35,38 Double diffusion field effect transistor (DMOSFET)
DESCRIPTION OF SYMBOLS 3 Protection diode 4 Control circuit 5,34,39 Voltage output type photodiode array 6 Substrate 7 Drift channel layer 8 Base layer 9,10 n + layer 11 p- layer 12 LOCOS
13, 16 Floating field plate 14 Insulating film 15 Drain electrode 17 Source field plate 18 Gate electrode 19 Source electrode 20, 32 Ceramic substrate 21, 22 Wiring 23, 24 Metal 25 Photodiode array 26, 27 Conductive adhesive 28 Amplifying circuit 29 A / D conversion circuit 30 Arithmetic circuit 31 Control circuit 36 Epoxy resin 37 Transparent silicon rubber 40 Shunt resistor 41, 56 Aluminum wiring 42 Mold resin 43 Dielectric separation chip 44 Transparent silicon resin 45 Lead frame 46 Wire 48, 50 Silicon wafer 49 Heat Oxide film 51 Organic polymer dielectric film 52 Guard ring 53 Inversion layer 54 Insulating layer 55 Polysilicon 200 Recorder

Claims (6)

In high voltage semiconductor relays,
Two LEDs,
A plurality of DMOSFETs formed in the peripheral portion of the substrate separated from each other in dielectric are connected in series, and the same number of voltage output type photodiode arrays as the DMOSFET receiving the output light of the LED are formed in the central portion of the substrate. A high-voltage semiconductor relay comprising: a voltage output photodiode array adjacent to the DMOSFET; and two dielectric isolation chips each having a shunt resistor connected in parallel between the source and gate of the DMOSFET. 2. The high withstand voltage semiconductor relay according to claim 1, wherein a transparent silicon resin is filled between the LED and the voltage output type photodiode array that receives the output light of the LED. The dielectric separated substrate is
A thermal oxide film is grown on a silicon wafer, the silicon wafer is bonded to the surface on which the thermal oxide film is grown, and a groove is formed on one silicon wafer by etching to reach the thermal oxide film. An organic polymer dielectric film is formed by embedding with a molecular dielectric material, and the surface of the formed organic polymer dielectric film is polished until reaching the one silicon wafer. Item 1. A high voltage semiconductor relay according to Item 1. The number of DMOSFETs is
2. The high withstand voltage semiconductor relay according to claim 1, wherein the number is necessary for satisfying a predetermined withstand voltage. The voltage output type photodiode array includes:
2. The high breakdown voltage semiconductor relay according to claim 1, wherein a plurality of photodiodes capable of obtaining an output sufficient to drive the DMOSFET are connected in series. The DMOSFET is
6. The high voltage semiconductor relay according to claim 1, wherein the high voltage semiconductor relay is a lateral DMOSFET.

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