JP2005252266A - Method for manufacturing memory device having gate containing uniformly distributed, silicon nano-dots - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a memory device having a gate containing uniformly distributed, silicon nano-dots. <P>SOLUTION: A method for manufacturing a memory device comprises a first stage in which an insulating film and a gate containing a nano-dot layer and a conduction film pattern which are sequentially stacked with a certain interval and enclosed by the insulating film; a second stage in which a source region and a drain region, which contact to the gate, are formed on the substrate; and a third stage in which a first metal layer and a second metal layer are formed in the source region and the drain region respectively. Thus, since nano-dots are never exposed in a etching process for the gate formation, a problem of projection of the nano-dots outside the gate, or irregularity of an edge of the gate is prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a memory device including gates including nanodots that are uniformly distributed.

  As the size of a MOSFET (Metal Oxide Field Effect Transistor) becomes smaller, there is a problem that it is difficult to reduce the size of the MOSFET. For example, as the element size is reduced, problems such as DIBL (Drain Induced Barrier Lowering) and punch-through due to a decrease in effective channel length, deterioration of oxide film due to high-temperature carriers generated due to an increase in electric field inside the element, and increase in leakage current, etc. Has occurred. Such a problem is a main factor that makes it difficult to reduce the size of the MOSFET.

  Most importantly, however, is the fact that we continue to face fundamental physical limitations as we continue to scale the MOSFET and reduce its size to the nanometer level.

  That is, in the miniaturized MOSFET, the number of electrons involved in the operation of the element is almost the same as the number of thermally oscillating electrons, and an appropriate operation at normal temperature cannot be expected.

  As a result, an element that replaces the MOSFET having the above-described problems is required, and one of the memory elements developed due to the necessity is a flash memory element.

  Referring to FIG. 1, the conventional flash memory device includes a substrate 10 used for an existing MOSFET and a gate stack 12 formed on the substrate 10. A source region 10s and a drain region 10d are formed on the substrate 10 at a predetermined interval. The gate stack 12 exists on the substrate 10 between the source region 10s and the drain region 10d. The gate stack 12 is formed by sequentially stacking a gate insulating film 12a, a floating gate 12b in which electrons are trapped, an interlayer insulating film 12c, and a control gate 12d.

  Such a flash memory element is a field effect transistor (FET), and is a non-volatile memory element that exists even after electrons trapped in the floating gate 12b are turned off. Therefore, if a flash memory device is used, a non-volatile memory device that is cheaper than a DRAM (Dynamic Random Access Memory) can be realized.

  Despite such advantages, the flash memory device shown in FIG. 1 has the disadvantages that the recording speed is slow, the recording voltage is high, and the number of recordings is limited to about 10,000. Further, in order to sufficiently increase the holding time, the gate insulating film must be kept sufficiently thick. Due to such factors, the reduction of the flash memory device is also limited.

  Accordingly, recently, flash memory devices using nanotechnology have been introduced.

  The feature of the flash memory device using the nano technology introduced so far is that the floating gate is formed of nano dots.

  However, in the case of the flash memory device using the nano technology introduced up to now, the nano dots are formed first, and then the etching process for forming the gate is performed, so that the nano dots and the gate insulating film are etched. Due to the difference in rate, the gate boundary may be bumpy along the nanodots, and in particular, some nanodots may jump out of the gate.

  The problem to be solved by the present invention is to improve the above-mentioned problems of the prior art, in which silicon nanodots can be uniformly distributed on the gate, and the nanodot can be prevented from jumping out of the gate A method for manufacturing an element is provided.

  A method of manufacturing a memory device according to the present invention includes forming a gate including an insulating film and a nanodot layer and a conductive film pattern that are sequentially stacked at a predetermined interval and are included in the insulating film on a substrate. A first step of forming a source region and a drain region in contact with the gate on the substrate; a first metal layer and a second metal layer on the source region and the drain region; It consists of a third stage of forming each.

  The first step includes forming a gate stack including the insulating film, a material film for forming a nanodot layer, and a conductive film pattern on the substrate, and a material film for forming the nanodot layer. It is preferable to include the 1B step | paragraph which converts into the nanodot layer containing at least 1 nanodot.

  In the step 1B, the gate stack is preferably annealed until the material film for forming the nanodot layer becomes the nanodot layer.

  The first A stage is a first AA stage in which a first insulating film, a material film for forming the nanodot layer, a second insulating film, a conductive film, and a third insulating film are sequentially stacked on the substrate. And a first AB step of patterning the first insulating film, the material film for forming the nanodot layer, the second insulating film, the conductive film, and the third insulating film to form a laminate. And a first AC step of forming a spacer on a side surface of the laminate.

  It is preferable that the second stage is performed before the first B stage.

The material film for forming the nanodot layer is preferably formed of a SiO _2−X film (0 <X <1) or a Si ₃ N _4−X film (0 <X <1).

  The annealing of the gate is preferably performed at a temperature of 700 ° C. to 1100 ° C. for 30 seconds to 1 hour.

  The first stage includes a first C stage for forming a first insulating film on a substrate, a first D stage for forming a material film for forming a nanodot layer on the first insulating film, and a material for forming the nanodot layer. A first step of forming a material film pattern for forming a nanodot layer defining a gate forming region by patterning the film, and a first F for converting the material film pattern for forming the nanodot layer into a nanodot layer including at least one nanodot. A first G stage of forming a second insulating film covering the nanodot layer on the resultant structure on which the nanodot layer is formed; and the conductive film pattern at a position corresponding to the nanodot layer of the second insulating film. A first H stage for forming a first insulating layer; a first I stage for forming a third insulating film covering the conductive film pattern on the second insulating film; and the conductive film pattern and the nanodots. To include the bets, and the first insulating film preferably includes a second insulating film, and a second 1J step of patterning the third insulating film.

  Preferably, the first insulating film, the second insulating film, and the third insulating film are formed of the same material film.

The material film for forming the nanodot layer is preferably formed of a SiO _2−X film (0 <X <1) or a Si ₃ N _4−X film (0 <X <1).

  In the first step F, it is preferable that the material film for forming the nanodot layer is annealed and converted into the nanodot layer.

  The annealing is preferably performed at a temperature of 700 ° C. to 1100 ° C. for 30 seconds to 1 hour.

  The first step includes a first K step of forming a first insulating film on the substrate, a first L step of implanting a seed for forming nanodots into the first insulating film, and a first step of implanting the seed. Patterning an insulating film to form a first insulating film pattern that defines a gate forming region; a first N stage that forms a nanodot layer including at least one nanodot in the first insulating film pattern; and Forming a second insulating film covering the first insulating film pattern including the nanodot layer on the substrate; and forming a second insulating film on a predetermined region corresponding to the upper side of the nanodot layer of the second insulating film. A first P stage for forming a conductive film pattern; a first Q stage for forming a third insulating film covering the conductive film pattern on the second insulating film; and the conductive film pattern and the nanodot layer. , Said first insulating film preferably includes a second insulating film, and a second 1R step of patterning the third insulating film.

  The first insulating film, the second insulating film, and the third insulating film are preferably formed of a silicon oxide film.

  The seed is preferably silicon.

  The first M stage is preferably performed before the first L stage.

  In the first N stage, the nanodot layer is preferably formed by annealing the first insulating film pattern.

  The annealing is preferably performed at a temperature of 700 ° C. to 1100 ° C. for 30 seconds to 1 hour.

  When a memory device is manufactured using the method for manufacturing a memory device according to the present invention, since the nanodot is not exposed at all in the etching process for forming the gate, the nanodot protrudes outside the gate or the edge of the gate. It is possible to prevent the portion from being bumpy.

  Hereinafter, a method for manufacturing a memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers and regions shown in the drawings are exaggerated for clarity of the specification.

  <First Embodiment>

  A method for manufacturing a memory device according to a first embodiment of the present invention (hereinafter referred to as a first manufacturing method of the present invention) will be described with reference to FIGS.

Referring to FIG. 2, a first insulating film 42, a material film for forming nanodots (hereinafter referred to as nanodot material film) 44, a second insulating film 46, a conductive film 48, and a third insulating film 50 are formed on a substrate 40. Sequentially formed. The substrate 40 can be formed of a semiconductor substrate, and the first insulating film 42 can be formed of a tunneling film, for example, a silicon oxide film SiO ₂ . The nanodot material film 44 may be formed of a material film having a predetermined thickness in which electrons are trapped, for example, a silicon oxide film SiO _{2 -X} or a nitride film Si ₃ N _{4 -X} . Here, the value of the subscript “X” is 0 <X <1. The second insulating film 46 can be formed of a predetermined oxide film, for example, a silicon oxide film. The conductive film 48 is for forming a control gate, and can be formed of, for example, a doped polysilicon film or a metal film.

  Next, a photosensitive film pattern (not shown) that defines a gate formation region is formed on the third insulating film 50. The material layers 42, 44, 46, 48, and 50 sequentially stacked on the substrate 40 are etched in reverse order using the photoresist pattern as a mask. At this time, the etching is performed until the substrate 40 is exposed. After the etching is completed, the photoresist pattern is removed. As a result, as illustrated in FIG. 3A, the gate stack G is formed on a predetermined region of the substrate 40, and a hole h <b> 1 that exposes the substrate 40 is formed between the gate stack G. The region exposed through the hole h1 of the substrate 40 becomes a source and drain region in a subsequent process. The gate stack G includes material patterns 42, 44, 46, 48, and 50 (see FIG. 2) 42a, 44a, 46a, 48a, and 50a sequentially stacked on the substrate 40.

  Thus, after forming the gate stack G, a thin silicon oxide film covering the gate stack G is formed on the entire surface of the substrate 40, and the silicon oxide film is anisotropically etched. Due to the nature of the anisotropic etching, the silicon oxide film is removed in the entire region except the side surface of the gate stack G, and a silicon oxide pattern SP, that is, a spacer is formed only on the side surface of the gate stack G.

  Hereinafter, as shown in FIG. 3B, the gate stack G and the spacer SP are combined and displayed by the first gate G1. The spacer SP and the first to third insulating film patterns 42a, 46a, and 50a can be formed of different insulating films, but are preferably formed of the same insulating film, and are therefore displayed as the insulating film 52.

  Next, as described above, after forming the first gate G1 on the substrate 40, the substrate 40 is loaded into a predetermined annealing apparatus and annealed at a predetermined temperature for a predetermined time. For example, it is preferable to anneal at a temperature of 700 ° C. to 1100 ° C. for 30 seconds to 1 hour. During the annealing, silicon Si is deposited from the nanodot material film pattern 44a. By performing such annealing, crystal dots having a nano size are formed in the nanodot material film pattern 44a of the first gate G1, and thus the nanodot material film pattern 44a has a predetermined interval as shown in FIG. Thus, the nanodot layer 56 including the nano-sized crystal dots 54 distributed in the region is formed. The nanodot layer 56 is composed of a plurality of nanodot groups N1 separated by a predetermined interval, and each group N1 includes a plurality of nanodots 54 again. The nanodot layer 56 is a floating gate, and electrons are trapped in each nanodot 54. Accordingly, the nanodot layer 56 can be used as a storage electrode.

  After the nanodot layer 56 is formed on the first gate G1, the substrate 40 is taken out from the annealing apparatus.

  Next, as shown in FIG. 5, a conductive impurity is ion-implanted into the substrate 40 on which the first gate G1 is formed, and the source region S and the drain region D are introduced into predetermined regions of the substrate 40 exposed through the holes h1. Form.

  As a result, a transistor including the first gate G1, the source region S, and the drain region D is formed on the substrate 40. The first gate G1 includes the nanodot layer 56 that can be used as a storage electrode. The transistor can perform the same role as a single-electron memory device.

  Next, as shown in FIG. 6, a first metal layer 58 connected to the source region S through the hole h1 is formed on the first gate G1, and a second metal layer connected to the drain region D through the hole h1. 60 is formed. The first metal layer 58 and the second metal layer 60 are formed by forming a metal layer (not shown) filling the hole h1 on the first gate G1, and then forming the first metal layer 58 and the second metal layer on the metal layer. A photosensitive film pattern (not shown) that defines the layer 60 may be formed, and the metal layer may be etched using the photosensitive film pattern as an etching mask.

  <Second Embodiment>

  Unlike the first manufacturing method of the present invention, the method of manufacturing a memory device according to the second embodiment of the present invention (hereinafter referred to as the second manufacturing method of the present invention) first forms a nanodot layer, The second gate is characterized by being formed sequentially.

  Of the reference numerals described in the detailed description of the second manufacturing method of the present invention below, the same reference numerals as those described in the detailed description of the first manufacturing method of the present invention are the same as those in the first of the present invention. The same member as the member described in the manufacturing method is shown. Below, the description about the same member is abbreviate | omitted.

  Referring to FIG. 7, in the second manufacturing method of the present invention, first, a first insulating film 42 and a nanodot material film 44 are sequentially formed on a substrate 40. Depending on the thickness of the nanodot material film 44, the size of the nanodot formed in the subsequent process varies. Therefore, the nanodot material film 44 can be formed to have a different thickness depending on a desired nanodot size. For example, the nanodot material film 44 can be formed to a thickness such that the nanodot size is 2 nm to 5 nm.

  Next, as shown in FIG. 8, a nanodot material that exposes a predetermined region of the first insulating film 42 on the first insulating film 42 by performing a photo and etching process (photoetching) on the nanodot material film 44. A film pattern 44a is formed. A source region and a drain region are formed in a subsequent process on the substrate 40 below the exposed region of the first insulating film 42. After the nanodot material film pattern 44a is formed, the resultant product is annealed at a predetermined temperature and pressure for a predetermined time using a predetermined annealing apparatus. For example, it is preferable to anneal at a temperature of 700 ° C. to 1100 ° C. for 30 seconds to 1 hour.

  In this process, while silicon is deposited from the nanodot material film pattern 44a, nanodots start to be formed in the nanodot material film pattern 44a. As a result, the nanodot material film pattern 44a is formed at predetermined intervals as shown in FIG. The nanodot layer 56 includes a plurality of nanodots 54 that are uniformly distributed.

  Referring to FIG. 10, a fourth insulating film 62 and a conductive film 64 are sequentially formed on the first insulating film 42 so as to cover the nanodot layer 54. The fourth insulating film 62 can be formed of a predetermined oxide film, for example, a silicon oxide film. The fourth insulating film 62 can correspond to the second insulating film 46 of the first manufacturing method of the present invention. The conductive film 64 can be formed of a doped polysilicon film or a metal film. The conductive film 64 can correspond to the conductive film 48 of the first manufacturing method of the present invention.

  After the conductive film 64 is formed, a conductive film pattern 64 a is formed on a predetermined region of the fourth insulating film 62 by applying a photograph and an etching process to the conductive film 64. As shown in FIG. 11, the conductive film pattern 64a is preferably formed on the fourth insulating film 62 directly above the nanodot layer 56 so that the nanodot layer 56 and the conductive film pattern 64a face each other vertically. The conductive film pattern 64a is used as a floating gate.

  Next, as shown in FIG. 12, a fifth insulating film 66 covering the conductive film pattern 64a is formed on the fourth insulating film 62 to a predetermined thickness. The fifth insulating film 66 can be formed of a predetermined oxide film, for example, a silicon oxide film. In this case, since the first insulating film 42, the fourth insulating film 62, and the fifth insulating film 66 are all the same material film, they may be represented by one sixth insulating film 68 as shown in FIG. it can.

  Next, as shown in FIG. 14, a hole h2 that exposes the substrate 40 is formed in the sixth insulating film 68 between the conductive layer patterns 64a, and a second gate G2 is formed on the substrate 40 between the holes h2. . The second gate G2 includes a sixth insulating film 68, and a nanodot layer 56 and a conductive film pattern 64a that are sequentially stacked are included in the sixth insulating film 68 so as to be separated from each other in the vertical direction. The second gate G2 is equivalent to the first gate G1 of the first manufacturing method of the present invention.

  Next, as shown in FIG. 15, a conductive impurity is ion-implanted into a predetermined region of the substrate 40 exposed through the hole h2, thereby forming a source region S and a drain region D.

  Next, as shown in FIG. 16, the first metal layer 58 is brought into contact with the source region S on the second gate G2, and the second metal layer 60 is brought into contact with the drain region D, respectively. Form. The first and second metal layers 58 and 60 are spaced apart.

  <Third Embodiment>

  In a method of manufacturing a memory device according to the third embodiment of the present invention (hereinafter, third manufacturing method of the present invention), silicon is ion-implanted into a first insulating film used as a tunneling film, and the first insulating film 42 is formed. It is characterized in that after the patterning, nanodots are formed in the patterned first insulating film 42.

  Of the reference numbers described in the detailed description of the third manufacturing method of the present invention below, the same reference numbers as those described in the detailed description of the first manufacturing method or the second manufacturing method of the present invention are as follows: The same member as the member demonstrated by the 1st manufacturing method or the 2nd manufacturing method of this invention is shown. Below, the description about the same member is abbreviate | omitted.

  In the third manufacturing method of the present invention, first, a seventh insulating film 70 is formed on the substrate 40 as shown in FIG. The seventh insulating film 70 can be formed of a predetermined oxide film, for example, a silicon oxide film.

  Next, as shown in FIG. 18, the seventh insulating film 70 is doped with a seed for forming nanodots, for example, silicon Si (71). At this time, the seed is preferably implanted into the surface layer of the seventh insulating film 70. Nanodots are formed in the seventh insulating film 70. Therefore, the thickness of the seventh insulating film 70 can be changed according to the desired size of the nanodots. For example, the seventh insulating film 70 can be formed to a thickness such that the size of the nanodot is about 2 nm to 5 nm.

  Next, as shown in FIG. 19, a seventh insulating film pattern 70 a is formed on the substrate 40 by applying a photograph and an etching process to the seventh insulating film 70 doped with the seed. When the seventh insulating film pattern 70a is formed, a part of the seventh insulating film 70 is also removed and a predetermined region of the substrate 40 is exposed. The exposed region of the substrate 40 becomes a source region S and a drain region D in a subsequent process. In FIG. 19, the seed display is omitted.

  After the seventh insulating film pattern 70a is formed, the seventh insulating film pattern 70a is annealed with a predetermined annealing apparatus at a predetermined temperature and pressure for a predetermined time. For example, it is preferable to anneal at a temperature of 700 ° C. to 1100 ° C. for 30 seconds to 1 hour.

  During this annealing, a seed doped in the seventh insulating film pattern 70a, for example, silicon is deposited, nanodots start to be formed in the seventh insulating film pattern 70a, and finally, in the upper layer portion of the seventh insulating film pattern 70a, Nanodot layers 56 in which a plurality of nanodots 54 are uniformly distributed are formed at predetermined intervals (FIG. 20).

Next, as shown in FIG. 21, an eighth insulating film 72 is formed on the substrate 40 to cover the seventh insulating film pattern 70a. The eighth insulating film 72 can be formed of a predetermined oxide film, for example, a silicon oxide film SiO ₂ . The eighth insulating film 72 is equivalent to the second insulating film 46 of the first manufacturing method of the present invention and the fifth insulating film 66 of the second manufacturing method of the present invention.

  On the other hand, the seventh insulating film pattern 70a and the eighth insulating film 72 can be formed of different insulating films, but are preferably formed of the same insulating film. Thus, the seventh insulating film pattern 70a and the eighth insulating film 72 are shown as one insulating film 74 as shown in FIG. 22, and hereinafter, the insulating film 74 is referred to as a ninth insulating film.

  Next, as shown in FIG. 23, a conductive film 76 used as a control gate is formed on the ninth insulating film 74. The conductive film 76 can be formed of a doped polysilicon film or a metal film. Next, the conductive film 76 is patterned to form a conductive film pattern 76a at a position facing the nanodot layer 56 on the ninth insulating film 74 vertically as shown in FIG. The conductive film pattern 76a is a control gate.

Referring to FIG. 25, a tenth insulating film 78 covering the conductive film pattern 76a is formed on the ninth insulating film 74 to a predetermined thickness. The tenth insulating film 78 can be formed of a predetermined oxide film, for example, a silicon oxide film SiO ₂ . Since the tenth insulating film 78 and the ninth insulating film 74 are preferably formed of the same insulating film, the ninth and tenth insulating films 74 and 78 are combined into one insulating film 80 as shown in FIG. It shows with. Hereinafter, the insulating film 80 is referred to as an eleventh insulating film.

  Next, as shown in FIG. 27, the eleventh insulating film 80 is patterned to form a hole h3 and a third gate G3 through which the substrate 40 is exposed. The configuration of the third gate G3 is the same as that of the first gate (G1 in FIG. 3B) and the second gate (G2 in FIG. 14). The third gate G3 is formed between the holes h3. A predetermined region of the substrate 40 in which the source region and the drain region are formed is exposed through the hole h3.

  As described above and as can be seen from FIG. 27, the nanodot layer 56 is composed of a plurality of nanodot groups N1 separated by a predetermined interval, and each group N1 includes a plurality of nanodots 54 again. Similar to the first gate G1 and the second gate G2, the third gate G3 includes one nanodot group N1. Since the nanodot group N1 is completely contained in the eleventh insulating film 80, the nanodot 54 forming the nanodot group N1 is not exposed outside the third gate G3, and the outline of the nanodot 54 is also the third gate G3. It does not appear on the side.

  That is, the nanodot 54 does not exist in the region where the hole h3 of the eleventh insulating film 80 is formed. Therefore, in the process of forming the third gate G3, the nanodot 54 protrudes from the side surface of the third gate G3 due to the difference in etching rate between the nanodot 54 and the eleventh insulating film 80, or around the third gate G3. Therefore, it is possible to solve the problems of the conventional memory device that is uneven.

  As described above, after forming the third gate G3, the source region S and the drain region D are formed in the exposed region of the substrate 40 as shown in FIG. The source region S and the drain region D are formed by ion-implanting a conductive impurity of a type opposite to the conductive impurity implanted into the substrate 40 into a predetermined region of the substrate 40 exposed through the hole h3.

  Next, as shown in FIG. 29, the first metal layer 58 that contacts the source region S is formed on the third gate G3, and the second metal layer 60 that contacts the drain region D is formed. The first metal layer 58 and the second metal layer 60 are spaced apart.

  FIG. 30 is a photograph showing a cross section of the gate of the memory element formed by any one of the first to third manufacturing methods of the present invention described above.

  Referring to FIG. 30, it can be seen that the silicon nanodot layer C having a uniform size is formed on the substrate (black portion).

  FIG. 31 is a photograph showing a crystal of silicon nanodots contained in the gate of a memory device formed by any one of the first to third manufacturing methods of the present invention described above.

  Referring to FIG. 31, it can be seen that crystals of silicon nanodots (portions indicated by circles) are generally uniform in size.

  Although many items have been specifically described in the above description, they should be construed as examples of desirable embodiments rather than limiting the scope of the invention. For example, those skilled in the art can apply the manufacturing method of the present invention to other memory elements including nanodots. The nanodot layer can be formed of at least one layer. In the first manufacturing method of the present invention, the nanodot layer 56 can be formed after the source region S and the drain region D are formed. In the third manufacturing method of the present invention, the silicon doping process can be performed after the seventh insulating film pattern 70a is formed. Accordingly, the scope of the present invention is not determined by the described embodiments, but must be determined by the technical ideas described in the claims.

  The present invention can be used for various computers, portable communication terminals such as mobile phones and PDAs, home appliances having a data memory function such as camcorders and digital cameras, and various players having a memory function such as GPS and MP3.

1 is a cross-sectional view of a conventional flash memory device. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a first embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a method of manufacturing a memory device including a gate including uniformly distributed silicon nanodots according to a third embodiment of the present invention. 4 is a scanning electron microscope (SEM) photograph showing a cross section of a gate of a memory element formed by a manufacturing method according to an embodiment of the present invention. 4 is a scanning electron microscope photograph showing a silicon nanodot crystal included in a gate of a memory device formed by a manufacturing method according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 10s Source region 10d Drain region 12 Gate stack 12a Gate insulating film 12b Floating gate 12c Interlayer insulating film 12d Control gate 40 Substrate 42 First insulating film 44 Nanodot material film 46 Second insulating film 48 Conductive film 50 Third insulating film G gate stack h1 hole SP spacer 52 insulating film 54 crystal dot 56 nanodot layer N1 nanodot group S source region D drain region 58 first metal layer 60 second metal layer 62 fourth insulating film 64 conductive film 64a conductive film pattern 66 first 5th insulating film 68 6th insulating film h2 hole G2 2nd gate 70 7th insulating film 72 8th insulating film 74 9th insulating film 76 conductive film 78 10th insulating film 80 11th insulating film

Claims (18)

A first step of forming on the substrate an insulating film and a gate including a nanodot layer and a conductive film pattern that are sequentially stacked with a predetermined interval and are included in the insulating film;
Forming a source region and a drain region in contact with the gate on the substrate;
A method for manufacturing a memory device, comprising: a third step of forming a first metal layer and a second metal layer in the source region and the drain region, respectively. The first stage includes
Forming a gate stack including the insulating layer, a material layer for forming a nanodot layer, and a conductive layer pattern on the substrate;
2. The method of claim 1, further comprising: a first B step of converting the material film for forming the nanodot layer into a nanodot layer including at least one nanodot.   3. The method of claim 2, wherein in the step 1B, the gate stack is annealed until the material film for forming the nanodot layer becomes the nanodot layer. Step 1A includes
A first AA step of sequentially stacking a first insulating film, a material film for forming the nanodot layer, a second insulating film, a conductive film, and a third insulating film on the substrate;
A first AB stage of patterning the first insulating film, the material film for forming the nanodot layer, the second insulating film, the conductive film, and the third insulating film to form a laminate;
The method of claim 2, further comprising a first AC step of forming a spacer on a side surface of the stack.   3. The method of claim 2, wherein the second step is performed before the first B step. 6. The material film for forming the nanodot layer is formed of a SiO _2−X film (0 <X <1) or a Si ₃ N _4−X film (0 <X <1). A method for manufacturing the memory element according to the above.   4. The method of claim 3, wherein the annealing of the gate is performed at a temperature of 700 [deg.] C. to 1100 [deg.] C. for 30 seconds to 1 hour. The first stage includes
A first C stage of forming a first insulating film on the substrate;
Forming a material layer for forming a nanodot layer on the first insulating layer;
Forming a material film pattern for forming a nanodot layer defining a gate forming region by patterning the material film for forming the nanodot layer;
Converting the material film pattern for forming the nanodot layer to a nanodot layer including at least one nanodot;
Forming a second insulating film covering the nanodot layer on the resultant structure on which the nanodot layer is formed;
A first H stage of forming the conductive film pattern at a position corresponding to the nanodot layer of the second insulating film;
Forming a third insulating film covering the conductive film pattern on the second insulating film;
The method of claim 1, further comprising a first J step of patterning the first insulating film, the second insulating film, and the third insulating film to include the conductive film pattern and the nanodot layer. The manufacturing method of the memory element of description.   9. The method of manufacturing a memory element according to claim 8, wherein the first insulating film, the second insulating film, and the third insulating film are formed of the same material film. Material film for the nano dot layer formed, according to SiO _2-X film (0 <X <1) or Si ₃ N _4-X film according to claim 8, characterized in that formed at (0 <X <1) Method for manufacturing the memory element.   9. The method of claim 8, wherein in the first step F, the material film for forming the nanodot layer is annealed and converted into the nanodot layer.   The method of claim 11, wherein the annealing is performed at a temperature of 700 ° C. to 1100 ° C. for 30 seconds to 1 hour. The first stage includes
A first K step of forming a first insulating film on the substrate;
A first L step of implanting seeds for forming nanodots into the first insulating layer;
Patterning the seeded first insulating layer to form a first insulating layer pattern defining a gate forming region;
Forming a nanodot layer including at least one nanodot in the first insulating layer pattern;
Forming a second insulating layer covering the first insulating layer pattern including the nanodot layer on the substrate;
A first P stage of forming the conductive film pattern on a predetermined region corresponding to the upper side of the nanodot layer of the second insulating film;
Forming a third insulating film covering the conductive film pattern on the second insulating film;
The method of claim 1, further comprising a first R step of patterning the first insulating film, the second insulating film, and the third insulating film to include the conductive film pattern and the nanodot layer. The manufacturing method of the memory element of description.   14. The method of manufacturing a memory element according to claim 13, wherein the first insulating film, the second insulating film, and the third insulating film are formed of a silicon oxide film.   The method of claim 13, wherein the seed is silicon.   The method of claim 13, wherein the first M stage is performed before the first L stage.   The method of claim 13, wherein the nanodot layer is formed by annealing the first insulating layer pattern in the first N step.   The method of claim 17, wherein the annealing is performed at a temperature of 700 ° C. to 1100 ° C. for 30 seconds to 1 hour.