JP2005242398A - Simulation method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the highly precise simulation method of digital and analog connecting part by mix mode simulation. <P>SOLUTION: The net list of a mixture circuit is read (101), and the library of a logical cell and an analog element is read (102), and a table to define the inclination of waveform corresponding to the input state transition of the logical cell is set at the output terminal of the logical cell of a portion where a signal propagates from a digital circuit to an analog circuit (103), and the parasitic resistance and parasitic capacitance of an input terminal are set (104), and a net list is regenerated (105), and logical simulation/circuit simulation is carried out (106, 107), and the inclination is added to the waveform of the output terminal of the logical cell (108), and the signal is converted into a digital signal according to the voltage of the circuit simulator of the analog circuit part, and mix mode simulation is performed (109). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of mixed mode simulation executed in a digital / analog mixed circuit.

  In a semiconductor integrated circuit simulation method, a mixed mode simulation is a simulation of a circuit in which a digital circuit and an analog circuit are mixed. In general, an analog circuit confirms an electrical characteristic by a circuit simulation using SPICE or the like, and a digital circuit verifies a logical operation by giving a test pattern to a circuit to be simulated using a logic simulation.

  In mixed mode simulation, there is a process of synchronizing between two simulators because there is signal exchange between a circuit simulation signal of an analog circuit and a logic simulation signal of a digital circuit.

In the simulation with the logic simulator, 0, 1, indefinite, and high impedance states are taken, and transitions between these states are instantaneously changed.
Also, when simulating in time series in circuit simulation in an analog circuit and simulating its electrical characteristics, the waveform has time to rise and fall, and the state transitions instantaneously like a logic simulator There is nothing. In addition, the circuit simulation does not correspond to the state changing without the transition time.

  Therefore, in a portion where signal propagation from the digital circuit to the analog circuit occurs in the mixed mode simulation, a signal whose state transitions instantaneously in the logic simulator cannot be directly passed to the circuit simulator.

FIG. 11 is a diagram showing an example of a conventional digital / analog mixed semiconductor integrated circuit.
Reference numeral 1101 denotes a digital integrated analog semiconductor integrated circuit, 1102 denotes a digital circuit portion of the semiconductor integrated circuit 1101, 1103 denotes an analog circuit portion of the semiconductor integrated circuit 1101, and 1104 and 1105 denote the semiconductor integrated circuit 1101. 1106 is an output terminal of 1104, 1107 is an input terminal of the logic cell 1105, and 1108 and 1109 are analog circuit portions 1103 of the semiconductor integrated circuit 1101. 1110 and 1111 are capacitive elements in the analog circuit portion 1103 of the semiconductor integrated circuit 1101.

  In the mixed mode simulation, the digital unit 1102 of the semiconductor integrated circuit 1101 performs logic simulation, and the analog circuit unit of the semiconductor integrated circuit 1102 performs simulation independently of each other by circuit simulation. The digital circuit unit 1102 and the analog circuit unit 1103 The mutual simulation results of signal propagation between them are synchronized in time.

  Therefore, in the digital / analog mixed semiconductor integrated circuit 1101 to be simulated, a constant slope is given to the signal propagating from the digital circuit to the analog circuit at the connection between the digital circuit unit 1102 and the analog circuit unit 1103, and the circuit simulator side is reached. Passing signals. Set the same value for the part where signal propagation from all digital circuits to the analog circuit occurs in the simulation-compatible circuit, or manually set individual values for each node. There is a way to do it. An actual example will be described with reference to FIG. In FIG. 12, 1201 indicates a waveform input from the digital side to the analog circuit side, and 1202 indicates a waveform of logic simulation in the digital circuit.

  The waveform that is output from the output terminal 1106 of the logic cell 1104 and propagates to the analog circuit portion is 1202. However, since the state transition occurs instantaneously in the waveform as it is, it cannot be handled by the circuit simulator. Therefore, a slope is given when the result of the logic simulation changes state from the “H” level to the “L” level as in the waveform 1201. Similarly, when the state transition of the logic simulation changes from the “H” level to the “L” level, the waveform propagating to the analog circuit is similarly given a slope.

As shown in this example, a change in the signal input to the analog circuit unit 1103, that is, a change in voltage handled by the circuit simulator must be given with a certain slope.
A case where a signal propagates from the analog circuit 1103 to the digital circuit 1102 will be described with reference to FIG. In FIG. 13, 1301 is a waveform of the circuit simulator, and 1302 is a waveform inputted to the digital circuit unit side.

  Define the “H” level voltage and “L” level voltage on the digital circuit side with respect to the voltage level on the analog circuit side, and transfer the signal to the digital circuit side in consideration of the voltage on the analog circuit side Yes. For example, in the case of a simulation waveform 1301 of an analog circuit connected to the input terminal 1107 of the logic cell 1105, a certain voltage Vt is defined as a digital “H” level or “L” level switching voltage, and more than Vt A high voltage is treated as “H” level in the digital circuit, and a voltage lower than the voltage Vt is treated as “L” level in the digital circuit. That is, the voltage Vt at the time t in the signal 1301 on the analog circuit side. That is, in the waveform as a digital signal input to the logic cell 1107, the value input to the digital circuit side is “L” level before time t, and the value input to the digital circuit side after time t. Becomes “H” level.

As such a prior art, (patent document 1) (patent document 2) can be mentioned.
JP 2000-357183 A JP 2001-147948 A

  In a mixed mode simulation of a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixed, a signal transferred from the “H” level to the “L” level or from the “L” level to “ Even if a signal having a rise or fall time of 0 in the state transition to the H ″ level is input to the analog circuit, it cannot be simulated by the circuit simulator.

  For this reason, when a signal propagates from a digital circuit to an analog circuit before execution of the mixed mode simulation, the rise and fall times of the waveform must be manually specified, but from all the digital circuits in the semiconductor integrated circuit to the analog circuit. Even if the same value is set in the part where the signal propagates, in an actual semiconductor integrated circuit, the rise and fall times are considered to be the same in the state transition of the signal where the signal propagates from all the digital circuits to the analog circuit. I can't. It is also possible to individually specify the rise and fall times for the part where the signal propagates from the digital circuit to the analog circuit. However, before executing the mixed mode simulation on the entire semiconductor integrated circuit, the analog circuit from each digital circuit A simulation must be performed to determine the rise and fall times in the state transition of the signal where the signal propagates to the circuit.

  Also, the logic cell on the digital circuit side is a circuit designed using MOS transistors, and the actual operation is modeled for simulation with a logic simulator, so in a multi-input logic cell, the state transition of each input Depending on the state of the output waveform, the rise and fall times of the output waveform may differ, so when simulating the operation of an actual semiconductor integrated circuit, the rise time and rise time of the output waveform are dependent on the state transition of the final drive cell input on the digital circuit side. It is necessary to change the downtime. When a signal is propagated from the analog circuit side to the digital circuit side, the result of the circuit simulator of the analog circuit is changed to a digital signal according to the voltage. The circuit simulation of the analog circuit portion in the conventional mixed mode simulation of the digital / analog mixed circuit performs a simulation of a portion composed of analog elements in the circuit. However, an actual semiconductor integrated circuit of a logic cell is generally configured using MOS transistors, and a gate wiring resistance and a gate parasitic capacitance exist on the input side of the logic cell. However, in most current mixed mode simulations, the mixed mode simulation is not executed in consideration of the wiring resistance of the gate and the parasitic capacitance of the gate.

  An object of the present invention is to provide a highly accurate simulation method for digital and analog connection portions in mixed mode simulation.

  In view of the above problems, the semiconductor integrated circuit simulation method of the present invention is a mixed-mode simulation method in which analog circuits of a digital circuit are mixed, and the process of reading into a netlist simulator and the propagation of signals from the digital circuit to the analog circuit Table setting process for setting the slope of the signal propagating from the digital circuit to the analog circuit at the output terminal of the logic cell to define the slope of the rise and fall of the waveform corresponding to the state transition of the input of the logic cell and the analog A resistance-capacitance setting process for setting the parasitic resistance and parasitic capacitance of the input terminal of the logic cell to the input terminal of the logic cell of the part where the signal propagates from the circuit to the digital circuit, and the part where the signal propagates from the analog circuit to the digital circuit The parasitic resistance of the input terminal of the logic cell is connected to the input terminal of the logic cell. The process of regenerating the netlist including the parasitic resistance and parasitic capacitance set in the capacitance setting process, the process of executing the logic simulation, the process of executing the circuit simulation, and the two processes Based on the result of logic simulation and the result of circuit simulation, the slope of the waveform propagating from the digital circuit set in the table setting process to the analog circuit is input to the logic cell set in the output terminal in the table setting process. The digital analog data synchronization process that detects the state transition and determines the slope of the signal that propagates to the analog circuit, and the analog digital interface setting process at the input terminal when the signal propagates from the analog circuit to the digital circuit The parasitic resistance and parasitic capacitance of the input terminal And having an analog-to-digital data synchronization process of reflecting adding circuit to the result of the analog simulation made.

  According to this configuration, by repeating the logic simulation process, the circuit simulation process, the digital analog data synchronization process, and the analog digital data synchronization process, it is possible to realize a simulation of a digital / analog mixed circuit, thereby A highly accurate simulation can be realized.

Embodiments of the present invention will be described below with reference to the drawings. This embodiment will be described together with claim 3.
FIG. 1 is a process flow diagram of a semiconductor integrated circuit simulation method of the present invention.

  101 is a process of reading a netlist from a circuit created from a digital / analog mixed circuit, 102 is a process of reading a library of logic cells and analog elements, and 103 is an output terminal of a logic cell in a portion where signals are propagated from the digital circuit to the analog circuit Table setting process for setting the slope of the signal propagating from the digital circuit to the analog circuit to define the rising and falling slope of the waveform corresponding to the state transition of the input of the logic cell, 104 is a signal from the analog circuit to the digital circuit A resistance-capacitance setting process for setting the parasitic resistance and parasitic capacitance of the input terminal of the logic cell to the input terminal of the logic cell in the part where the signal propagates, 105 is the parasitic resistance and parasitic of the input terminal of the logic cell set in the process 104 The process of regenerating the netlist used in the simulation including the capacity value 106 is a process of executing a logic simulation of the digital circuit unit, 107 is a process of circuit simulation of the analog circuit unit, 108 is a signal from the digital circuit unit to the analog circuit unit based on the simulation results in steps 106 and 107, respectively. In the propagation part, the table set in step 103 and the output terminal of the logic cell are selected to select the slope of the table corresponding to the state transition of the input terminal of the logic cell connected to the analog element. A digital analog synchronization process for adding a slope selected in the table to the waveform, 109 is applied to the input terminal of the logic cell to which the analog element is connected to the input terminal of the logic cell when the signal propagates from the analog circuit to the digital circuit. Depending on the input analog circuit circuit simulator voltage An analog-to-digital data synchronization process of changing into a digital signal, the process 106, process 107, process 108, it is possible to perform highly accurate simulation of digital and connection portions of the analog by repeatedly executing the process 109.

Furthermore, each process is demonstrated in detail.
Hereinafter, a specific operation process of the process 103 will be described with reference to FIG.
FIG. 2 shows the slope of the signal propagated from the digital circuit to the analog circuit at the output terminal of the logic cell where the signal propagates from the digital circuit to the analog circuit. It is a process flow figure of the table setting process which sets the table which defines inclination.

  201 is a process of determining whether or not there is a cell that has not been processed in the table setting process in all the output terminals of the logic cell in which the output terminal of the logic cell is connected to the analog element in the digital / analog mixed circuit; 202 is a step of determining whether or not a table setting process has been performed on all output terminals of cells that have not been processed in the table setting process at the output terminal in step 201, and 203 is a cell of the corresponding cell in step 202. The process of acquiring a table prepared in advance according to the name and the output terminal of the cell, 204 can be realized by repeating the process of setting the table acquired in process 203 as the output terminal of the logic cell.

Further, a specific operation process of the process 104 will be described with reference to FIG.
FIG. 3 shows that the parasitic resistance and parasitic capacitance of the input terminal of the logic cell are set at the input terminal of the logic cell where the signal propagates from the analog circuit to the digital circuit, and the parasitic signal is transmitted to the signal propagated from the analog circuit to the digital circuit. It is a process flow figure of the resistance capacity setting process for changing a waveform in consideration of the value of resistance and parasitic resistance.

  301 is a process of determining whether or not there is a cell that has not been processed in the resistance-capacitance setting process in all the input terminals of the logic cell in which the input terminal of the logic cell is connected to the analog element in the digital / analog mixed circuit. , 302 is a process of determining whether or not a resistance capacitance setting process has been performed on all input terminals of a cell that has not been processed in the resistance capacitance setting process in step 301, and 303 corresponds to step 302. A process of acquiring a parasitic resistance and a parasitic capacitance prepared in advance according to the cell name of the cell and the input terminal of the cell. 304 sets the parasitic resistance and the parasitic capacitance acquired in process 303 as the input terminal of the logic cell. This is possible by repeating the process.

The process 105 will be described in detail with reference to FIGS. 4, 5, and 6.
In FIG. 4, 401 is a part of a digital / analog mixed semiconductor integrated circuit, 402 is a part of a digital circuit part of the semiconductor integrated circuit 401, and 403 is a part of an analog circuit part of the semiconductor integrated circuit 401. , 404 is a cell symbol in the digital circuit unit 402 having an inverter logic function, 405 is an input terminal IN of the cell 404 having an inverter logic function, and 406 is an output terminal of the cell 404. , 407 are resistance element symbols in the analog circuit unit 403, and 408 is a capacitance symbol in the analog circuit unit 403.

In FIG. 5, 501 is a parasitic resistance of the input terminal 405 of the logic cell 404, and 502 is a parasitic capacitance of the input terminal 405 of the logic cell 404.
In FIG. 6, reference numeral 601 denotes data on the parasitic resistance value and the parasitic capacitance value of the input terminal 405 of the cell 404.

  When a signal propagates to the digital circuit unit, in the normal circuit simulation, the parasitic resistance and parasitic capacitance of the input of the logic cell 404 set in the step 104 are further treated as elements in the circuit simulator. In FIG. 5, the net list is regenerated in the process 105 of re-generating the net list by adding a circuit configuration as indicated by reference numeral 503. The example shown in FIG. 5 is merely an example, and the same function can be realized even if an analog function description is used for an additional configuration other than that realized by circuit elements such as actual resistors and capacitors.

The process 108 will be described in detail with reference to FIGS.
In FIG. 7, reference numeral 701 denotes a part of the digital integrated analog semiconductor integrated circuit, reference numeral 702 denotes a part of the digital circuit part of the semiconductor integrated circuit 701, and reference numeral 703 denotes a part of the analog circuit part of the semiconductor integrated circuit 701. 704 is a cell symbol in the digital circuit portion 702 having an AND logic function, 705 and 706 are input terminals IN1 and IN2 of the cell 704 having an AND logic function, and 707 is the cell 704 Reference numeral 708 denotes a resistance element symbol in the analog circuit portion 703, and reference numeral 709 denotes a capacitance symbol in the analog circuit portion 703.

In FIG. 8, reference numeral 801 denotes an example of a table for setting a slope with respect to the output waveform from the output terminal 707 of the cell 704 having the AND logic function.
FIG. 9 shows a part of the simulation waveform of the semiconductor integrated circuit 701. The waveform from the output terminal 707 rises and rises based on the table 801 in accordance with the state transition of the input terminals 705 and 706 of the cell 704. An example of a signal when an inclination is given to the downstream signal portion is shown.

  As in the example of the simulation waveform 901 in FIG. 9, the IN1 signal of the input terminal 705 of the cell 704 in the semiconductor integrated circuit 701 is “H” level and the IN2 signal of 706 is “L” level to “H” at time t1. When the signal rises to the level, as a result of the logic simulation, the waveform of the output terminal 707 of the cell 704 becomes a signal with no slope at the signal rise / fall, as indicated by 904. In this case, the input signal described in the table 801 is changed. In this example, IN1 of the input terminal 705 is fixed at “H” level, and IN2 of the input terminal 706 rises from “L” level to “H” level. ing. In this case, a waveform 905 obtained by adding the slope of the table 801 to the logic simulation result of the output terminal 707 is a waveform that propagates to the analog circuit. The same applies when the input of the IN2 terminal of the input terminal 706 falls from the “H” level to the “L” level at time t2.

  In the digital-analog mixed simulation method of the present invention, the slope value of the table that defines the rising and falling slope of the waveform corresponding to the state transition of the input of the logic cell is connected to the output terminal of the logic cell in step 103. If the function varies depending on the values of the capacitance element and the resistance element, the process and inclination of searching for the capacitance element and the resistance element connected to the output terminal of the logic cell are calculated in the flow described with reference to FIG. It can be realized by adding a process to do. The processing flow is shown in FIG.

  FIG. 10 shows the rise and fall of the waveform corresponding to the state transition of the input of the logic cell at the output terminal of the logic cell where the signal propagates from the digital circuit to the analog circuit. FIG. 5 is a process flow diagram of a table setting process when a slope value is a function that changes according to the values of a resistance element and a capacitance element connected to the output terminal of the logic cell in a table that defines the slope.

  1001 is a process of determining whether all the output terminals of the logic cells whose logic cell output terminals are connected to the analog elements in the digital / analog mixed circuit are cells that have not been processed in the table setting process; 1002 is a step of determining whether or not a table setting process has been performed on all the output terminals of cells that have not been processed in the table setting process at the output terminal in step 1001, and 1003 is connected to the output terminal of the logic cell. 1004 is a process of searching for a resistive element and a capacitive element, and 1004 is a process of determining whether there is an unsearched element among the resistive element and the capacitive element connected to the output terminal of the logic cell. A process of acquiring a table prepared in advance according to the cell name of the corresponding cell and the output terminal of the cell; 003 and the step of calculating the slope of the output waveform of the logic cell from the values of the resistance element and the capacitive element searched in step 1004 and the table acquired in step 1005, and 1007 the slope calculated in step 1006 at the output terminal of the logic cell. This process can be realized by repeating these processes.

  As a result, even in the same type of logic cell, it is possible to set a detailed value for each cell because the slope of the output waveform differs depending on the element connected to the output terminal. Further, the resistance element and the capacitor element searched in the process 1003 can be realized by this flow even by searching including the resistance of the wiring and the parasitic resistance of the wiring, the parasitic resistance of the terminal of the transistor, and the parasitic capacitance component.

  The net list of the analog circuit section can be easily realized by using the net list including the parasitic resistance and the parasitic capacitance extracted from the layout cell of the analog circuit section.

  As described above, according to the present embodiment, the digital analog mixed semiconductor integrated circuit simulation method first reads a netlist from a circuit created from a digital analog mixed circuit, and then reads a library of logic cells and analog elements. Further, the slope of the signal rising from the digital circuit to the analog circuit at the output terminal of the logic cell where the signal propagates from the digital circuit to the analog circuit is the slope of the rising or falling edge of the waveform corresponding to the state transition of the input of the logic cell. Next, set the parasitic resistance and parasitic capacitance of the input terminal of the logic cell to the input terminal of the logic cell where the signal propagates from the analog circuit to the digital circuit. Replay netlist for simulation including parasitic resistance and capacitance values Later, a logic simulation is performed on the digital circuit unit and an analog circuit unit is simulated, and the output terminal of the logic cell is set in the part where the signal propagates from the digital circuit unit to the analog circuit unit based on the simulation result. Select the slope of the table corresponding to the state transition of the input terminal of the logic cell connected to the analog element, and add the slope selected in the table to the waveform of the output terminal of the logic cell, and perform analog / digital synchronization When analog signals are propagated from the circuit to the digital circuit, the analog simulation voltage input to the logic cell input terminal connected to the logic cell input terminal is changed to a digital signal. Repeatedly executes digital and analog It is possible to perform highly accurate simulation of the connection portion of the grayed.

  It should be noted that the present invention can be realized by using a conventional method for a netlist creation method of a semiconductor integrated circuit, a logic simulation, a circuit simulation, and a method of changing a circuit simulation result to a digital signal according to a voltage. .

  As described above, the semiconductor integrated circuit simulation method of the present invention includes a process of reading a netlist from a circuit created from a digital / analog mixed circuit, a process of reading a library of logic cells and analog elements, and a signal from the digital circuit to the analog circuit. Table setting process for setting the slope of the signal propagating from the digital circuit to the analog circuit at the output terminal of the logic cell where the signal propagates defines the slope of the rising and falling edges of the waveform corresponding to the state transition of the input of the logic cell A resistance-capacitance setting process for setting the parasitic resistance and parasitic capacitance of the input terminal of the logic cell to the input terminal of the logic cell where the signal propagates from the analog circuit to the digital circuit; Used for simulation including parasitic resistance and parasitic capacitance values of cell input terminals The process of regenerating the netlist, the process of executing the logic simulation of the digital circuit part, the process of performing the circuit simulation of the analog circuit part, and the analog from the digital circuit part based on the simulation results of the logic simulation and the circuit simulation, respectively. In the portion where the signal propagates to the circuit unit, the table set in the table setting process and the inclination of the table corresponding to the state transition of the input terminal of the logic cell where the output terminal of the logic cell is connected to the analog element are selected. A digital analog synchronization process for adding the slope selected in the table to the waveform of the output terminal of the logic cell, and a logic in which an analog element is connected to the input terminal of the logic cell when a signal propagates from the analog circuit to the digital circuit. Analog input to the cell input terminal Based on the simulation result of the circuit composed of the parasitic resistance and parasitic capacitance of the input terminal set in the process according to the voltage of the circuit simulator in the part, it is converted into the digital signal according to the voltage of the analog simulation result The analog / digital data synchronization process is changed, and the logic simulation process, circuit simulation process, digital / analog synchronization process, and analog / digital synchronization process are repeatedly executed.

  Therefore, according to the semiconductor integrated circuit simulation method of the present invention, output is performed in accordance with the state transition of the input of the logic cell in which the analog circuit is connected to the output terminal at the portion where the signal propagates from the digital circuit portion to the analog circuit portion. Change the slope value of the waveform and include the parasitic resistance and parasitic capacitance in the actual circuit at the input terminal of the logic cell where the analog signal is input in the part where the signal propagates from the analog circuit to the digital circuit. By performing the circuit simulation with the list, it is possible to perform a simulation with high accuracy of the connection portion between the digital circuit portion and the analog circuit portion.

  According to another semiconductor integrated circuit simulation method of the present invention, a capacitor element in which a slope value of a table defining a rising / falling slope of a waveform corresponding to a state transition of an input of a logic cell is connected to an output terminal of the logic cell. If the function varies depending on the value of the resistor element, a process of searching for a capacitor element and a resistor element connected to the output terminal of the logic cell and a process of calculating a slope are performed.

  Therefore, according to the semiconductor integrated circuit simulation method of the present invention, even in the case of the same logic cell, when the configuration of the analog element connected to the output terminal is different, the signal propagated from the output terminal of the logic cell to the analog circuit has a different slope. By setting this value, it is possible to perform a more accurate simulation of the connection portion between the digital circuit portion and the analog circuit portion.

  The present invention can be used in the design process of a semiconductor integrated circuit having a digital-analog connection portion.

The flowchart which shows the procedure of the simulation method of the semiconductor integrated circuit which is one embodiment of this invention Processing flow showing procedure of step 103 of semiconductor integrated circuit simulation method according to one embodiment of the present invention Processing flow showing procedure of step 104 of semiconductor integrated circuit simulation method according to one embodiment of the present invention The figure which showed an example of the circuit which is going to implement | achieve the simulation method of the semiconductor integrated circuit which is one embodiment of this invention The figure which showed an example of the circuit which performed the process of the process 104 with the simulation method of the semiconductor integrated circuit which is one embodiment of this invention The figure which showed an example of the value of the parasitic resistance of the input terminal of a logic cell used in the process 104 of the simulation method of the semiconductor integrated circuit which is one embodiment of this invention, and the value of a parasitic capacitance The figure which showed an example of the circuit which is going to implement | achieve the process of the process 103 with the simulation method of the semiconductor integrated circuit which is one embodiment of this invention The figure which showed an example of the table which defined the inclination of the waveform set to the output terminal of the logic cell used in the process 103 of the simulation method of the semiconductor integrated circuit which is one embodiment of this invention The figure which showed an example of the simulation waveform at the time of performing the process of the process 108 of the simulation method of the semiconductor integrated circuit which is one embodiment of this invention Processing flow chart in the case where the waveform inclination table is a function of the resistance value and the capacitance value in the process 108 of the semiconductor integrated circuit simulation method according to the embodiment of the present invention. Diagram showing an example of a digital-analog mixed semiconductor integrated circuit The figure which shows the conventional example of the signal which propagates from the digital circuit section to the analog circuit section in the mixed mode simulation The figure which shows the conventional example of the signal which propagates from the analog circuit to the digital circuit in the mixed mode simulation

Explanation of symbols

101 Netlist reading process 102 Library reading process 103 Table setting process 104 Resistance capacitance setting process 105 Netlist regeneration process 106 Logic simulation process 107 Circuit simulation process 108 Digital analog synchronization process 109 Analog digital synchronization process

Claims (5)

  The process of reading a netlist created from a digital / analog mixed circuit, the process of reading a library of logic cells and analog elements, and the input of a logic cell to the output terminal of the logic cell where the signal propagates from the digital circuit to the analog circuit. Table setting process for defining rising and falling slopes of output waveform corresponding to state transition, process for executing logic simulation of digital circuit part, process for circuit simulation of analog circuit part, logic simulation process and circuit Logic cell in which the table set in the table setting process and the output terminal of the logic cell are connected to the analog element in the part where the signal propagates from the digital circuit part to the analog circuit part based on the simulation results in the simulation process. Input terminal status Simulation method of a semiconductor integrated circuit, characterized in digital analog synchronization process of adding a tilt said selected table to the waveform of the output terminal of the logic cell by selecting the inclination of the table corresponding to the transfer.   The process of reading a netlist from a circuit created from a digital / analog mixed circuit, the process of reading a library of logic cells and analog elements, and the logic cell input terminal of the part where the signal propagates from the analog circuit to the digital circuit. A resistance capacitance setting process for setting the parasitic resistance and parasitic capacitance of the input terminal, and the netlist used for the simulation including the values of the parasitic resistance and parasitic capacitance of the input terminal of the logic cell set in the resistance capacitance setting process are reproduced. A digital signal corresponding to a voltage obtained as a result of a simulation performed in a circuit simulation process using a netlist generated in the process of generating and regenerating the netlist when a signal propagates from an analog circuit to a digital circuit. Having a changing analog-digital data synchronization process Simulation method of a semiconductor integrated circuit according to claim.   4. The semiconductor integrated circuit simulation method according to claim 1, wherein the semiconductor integrated circuit simulation method according to claim 1 is combined with the semiconductor integrated circuit simulation method according to claim 2.   In the semiconductor integrated circuit simulation method, a table defining a rising / falling slope of an output waveform corresponding to an input state transition of a logic cell at an output terminal of a logic cell in a portion where a signal propagates from the digital circuit to an analog circuit Depends on the resistance and capacitance element connected to the output terminal of the logic cell, and the process of searching for the resistance and capacitance element connected to the output terminal of the logic cell before the table setting process, and the search in the process 2. The method for simulating a semiconductor integrated circuit according to claim 1, wherein a value of the slope of the waveform is calculated based on the values of the resistance and the capacitance element, and a table is set at the output terminal of the logic cell.   5. A semiconductor integrated circuit simulation method realized by combining the semiconductor integrated circuit simulation method according to claim 3 and the semiconductor integrated circuit simulation method according to claim 4.

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