JP2005236985A - Multivalued logic circuit and multivalued specific value logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose novel algebra of an n-ary number (logics of an n-ary number) by adding features, such as freely released development function, an output opening function, a small number components, a small ON-voltage output, noise resistance, switching loss/power loss reduction, a transient power source short-circuiting prevention function and malfunction reduction. <P>SOLUTION: There are power lines V0-V(n-1) of which potentials increase in this order, when a predetermined number is (n) (≥3), and "a bidirectional switch connecting 'back gates and sources' of two NMOSs and gates with each other between "a power line Vm corresponding to a specific value (m)" and an output terminal Out" is connected. Between a power line V(m+1) and a power line V(m-1), a discrimination section (a connector of transistors 1, 2, 17 and a resistor 19) is provided for discriminating whether the potential of an input terminal In is "between both plus and minus threshold potentials with a potential of a power line Vm as a criterion", and the bidirectional switch is on-driven, if the potential of the input terminal In is between both the threshold potentials, and is driven off if not. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  In the first and second inventions, a multi-value logic circuit (or multi-adic system) in which each value of multi-value (≧ 3) corresponds to the potential or voltage of each potential supply means (eg, power supply line) one-to-one. Logic circuit). These multi-valued logic circuits and the like are converted into multi-value arithmetic means (or multi-adic arithmetic means), multi-value storage means, multi-value computer (or multi-value computer. Especially 4, 8, "10", 16, 32, 64 , “100”, 128-base computer, etc.), multi-value modulation communication means, multi-value information recording means, and multi-value control means (or multi-value control means).

In the case of the first invention, it can be configured without using a normally-on gate-insulated FET (eg, depletion mode MOS FET), the voltage output method is not limited by the input voltage, Be free.
In the case of the second invention developed from the first invention, the inventor brings the concept of “specific value” to multi-valued logic (or multi-ary logic), and “the input numerical value is an input specific value (one or Predetermined multi-valued logic processing (based on whether it is between two or more), whether it is larger or smaller (or above or below), whether or not it is between a plurality of specific values for input, and whether they are equal or not equal Or a multi-adic logic process), and outputs a specific potential or a specific voltage corresponding to a specific value for output according to the processing result, or opens the output.
For this reason, the multi-valued logic function can be easily expressed and expressed by human words (eg circuit names) or mathematical expressions without using a truth table, and multi-values can be expressed by such words and mathematical expressions. If a logic circuit can be expressed and expressed, its function can be known from the expression and notation.
From another point of view, the present inventor considers that “the construction of a new algebra (multi-ary logic) instead of a binary Boolean algebra (binary logic)”.

  In both the first and second inventions, as long as different output potentials or output voltages are not output at the same time, the exit means (eg, output terminals) of a plurality of multi-valued logic circuits are connected to each other {, in some cases, the entrance means ( Example: input terminals etc.) can also be connected to develop and enhance logic functions. Both inventions have such a degree of freedom, and are free-release and evolutionary multi-value logic circuits (or multi-ary logic circuits). In addition, since the on-voltage of the output section is small, the switching loss can be reduced, and since the on-voltage is small, each power supply voltage can be reduced and the overall power loss can be reduced. Furthermore, since “plus and minus fluctuations with reference to the output potential”, that is, “error from the output potential during pull-up and pull-down” is reduced, the logic circuit in the next stage is “corresponding to the input potential. It is hard to mistake "input numerical value". In addition, it is difficult for noise to be applied to the output signal, and malfunction due to noise is less likely to occur in the next-stage circuit or the like.

A multi-value logic circuit is disclosed in JP-T-2002-517937 as a prior art. FIG. 2 shows the basic circuit (three-value one-input) of this Omoto that has been simplified for the sake of explanation. In addition, the circuit diagram of the patent publication is correct because it is an error (the normally-on display and the normally-off display of the gate insulating FET are opposite to each other). The potentials of the power supply lines V0, V1, and V2 are sequentially set to potentials v0, v1, and v2.
In the circuit of FIG. 2, normally-on type (depletion mode) P, N-channel gate insulating FETs (Q2 and Q3) 2 are used as output means for outputting an intermediate potential v1 between the highest potential v2 and the lowest potential v0. Bidirectional switching means with two connected in series is used. In addition, the circuit of FIG. 2 can also be used as a determination means for determining whether the “input numerical value corresponding to the input potential” corresponds to “the numerical value corresponding to the intermediate potential v1”. “On driving”, that is, “a characteristic that both transistors Q2 and Q3 are turned on when the potential difference (= voltage) between the input potential and the intermediate potential v1 is zero” is used.
The combined use of the output means and the determination means has an advantage that the number of parts is small for the logical function and the circuit configuration is simple. In the operation, if the input potential is v0, the output potential is v2, if the input potential is v1, the output potential is v1, and if the input potential is v2, the output potential is v0.

  Note that two P- and N-channel junction FETs cannot be used in place of these gate-insulated FETs. This is because when the transistor Q3 is a P-channel junction FET, when the input potential is v0 and the transistor Q1 is on, a power supply short-circuit current flows from the transistor Q1 to the input terminal In via the drain-gate PN junction of the transistor Q3. It is because it ends. On the other hand, in the case where the transistor Q2 is an N-channel junction FET, the gate-drain PN junction of the transistor Q2 clamps the upper limit of the input potential to the power supply potential v1. This is because a power supply short circuit current flows. In addition, since the gates and sources of the transistors Q2 and Q3 are connected in parallel, if a junction FET is used, the PN junction between the gates and sources is connected in reverse parallel, and sufficient gate reverse is provided for each. This is because a bias voltage cannot be applied.

Problem 1

For this reason, the first problem is that “a gate-isolated normally-on FET must be used as a part of it”, that is, “it is desired to be configured without using a normally-on gate-isolated FET”. There are points.
If normally-off type switching means can be used for all switching means, it is convenient to increase the number of parts to be used. Similarly, if bipolar mode transistors can be used, it is convenient to increase the number of parts to be used.

Problem 2

Further, there is a second problem that “a multi-value logic circuit having four or more values causes a power supply short-circuit current to flow transiently when the power is turned on”.
This is because in the case of a multi-value logic circuit having four or more values, there are two or more intermediate power supply potentials described above, and each of the intermediate power supply potentials is “both two normally-on gate-insulated FETs connected in series as described above. Since the “directional switching means” are connected one by one, at least one or more “combinations in which two normally-on bidirectional switching means are connected between two power supply potentials (= between both power supply ends)” Because there is. As a result, for example, in the case of a quaternary logic circuit, each gate voltage is zero before the power is turned on, and the bidirectional switching means is in the on state, and after the power is turned on, each power supply voltage rises and at least one bidirectional switching is performed. This is because the power supply short-circuit current flows until a sufficient gate reverse bias voltage is applied to each gate of the means. The problem with this power supply short circuit is that if a digital circuit is configured using a large number of multi-valued logic circuits, a very large power supply short-circuit current will flow when the power is turned on, and the power supply voltage cannot be raised, making it unusable. Or the power line is burned out by repeated power-on, or the semiconductor near the power line is damaged by thermal damage or distortion.

Problem 3

Furthermore, the third is that there are multi-valued logic processing functions that cannot be realized and unknown multi-valued logic processing functions because bidirectional switching means for limiting the relationship between the input voltage and the output voltage is used. There is a problem.
First, “restriction of relationship between input voltage and output voltage” will be described. For the sake of explanation, consider the case where the transistors Q1 and Q4 are removed from the circuit of FIG. 2 and the power supply potential v0 (0 volts) is input to the input terminal In. Here, if the potential of the output terminal Out becomes v0 for some reason, the drain and gate of the P-channel transistor Q3 are “the same potential”, that is, “substantially the same as being directly connected”. . For this reason, the transistor Q3 becomes conductive, so that both source potentials of the transistors Q3 and Q2 eventually become the potential v0, that is, the gate-source voltages of the transistors Q3 and Q2 become zero. As a result, normally-on transistors Q3 and Q2 are completely turned on, so that both transistors Q3 and Q2 short-circuit between the power supply potentials v1 and v0.
In order to prevent this power supply short circuit, when the input potential is v0 (0 volts), the source potential of the transistor Q2 is set to plus 1.75 volts or more, and the gate-source voltage of the transistor Q2 is set to the on / off threshold value. The voltage must be minus 1.75 volts or less. At this time, since the transistor Q3 is turned on, the potential of the output terminal Out is also set to plus 1.75 volts or more. That is, when the input potential is v0, the output potential must be plus 1.75 volts or more. In other words, the “circuit of FIG. 2 assuming that the transistors Q1 and Q4 are removed for explanation” can only be used in this way.
This is the same even when the input potential is v2 (5 volts). The positions of the transistors Q2 and Q3 are interchanged, and the output potential must be (v2-1.75 volts) = plus 3.25 volts or less. . Actually, in the original circuit of FIG. 2, when the input potential is v0, the transistor Q1 pulls up the output potential to v2, and when the input potential is v2, the transistor Q4 pulls down the output potential to v0. Therefore, when the input potential is v0, the output potential v0 cannot be output or released, and when the input potential is v1, the output cannot be opened, and the input potential is v2. In this case, the output potential v2 cannot be output or the output cannot be opened. For this reason, the relationship between the input voltage and the output voltage is limited in the circuit of FIG. 2 and the “circuit from which the transistors Q1 and Q4 are removed from the circuit of FIG. 2”.

Next, mathematically considered “super-explosive size of multi-valued logic processing” will be explained. For example, in the case of binary logic with 1 digit (digits) and 2 inputs, there are 4 combinations of input variables, that is, the square of 2 = 4 sets, and in each of the 4 sets, the output method has numerical values “0” and “1”. Since there are two types, the number of logic processes or logic functions is the fourth power of 2 = 16. That is, there are 16 different output patterns for four sets of input variables “0 and 0”, “0 and 1”, “1 and 0”, and “1 and 1” with two binary digits and one input. It is.
Reference: "Introduction to Transistor Circuit Lecture 5: Digital Circuit Concept" (published on May 20, 1981 by Ohm Corporation). 34 “Table 3. 8 Logical functions consisting of two input variables”.
Similarly, in the case of ternary logic with one digit and two inputs, there are 9 combinations of input variables, that is, the square of 3 = 9 sets, and in each of the 9 sets, the output method has numerical values “0”, “1”, Since there are three types of “2”, the types of logical processing or logical functions increase at a time to 3 9 = 19,683. That is, nine sets of input variables “0 and 0”, “0 and 1”, “0 and 2”, “1 and 0”, “1 and 1”, “1 and 2”, which are ternary 1-digit 2-input, That is, there are 19,683 different output patterns for “2 and 0”, “2 and 1”, and “2 and 2”.
Similarly, in the case of 4-digit logic with 1 digit and 2 inputs, the combination of input variables is the square of 4 = 16 sets, and in each of the 16 sets, numerical values “0”, “1”, “2” are used for output. , “3”, there are four types of logic processing or logic functions, which are 4 16 = 4,294,968,000. Similarly, in the case of 5-digit logic with 1 digit and 2 inputs, 5 to the 25th power = 2.9980233 × (10 to the 17th power) type, and in the case of 10-value logic with 1 digit and 2 inputs, the “10 to the 100th power” type. .

  As the number of multi-values (N for N values, 10 for 10 values, and so on) increases, the type of multi-value logic processing increases “super-explosively”. This means that if a multi-value logic circuit having a multi-value logic processing function optimal for “required logic processing” is realized and selected, even a small number of circuits can cope with “various logic processing required”. This suggests that "It is similar to software programming in terms of problem-handling ability, and a completely new and extremely large possibility may be buried in multi-valued logic and multi-valued logic." doing. Perhaps multi-digit computers, especially decimal computers, may outperform future binary quantum computers. (The rationale and reason will be described later.) In addition, there are “meaningful” and “nonsense” in logical functions and logical processing, and the number of types of “significant logical processing” is Even if it is a fraction of that, there is no change in the type of “super-explosive increase”.

  Therefore, even though the number of multi-valued logic circuits disclosed in the special table 2002-517937 is large, given the above-mentioned “ultra-explosive enormous number of types of multi-value logic processing”, Since it is extremely insignificant, it has great significance to provide a multi-value logic circuit capable of executing “multi-value logic processing not yet realized” and “unknown multi-value logic processing”. For that reason, “There are multi-level logic processing functions that are not realized or unknown because there is a bidirectional switching means that limits the relationship between the input voltage and output voltage. There is a third problem.

Problem 4

“Other multi-value logic circuits and outlet means (eg, output terminals, output electrodes, drain electrodes, etc.) cannot be connected to develop and enhance multi-value logic functions, nor can they change functions.” In other words, there is a fourth problem that “it is desirable to be able to perform a multi-valued logic output method of releasing the output”.
Since the multi-value logic circuit of JP-T-2002-517937 prioritizes “small number of parts” and fixes its function, it is not possible to connect other multi-value logic circuits and exit means. If it is connected forcibly, a power supply short circuit will occur. For example, it is impossible to change the output voltage by connecting a pull-up resistor or a pull-down resistor.
Therefore, if there is an “opening output” method (for example, an output method called an open collector in a binary logic circuit) as a multi-value logic output method, a plurality of output values can be used as long as different output voltages are not output simultaneously. Connect the exit means of the multi-valued logic circuit freely {In some cases, connect the entrance means (eg, input terminal, input electrode, gate electrode, etc.) freely} By supplementing each other, the multi-value logic function can be flexibly developed and strengthened in accordance with “required multi-value logic processing”. For example, the output voltage can be freely changed by connecting a pull-up resistor or a pull-down resistor.
The flexible function development / enhancement capability and function change capability are very advantageous for flexibly responding to the above-mentioned “ultra-explosive enormous amount of multi-valued logic processing”.
That's why "You can't connect other multi-value logic circuits and exit means to develop and enhance multi-value logic functions, and you can't change functions", that is, "Multi-value logic that opens output" There is a fourth problem that it is desirable to be able to output.

Problem 5

There is a fifth problem that “it is desirable to understand the multi-valued logic processing function from a human language (eg, circuit name) or mathematical expression”.
As mentioned above, the number of types of multi-valued logic processing increases enormously and explosively, so it was not very memorable and couldn't cope with the fact that it was written in the truth table one by one. That is absolutely impossible. For example, the most convenient multi-decimal system for humans is the decimal system, but in the case of 10-value 1-digit 3-input / logic, there are 1,000 combinations of input variables, 10-value 1-digit 4-input. In the case of logic, there are 10,000 combinations of input variables.
Therefore, if we can know the multi-valued logic processing function immediately from a person's words (example: circuit name) or mathematical formulas (may be a new notation), it is kind to people and very convenient. It is indispensable for practical use of multi-adic control means such as a decimal computer. From another point of view, the present inventor considers that “the construction of a new algebra (multi-ary logic) instead of a binary Boolean algebra (binary logic)”.

  Note that each embodiment of the special table 2002-517937 is an application and development of the basic circuit of FIG. 2, and a plurality of P or N-channel gate-insulating types are employed depending on the number of input signals and the processing function of multi-value logic. Although FETs are complicatedly connected in series or connected in parallel, the basic operation of the normally-on bidirectional switching means is the same. In short, the method described in paragraph [0008] is used in a steady state after power-on. A plurality of bidirectional switching means are connected in series and in parallel to one intermediate potential, and at least one of them is used as described above. In this usage, even in the case of a logic circuit having four or more values, “bidirectional switching means having different potentials” are not simultaneously turned on in a steady state after power-on. However, when the output signal is switched at the time of switching the input signal, it may be turned on simultaneously in a transient manner. In the circuit of FIG. 2, the transistors Q1 to Q3 are simultaneously turned on while the input potential is between (2.5-1.75) = 0.75 volts and <5-3.25) = 1.75 volts. Then, the transistors Q2 to Q4 are simultaneously turned on even when the input potential is between 3.25 volts and (2.5 + 1.75) = 4.25 volts. Accordingly, it is necessary to prevent the input potential from being long and staying between these potentials. However, it is inevitable that the switching power loss increases due to the power supply short-circuit due to simultaneous ON when the input signal is switched.

Problem 6

The prior art of the present inventor (the following Patent Documents 2 and 3) is a technique for solving the problems 1 to 5 described above, and two examples thereof are shown in FIGS. In both cases, the switch terminal and the drive section are completely turned off in both directions. However, since both use bidirectional switching means in which a MOS-FET and a diode are connected in series at the output section, “the total on-voltage increases and the switching loss increases”. In addition, each power supply voltage must be increased in order to prevent a decrease in the magnitude of the output voltage as the total on-voltage increases. As a result, “the power loss of the entire circuit also increases”.
Therefore, there is a sixth problem that “the increase in the total on-voltage of the output unit increases the switching loss and also increases the power loss of the entire circuit”.

Problem 7

  In addition, the output potential drops when the total ON voltage increases due to that voltage pull-up, while the output potential rises when the voltage pull-down occurs, that is, `` plus or minus fluctuation based on the original output potential '' As a result of an increase in “error from the original output potential both at the time of pull-up and pull-down”, a logic circuit at the next stage or the like is likely to make an error in the “input numerical value corresponding to the input potential”. Therefore, there is a seventh problem that “the next-stage circuit is likely to mistake the input numerical value”.

Problem 8

  In addition, neither the pull-up diode nor the pull-down diode can be securely pulled smaller than the forward voltage due to the presence of the forward voltage, that is, neither the diode can be securely turned on because it cannot be voltage clamped (or voltage clamped). Since it is in an open state in the vicinity of the output potential, there is an eighth problem that “it is easy for noise to be applied to the output signal, and malfunction due to noise is likely to occur in the next stage circuit”.

Previous application

  Special table 2002-517937 (multi-valued logic circuit)   JP 2004-32702 (multi-valued logic circuit, filed by the present inventor)   Japanese Patent Application No. 2004-34260 (same as above)   Patent No. 3423780 (inventor's bidirectional insulated switch)   "Introduction to Transistor Circuit Lecture 5: Digital Circuit Concept" published by OHM Co., Ltd. on May 20, 1986. p. 34 “Table 3. 8 Logical functions consisting of two input variables”.

Related applications

  Patent No. 2853041 (inventor's multi-value storage means)   JP 2000-83369 (same as above)   JP 2001-257570 (same as above)   WO 03/028214 A1 (same as above)   JP 2003-188696 (same as above)   JP 2004-88763 (same as above)   Japanese Patent Application No. 2004-303564 (same as above)

Disclosure of the first invention

Problems to be solved by the first invention

Therefore, there are seven conventional problems as follows. (Task)
a) It is desirable to be able to configure without using a normally-on gate insulated FET.
b) In the case of a multi-value logic circuit having four or more values, a power supply short-circuit current flows transiently when the power is turned on.
c) Since bidirectional switching means for limiting the relationship between the input voltage and the output voltage is used, there are “unrealizable multilevel logic processing function” and “unknown multilevel logic processing function”.
d) It is desired that a multi-value logic output method of releasing the output can be performed.
e) The switching loss increases due to the increase in the total on-voltage of the output section, and the power loss of the entire circuit also increases.
f) The next stage circuit tends to mistake the input numerical value.
g) Noise is easily applied to the output signal, and malfunction due to noise is likely to occur in the next-stage circuit.

SUMMARY OF THE INVENTION Accordingly, an object of the first invention is to provide the following multi-value logic circuit.
(Object of the first invention)
a) It can be configured without using a normally-on gate insulated FET.
b) Only when a normally-off type is used for the bidirectional switching means of the output section, a transient power supply short-circuit current due to the normally-on type does not flow when the power is turned on even in the case of a multi-valued logic circuit having four or more values. .
c) There is also an option to enable execution of “a multi-value logic processing function that has not yet been realized” or “an unknown multi-value logic function”.
d) There is also an option of “how to open output” with multi-valued logic output.
e) The switching loss can be reduced by reducing the total on-voltage of the output section, and the power loss of the entire circuit can be reduced.
f) It is possible to make it difficult to make an error in the input numerical value of the next stage circuit.
g) Noise is difficult to ride on the output signal, and malfunction due to noise is unlikely to occur in the subsequent circuit.

Means to solve the problem

That is, the first invention is a multi-value logic circuit according to claim 1. Such an output means uses such a “combination of one or more bidirectional switching means and on / off driving means” that opens the outlet means in both directions during the off driving.
One means may also serve as a plurality of means. Further, the N indicates a multi-value (3 ≧) number, and generally the numerical value is 0 to (N−1). Generally, the first potential is defined as a numerical value 0, the second potential is defined as a numerical value 1,..., And the Nth potential is defined as a numerical value (N-1). If a certain signal potential is lower than “a positive threshold potential based on the first potential”, the signal potential means a numerical value of zero. If a signal potential is “between a negative threshold potential and a positive threshold potential with respect to the second potential”, the signal potential means the numerical value 1, and the signal potential is similarly If there is between both threshold potentials of each potential up to (N-1) potential, the signal potential means each numerical value up to numerical value (N-2). If a signal potential is higher than “a negative threshold potential with reference to the Nth potential”, the signal potential means a numerical value (N−1).

Effects of the first invention

As a result, it is not necessary to use both the discriminating means for discriminating the potential of the input signal and the bidirectional switching means for output (although of course, they can also be used). It becomes possible to configure even using normally-off type switching means. (Effect 1 of the first invention)
In addition, since normally-off type switching means is used in the output section, in the case of a four-value or more multi-value logic circuit, a transient power supply short-circuit current does not flow when the power is turned on, unlike the normally-on type. (Effect 2 of the first invention)
Further, since the “bidirectional switching means for outputting an intermediate potential between the second potential and the (N−1) th potential” is used for each of the “combination of bidirectional switching means and on / off driving means” as described above. Since the relationship between the input voltage and the output voltage is not limited, there is also an option to provide a multi-value logic circuit capable of executing “multi-value logic processing not yet realized” and “multi-value logic processing not yet known” To be able to (Effect 3 of the first invention)
In addition, since the above combination is used, it is possible to have an option of “how to release the output” with multi-valued logic output. (Effect 4 of the first invention)
In addition, the meaning of “being able to have options” means that “it may choose to execute a well-known multi-valued logic process depending on the embodiment” or “how to not open the output” It may mean that you may choose.
Then, "Same channel, two reverse-conducting, normally-off, gate-insulated FETs with their sources and gates connected to each other" or "Normally-off, four-terminal gate-insulating FET" for output Therefore, it is possible to reduce the total on-voltage of the output section, reduce the switching loss, and reduce the power loss of the entire circuit. (Effect 5 of the first invention)
Further, since the output potential, the positive and negative fluctuations of the voltage, and the error are reduced by reducing the total ON voltage of the output unit, it is possible to make it difficult to make an error in the input numerical value of the next stage circuit. (Effect 6 of the first invention)
In addition, since no diode is used for the output section, it can be pulled up and down firmly near the output potential and voltage, making it difficult for noise to be applied to the output signal and causing malfunctions due to noise in the next stage circuit. . (Effect 7 of the first invention)

Disclosure of the second invention

Problems to be solved by the second invention

Therefore, in addition to the above seven conventional problems (paragraph number 0020), there is one problem described below. (Task)
a) It is desired that the multi-valued logic processing function can be understood from a human language (eg, circuit name) or a mathematical expression (which may be a new notation).

  Therefore, the second invention has the effects of the first invention described above (paragraph number 0023) and “a multivalued logic processing function can be known from a person's word or mathematical expression”. The purpose is to provide. (Object of the second invention)

Means to solve the problem

That is, the second invention is a multi-value specific value logic circuit according to claim 2. The inventor introduces a specific value for input (each numerical value corresponding to one or more specific potentials for input) into the multi-value logic circuit of the first invention, and the numerical value discriminating means discriminates it. The relationship between “the numerical values corresponding to the respective potentials of the first inlet means to the S inlet means” and the input specific value is limited to “relation that can be expressed and expressed by human words or mathematical expressions”, and the relationship Is realized. The relationship to be discriminated is a numerical value “size relationship or vertical relationship”, “relationship between whether or not there is”, or “relationship between equality or inequality”. As a matter of course, the second invention has the effect that “the multi-valued logic processing function can be known from a person's word or mathematical expression”.
(Effect of the second invention)

  With respect to the “relation between equality and inequality” of numerical values, the “numerical value determination means for determining whether or not each numerical value corresponding to each potential of the first input means to Sth input means” is equal to or not equal to the specific value for input. Is determined. For this reason, the present inventor refers to the “multi-value specific value logic circuit for determining whether the numerical values are equal or not equal” as “multi-value specific value EQUAL circuit” and “multi-value specific value NOT circuit”. Named each one.

  Further, regarding the “relationship between whether or not there is” between the numerical values, it is determined whether “the numerical values corresponding to the respective potentials of the first input means to the S input means” are among the plurality of input specific values. Therefore, the present inventor has decided that “multi-value specific value logic circuit for determining whether there is a relationship between” “multi-value specific value BETWEEN circuit” and “multi-value specific value NOBETWEEN” circuit. And named each.

  With regard to the numerical value “magnitude relationship or vertical relationship”, “each numerical value corresponding to each potential of the first input means to S input means” is greater than or less than (or above or below) the specific value for input. The numerical value determining means determines whether there is a case. For this reason, the present inventor refers to “a multi-value specific value logic circuit for discriminating a magnitude relationship or a vertical relationship” as “a multi-value specific value OVER (over) circuit” and “a multi-value specific value NOVER (now bar) circuit”. , “Multi-value specific value UNDER (under) circuit” and “multi-value specific value NUNDER (nander) circuit”, respectively. The meaning of “OVER” means “above (or greater than) the specified value for input”, and the meaning of “NOVER” means “below (or smaller) or equal to or less than the specified value for input” because it is the negation of “OVER”. "Under" means "below (or smaller than) a specific value for input", and "NUNDER" means "Under", so it is "above (or greater than) or equal to a specific value for input" It means that.

Regarding the notation of mathematical formulas, for example, the following notation methods can be considered.
1) EQUAL (3) = 3
When [Numerical value of input signal = 3], the numerical value 3 is output. Otherwise, the output is released.
2) NOT (3) = 3
When [input signal value = 3], the output is released. Otherwise, the value 3 is output.
3) EQUAL (0, 2, 4, 6, 8) = 5
When [Numeric value of input signal = 0, 2, 4, 6, 8], the numerical value 5 is output. Otherwise, the output is released.
4) NOT (0, 2, 4, 6, 8) = 5
When [Numerical value of input signal = 0, 2, 4, 6, 8], the output is released. Otherwise, the numerical value 5 is output.
5) BETWEEN (4 & 7) = 5 or BETWEEN (4,7) = 5
When [4 <input signal value <7], the value 5 is output, otherwise the output is released.
6) NOBETWEEN (4 & 7) = 5 or NOBETWEEN (4,7) = 5
Since “NOBETWEEN” is negative of “BETWEEN”, the numerical value 5 is output when [input signal numerical value ≦ 4, 7 ≦ input signal numerical value], otherwise the output is released.
7) OVER (5) = 3
When [5 <input signal value], the value 3 is output, otherwise the output is released.
8) NOVER (5) = 3
Since “NOVER” is a negation of “OVER”, the numerical value 3 is output when [the numerical value of the input signal ≦ 5], and the output is released otherwise.
9) UNDER (7) = 4
[Numerical value of input signal <7] Outputs numerical value 4; otherwise, the output is released.
10) NUNDER (7) = 4
Since “NUNDER” is negative of “UNDER”, the numerical value 4 is output when [7 ≦ the numerical value of the input signal], and the output is released otherwise.
11) NOVER (4) = 2, EQUAL (5) = 4, NUNDER (6) = 6
A numerical value 2 is output when [input signal numerical value ≦ 4], a numerical value 4 is output when [input signal numerical value = 5], and a numerical value 6 is output when [6 ≦ input signal numerical value].

There are also a “multi-value specific value AND circuit”, “multi-value specific value NAND circuit”, “multi-value specific value OR circuit”, and “multi-value specific value NOR circuit”. The meanings of “AND” and “NAND” determine whether “all numerical values corresponding to the potentials of the first input means to the S input means” are equal to or not equal to the input specific value. The meanings of “OR” and “NOR” determine whether “any one of the numerical values corresponding to the potentials of the first input means to the S-th input means” is equal to or not equal to the input specific value. Regarding the notation of mathematical formulas, for example, the following notation methods can be considered.
1) AND (7) = 7
When [all numerical values of the input signal = 7], the numerical value 7 is output, otherwise the output is released.
2) AND (4) = 8
When [all numerical values of the input signal = 4], the numerical value 8 is output, otherwise the output is released.
3) NAND (4) = 8
When [all numerical values of the input signal = 4], the output is released, and if not, the numerical value 8 is output.
4) OR (4) = 8
When [any of the numerical values of the input signal = 4], the numerical value 8 is output, otherwise the output is released.
5) NOR <4) = 8
When [any of the numerical values of the input signal = 4], the output is released. Otherwise, the numerical value 8 is output.

Further, a combination of “AND”, “NAND”, “OR”, and “NOR” groups and “OVER”, “NOVER”, “UNDER”, and “NUNDER” groups is possible. “Multi-value specific value AND / OVER circuit”, “Multi-value specific value NAND / OVER circuit”, “Multi-value specific value AND / NOVER circuit”, “Multi-value specific value NAND / NOVER circuit”, “Multi-value specific value AND”・ Under circuit ”,“ Multi-value specific value NAND / UNDER circuit ”,“ Multi-value specific value AND / NUNDER circuit ”, and“ Multi-value specific value NAND / NUNDER circuit ”are all input above or below the specific value. (Or larger or smaller), and whether or not they may be equal.
On the other hand, “Multi-value specific value OR / OVER circuit”, “Multi-value specific value NOR / OVER circuit”, “Multi-value specific value OR / NOVER circuit”, “Multi-value specific value NOR / NOVER circuit”, “Multi-value specific” "Value OR / UNDER circuit", "Multi-value specific value NOR / UNDER circuit", "Multi-value specific value OR / NUNDER circuit", "Multi-value specific value NOR / NUNDER circuit" each of which is higher than the specific value It is determined whether it is below or below (or larger or smaller) and even more equal. However, each of the following has the same logical function.
a) Multi-value specific value AND / NUNDER circuit = Multi-value specific value NOR / UNDER circuit b) Multi-value specific value NAND / NUNDER circuit = Multi-value specific value OR / UNDER circuit c) Multi-value specific value OR / NUNDER circuit = Multi Value specific value NAND / UNDER circuit d) Multi-value specific value NOR / NUNDER circuit = Multi-value specific value AND / UNDER circuit e) Multi-value specific value AND / NOVER circuit = Multi-value specific value NOR / OVER circuit f) Multi-value specific Value NAND / NOVER circuit = multi-value specific value OR / OVER circuit g) multi-value specific value OR / NOVER circuit = multi-value specific value NAND / OVER circuit h) multi-value specific value NOR / NOVER circuit = multi-value specific value AND / OVER circuit

Similarly, a combination of “AND”, “NAND”, “OR”, “NOR” and “BETWEEN”, “NOBETWEEN” is also possible. “Multi-value specific value AND / BETWEEN circuit”, “Multi-value specific value NAND / BETWEEN circuit”, “Multi-value specific value AND / NOBETWEEN circuit”, “Multi-value specific value NAND / NOBETWEEN circuit” each have multiple inputs. It is determined whether it is between the input specific values.
On the other hand, each of “Multi-value specific value OR / BETWEEN circuit”, “Multi-value specific value NOR / BETWEEN circuit”, “Multi-value specific value OR / NOBETWEEN circuit”, and “Multi-value specific value NOR / NOBETWEEN circuit” It is determined whether or not (= at least one) is between a plurality of input specific values.

  In addition, about description of these numerical formulas etc., it is the same as that of the description method mentioned above. In addition, the expression on the circuit diagram may be expressed by the above-described mathematical formula or the like beside or in the frame of “for example, a square frame” or “a graphic symbol of the same logic circuit as in the past” as a circuit diagram symbol. Of course, a simplified expression such as a mathematical expression may be used.

Best Mode for Carrying Out Each Invention

  In order to explain each invention in more detail, these will be described with reference to the accompanying drawings. Note that the potential of the power supply line V0 is represented by the potential v0, the potential of the power supply line V1 is represented by the potential v1, and thereafter, similarly, each potential from the power supply line V2 to the power supply line V (n−1) is represented by a lowercase letter “v”. Each one is represented by a combination of “corresponding same numbers”.

FIG. 1 is an embodiment common to the first and second inventions, and is a multi-value logic circuit named the multi-value specific value EQUAL circuit (or multi-value specific value determination circuit) described above, and EQUAL (m) = m. N in the figure corresponds to the above-mentioned N, S = 1, and m is the specific value for input (each numerical value corresponding to “one or more specific potentials for input” in claim 2) and It also serves as a specific value for output (each numerical value corresponding to the potential of “one or more specific potential supply means” in claim 1).
In the embodiment of FIG. 1, each component corresponds to each component described in claims 1 and 2 as follows, and “n ≧ 3”, “n−1 ≧ m + 1”, “m−1 ≧ 0”. There is a relationship.
a) power supply line V0,..., power supply line V (m-1), power supply line Vm, power supply line V (m + 1), ..., power supply line V (n-1). For each of the potential supply means to the Nth potential supply means.
b) The input terminal In is the first inlet means to the S-th inlet means (where S = 1).
c) “The power source line V (m + 1), the power source line V (m−1), the connection body of the transistors 1 to 2, 17 and the resistor 19” is the numerical value discrimination means according to claim 1.
Note that the negative threshold potential of the specific value m is determined by the potential of the power supply line V (m−1) and the on / off threshold voltage of the transistor 2, and the positive threshold potential of the specific value m. Is determined by the potential of the power supply line V (m + 1) and the magnitude of the on / off threshold voltage of the transistor 1. In general, the negative threshold potential of the specific value m is not limited to the embodiment of FIG. 1 and is between the “potential of the power supply line Vm” and the “middle potential of both potentials of the power supply lines Vm · V (m−1)”. Is set. The positive threshold potential of the specific value m is set between “the middle potential of both the power supply lines V (m + 1) and Vm” and “the potential of the power supply line Vm”.
d) “Connected body of transistors 1, 17 and resistor 19” is the multi-value logic processing means according to claim 1.
e) The output terminal Out is the outlet means according to claim 1.
f) The potential of the power line Vm is the potential of “one or more specific potential supply means” in claim 1 and “one or more specific potentials for input” in claim 2.
g) “one or more bidirectional switching means connected between the power supply line Vm and the output terminal Out and configured by the transistors 3 to 4” is described as “one or more bidirectional switching means” in claim 1. .
h) The transistors 1 and 17 and the resistors 15 and 19 are the on / off driving means according to claim 1.

  The operation of the embodiment of FIG. 1 is as follows. If the potential of the input terminal In is between the “minus threshold potential with respect to the potential of the power supply line Vm and the plus threshold potential”, the transistors 1 and 2 are simultaneously turned on. , 19 turns on the transistors 3-4. As a result, the output terminal Out is bidirectionally connected to the power supply line Vm, so that the output terminal Out is connected bidirectionally to the power supply line Vm, and the output terminal Out outputs the potential of the power supply line Vm. On the other hand, if the potential of the input terminal In is not between both threshold potentials, one or both of the transistors 1 and 2 are turned off, and the resistor 15 drives the transistors 3 to 4 off, so that the output terminal Out is open. Become. With respect to the multi-value logic operation, the embodiment of FIG. 1 corresponds to the output specific value m (the potential of a specific potential supply means) when the numerical value of the input signal (the numerical value corresponding to the input potential) is equal to the input specific value m. When the numerical value of the input signal is not equal to the input specific value m, the output is released. In this embodiment, both specific values are the same.

  It should be noted that the output terminal Out is considered to be pulled up or pulled down to a “power supply line other than the power supply line Vm” or “a power supply line other than the power supply lines V0 to V (n−1)” by a resistor or the like. It is done. Further, a method of “preparing a plurality of embodiments in FIG. 1 having different specific values m common to the input and output, connecting the input terminals, and connecting the output terminals” is also conceivable. Further, instead of the resistor 15, “junction FET or normally-on type MOS • FET in which the gate and the source are directly connected” can be used one by one as the resistance means. Then, the relationships of “n ≧ 3”, “n−1 ≧ m + 1”, and “m−1 ≧ 0” are shown in FIGS. 5 to 13, 15, 17, 19, 21, and 26 described later. The same applies to the examples. An embodiment in which the drain of the transistor 3 is reconnected from the power supply line Vm to any one of the power supply line V0 to the power supply line V (m−1) is also possible, and this is the same in other embodiments. . An embodiment in which one end of the resistor 15 is reconnected to the power supply line V0 from the sources of the transistors 3 and 4 is also possible.

  By the way, in the embodiment of FIG. 1, an embodiment in which the source of the transistor 1 is reconnected from the power supply line V (m + 1) to any one of the power supply lines V (m + 2) to V (n−1) is possible. In addition, an embodiment in which the source of the transistor 2 is reconnected from the power supply line V (m−1) to any one of the power supply lines V (m−2) to V0 is possible. An embodiment in which the sources 1 and 2 are reconnected in the same manner as described above is also possible. In these cases, the embodiment of FIG. 1 becomes a multi-value specific value BETWEEN circuit. In the case of the embodiment of FIG. 1 and the like, the built-in diode and the channel are in parallel when each of the transistors 3 and 4 is on.

  The embodiment of FIG. 5 is a circuit having a symmetrical relationship with the embodiment of FIG. 1 in terms of voltage polarity or voltage direction. “In the embodiment of FIG. 1, the levels of the power supply potentials v0 to v (n−1) are made opposite to each other. Each transistor (controllable switching means) is replaced one by one with a complementary transistor, and the direction of each constituent means (eg, power supply, diode, etc.) having a voltage polarity or direction is reversed one by one. Circuit ". Accordingly, other embodiments described later also have “an embodiment having a symmetrical relationship with the embodiment in terms of voltage polarity or voltage direction”.

  The embodiment of FIG. 6 is an embodiment in which one four-terminal gate insulating FET is used as the bidirectional switching means, and is a multi-value specific value EQUAL circuit.

  The embodiment shown in FIG. 7A is a circuit obtained by simplifying the configuration of the embodiment shown in FIG.

  The embodiment shown in FIG. 7B is a circuit obtained by simplifying the configuration of the embodiment shown in FIG.

  The embodiment of FIG. 8A is also a circuit obtained by simplifying the configuration of the embodiment of FIG.

  The embodiment of FIG. 8B is also a circuit obtained by simplifying the configuration of the embodiment of FIG. 7B. “In the embodiment of FIG. It is also the circuit used. Similarly, in each embodiment shown in FIGS. 9 to 25 described later, an “embodiment using a four-terminal insulated FET instead of the same bidirectional switching means” is also possible.

The embodiment of FIG. 9 is a multi-value specific value NOT circuit, which is a circuit in which a “binary NOT circuit (inverter circuit) formed by a transistor 24 and a resistor 23” is inserted and connected to the embodiment of FIG. The diode 25 prevents “the current of the resistor 23 and the like from flowing toward the power supply line V (m−1)”. The diode 26 and the resistor 27 are for complete off driving of the transistor 24, but are unnecessary if the on / off threshold voltage of the transistor 24 is large and the off driving is easy.
In the embodiment of FIG. 9, an embodiment in which the source of the transistor 1 is reconnected from the power supply line V (m + 1) to any one of the power supply lines V (m + 2) to V (n−1) is also possible. In addition, an embodiment in which the source of the transistor 2 is reconnected from the power supply line V (m−1) to any one of the power supply lines V (m−2) to the power supply line V0 is possible. Embodiments in which the sources 1 and 2 are reconnected in the same manner as described above are also possible, in which case the embodiment of Fig. 9 becomes a multi-value specific value NOBETWEEN circuit.

  The embodiment of FIG. 10 is a logic circuit that is applied to the embodiment of FIG. 1 and is named “multi-value specific value AND circuit” by the present inventor. The output specific value m is output only when both numerical values of the input signal are the input specific value m. Otherwise, its output is freed. As described above, the specific value for output can be changed by reconnecting one end of the bidirectional switching means to a power supply line having a low potential other than the power supply line Vm. Then, as described above, the “PMOS source connected to the power supply line V (m + 1)” is reconnected to the “power supply line having a higher potential than the power supply line V (m + 1)” or “the power supply line V (m−1)”. 10) is connected to the “power source line having a potential lower than that of the power source line V (m−1)”, the embodiment of FIG. 10 becomes the “multi-value specific value AND / BETWEEN circuit”. Become.

  The embodiment of FIG. 11 is a multi-value specific value NAND circuit, which is a circuit in which the number of inputs is increased to 3 in the embodiment of FIG. 10 and a binary NOT circuit (inverter circuit) is inserted and connected in the same manner as described above. As described above, the output specific value can be changed by changing the connection of the power supply line of the bidirectional switching means. Similarly to the above, the embodiment of FIG. 11 becomes a multi-valued specific value NAND / BETWEEN circuit by changing the connection of the power source lines of the PMOS and NMOS sources for determining the input threshold potential.

  The embodiment of FIG. 12 is a logic circuit that the present inventor has named the “multi-value specific value OR circuit” to which the embodiment of FIG. 1 is applied. When any of the three numerical values (at least one) of the input signal is the input specific value m, the output specific value m is output. Otherwise, its output is freed. As described above, the specific value for output can be changed by reconnecting one end of the bidirectional switching means to the power supply line having a lower potential than the power supply line Vm. Further, as described above, the “sources of the three PMOSs connected to the power supply line V (m + 1)” are reconnected to the “power supply line having a higher potential than the power supply line V (m + 1)” or the “power supply line V (m -1) is reconnected to "a power supply line having a lower potential than the power supply line V (m-1)", the embodiment of FIG. BETWEEN circuit ".

  The embodiment of FIG. 13 is a multi-value specific value NOR circuit, and is a circuit in which a binary NOT circuit (inverter circuit) is inserted and connected in the same manner as in the embodiment of FIG. As described above, the output specific value can be changed by changing the connection of the power supply line of the bidirectional switching means. Similarly to the above, the embodiment of FIG. 13 becomes a multi-value specific value NOR / BETWEEN circuit by changing the connection of the power source lines of the three input threshold potential judging PMOSs and three NMOS sources.

The embodiment of FIG. 14 is a logic circuit named by the present inventor as a “multi-value specific value OVER circuit”. When the numerical value of the input signal is higher (larger) than the input specific value (m−1), the output specific value m is output. Otherwise the output is released. As described above, the specific value for output can be changed by reconnecting one end of the bidirectional switching means to a power supply line having a higher potential than the power supply line Vm. Also, as described above, if the “NMOS source connected to the power supply line V (m−1)” is reconnected to the “power supply line having a lower potential than the power supply line V (m−1)”, the specific value for input is changed. it can. In the embodiment of FIG. 14, the input on / off threshold potential is set to be higher than the positive threshold potential of the input specific value (m−1) and lower than the potential vm. It is also possible to set it higher than the threshold potential. In this case, the input specific value is m.
Note that “n ≧ 3”, “n−1 ≧ m”, and “m−1 ≧ 0”. These “changes in specific values for input and output and the relationship between n and m” are shown in FIGS. 16, 22 (a) and (b), and FIGS. 24 (a) and (b) described later. The same applies to each embodiment.

  The embodiment of FIG. 15 is also a logic circuit named by the present inventor as a “multi-value specific value OVER circuit”. When the numerical value of the input signal is higher (larger) than the input specific value (m−1), the output specific value m is output. Otherwise the output is released. As described above, the specific value for output can be changed by reconnecting one end of the bidirectional switching means to the power supply line having a lower potential than the power supply line Vm. Also, as described above, if the “NMOS source connected to the power supply line V (m−1)” is reconnected to the “power supply line having a lower potential than the power supply line V (m−1)”, the specific value for input is changed. it can. In the embodiment of FIG. 15, the input on / off threshold potential is set higher than the positive threshold potential of the input specific value (m−1) and lower than the potential vm. It is also possible to set it higher than the threshold potential. In this case, the input specific value is m.

  The embodiment of FIG. 16 is a logic circuit named by the present inventor as a “multi-value specific value NOVER circuit”, and is a circuit in which a binary NOT circuit is inserted and connected in the embodiment of FIG. When the numerical value of the input signal is higher than the input specific value (m−1) (when it is large), the output is released, and when not so, the output specific value m is output.

  The embodiment of FIG. 17 is a logic circuit named by the present inventor as a “multi-value specific value NOVER circuit”, and is a circuit in which a binary NOT circuit is inserted and connected in the embodiment of FIG. When the numerical value of the input signal is higher than the input specific value (m−1) (when it is large), the output is released, and when not so, the output specific value m is output. Note that “the change of each specific value for input and output is the same as in the embodiment of FIG. 15 described above.

  The embodiment of FIG. 18 is a logic circuit named by the present inventor as a “multi-value specific value UNDER circuit”. When the numerical value of the input signal is lower (smaller) than the input specific value (m + 1), the output specific value m is output. Otherwise the output is released. As described above, the specific value for output can be changed by reconnecting one end of the bidirectional switching means to the power supply line having a lower potential than the power supply line Vm. As described above, the input specific value can be changed by reconnecting the “PMOS source connected to the power supply line V (m + 1)” to the “power supply line having a higher potential than the power supply line V (m + 1)”. In the embodiment of FIG. 18, the on / off threshold potential of the input is set lower than the negative threshold potential of the input specific value (m + 1) and higher than the potential vm. It can be set lower than the threshold potential, and in this case, the specific value for input is m. Note that “n ≧ 3”, “n−1 ≧ m + 1”, and “m ≧ 0”. These “changes in specific values for input and output” and the relationship between n and m are shown in FIGS. 20, 23 (a) and (b), and FIGS. 25 (a) and (b) described later. The same applies to each embodiment.

  The embodiment of FIG. 19 is also a logic circuit named by the present inventor as a “multi-value specific value UNDER circuit”. When the numerical value of the input signal is lower (smaller) than the input specific value (m + 1), the output specific value m is output. Otherwise the output is released. As described above, the specific value for output can be changed by reconnecting one end of the bidirectional switching means to a power supply line having a higher potential than the power supply line Vm. As described above, the input specific value can be changed by reconnecting the “PMOS source connected to the power supply line V (m + 1)” to the “power supply line having a higher potential than the power supply line V (m + 1)”. In the embodiment of FIG. 19, the input on / off threshold potential is set lower than the negative threshold potential of the input specific value (m + 1) and higher than the potential vm, but the negative threshold of the numerical value m. It is also possible to set it lower than the value potential. In this case, the output specific value is m.

  The embodiment shown in FIG. 20 is a logic circuit named by the present inventor as a “multi-value specific value NUNDER circuit”. In the embodiment shown in FIG. 18, a binary NOT circuit is inserted and connected in the same manner as described above. When the numerical value of the input signal is lower (smaller) than the input specific value (m + 1), the output is released, otherwise the output specific value m is output.

  The embodiment shown in FIG. 21 is a logic circuit named by the present inventor as a “multi-value specific value NUNDER circuit”. In the embodiment shown in FIG. 19, a binary NOT circuit is inserted and connected in the same manner as described above. When the numerical value of the input signal is lower (smaller) than the input specific value (m + 1), the output is released, and when not, the output specific value m is output. Note that “the change of the specific values for input and output is the same as in the embodiment of FIG. 19 described above.

  The embodiment of FIG. 22A is a multi-value logic circuit named by the inventor as "multi-value specific value AND / OVER circuit". In the embodiment of FIG. Is a four-input multi-value logic circuit that is connected in series. When all the numerical values of the four input signals of the input terminals In1 to In4 are higher (larger) than the input specific value (m-1), the output specific value m is output. Otherwise the output is released.

  The embodiment of FIG. 22B is a multi-value logic circuit named by the present inventor as a “multi-value specific value NAND / OVER circuit”. In the embodiment of FIG. "4-input multi-value logic circuit in which four NMOSs are connected in series" and "a circuit in which a binary NOT circuit is inserted and connected in the embodiment of FIG. 22A". When all of the numerical values of the four input signals of the input terminals In1 to In4 are higher than the input specific value (m-1) (when larger), the output is released, otherwise the output specific value m is output.

  The embodiment of FIG. 23 (a) is a multi-value logic circuit named by the inventor as "multi-value specific value AND / UNDER circuit". In the embodiment of FIG. Is a four-input multi-value logic circuit that is connected in series. When all the numerical values of the four input signals of the input terminals In1 to In4 are lower (smaller) than the input specific value (m + 1), the output specific value m is output. Otherwise the output is released.

    The embodiment of FIG. 23B is a multi-value logic circuit named by the present inventor as a “multi-value specific value NAND / UNDER circuit”. In the embodiment of FIG. "4-input multi-value logic circuit in which four NMOSs are connected in series" and "a circuit in which a binary NOT circuit is inserted and connected in the embodiment of FIG. 23A". When all the numerical values of the four input signals of the input terminals In1 to In4 are lower (smaller) than the input specific value (m + 1), the output is released, otherwise the output specific value m is output.

  The embodiment shown in FIG. 24A is a multi-value logic circuit named by the inventor as "multi-value specific value OR / OVER circuit". In the embodiment shown in FIG. 14, four NMOSs for determining the input threshold potential are used. Are four-input multi-value logic circuits connected in parallel. The output specific value m is output when at least one of the numerical values of the four input signals of the input terminals In1 to In4 is higher (larger) than the input specific value (m-1). Otherwise the output is released.

  The embodiment of FIG. 24B is a multi-value logic circuit named by the present inventor as a “multi-value specific value NOR / OVER circuit”. In the embodiment of FIG. "4-input multi-value logic circuit in which four NMOSs are connected in parallel" and "a circuit in which a binary NOT circuit is inserted and connected in the embodiment of FIG. 24A". When at least one of the numerical values of the four input signals of the input terminals In1 to In4 is higher than the input specific value (m-1) (when it is larger), the output is released, otherwise, the output specific value m is output. Is done.

  The embodiment of FIG. 25 (a) is a multi-value logic circuit named by the inventor as "multi-value specific value OR / UNDER circuit". In the embodiment of FIG. Are four-input multi-value logic circuits connected in parallel. The output specific value m is output when at least one of the numerical values of the four input signals of the input terminals In1 to In4 is lower (smaller) than the input specific value (m + 1). Otherwise the output is released.

    The embodiment of FIG. 25B is a multi-value logic circuit named by the present inventor as a “multi-value specific value NOR / UNDER circuit”. In the embodiment of FIG. "4-input multi-value logic circuit in which four NMOSs are connected in parallel" and "a circuit in which a binary NOT circuit is inserted and connected in the embodiment of FIG. 25A". When at least one of the numerical values of the four input signals of the input terminals In1 to In4 is lower (smaller) than the input specific value (m + 1), the output is released, otherwise the output specific value m is output. .

  The embodiment of FIG. 26 is a multi-value logic circuit named by the present inventor as a “multi-value specific value AND circuit”. In the embodiment of FIG. 7A, the input threshold potential is the same as the embodiment of FIG. This is a “three-input multi-value logic circuit in which three PMOSs and NMOSs for discrimination are connected in series.” When all three numerical values of the input signals of the input terminals In1 to In3 are equal to the input specific value m, the output specific value m is output, otherwise the output is released. In the embodiment of FIG. 26, if a binary NOT circuit is inserted and connected as in the embodiment of FIG. 11 with respect to the embodiment of FIG. 10, a multi-value specific value NAND circuit is obtained.

  The embodiment shown in FIG. 27 is a multi-value logic circuit named by the present inventor as a “multi-value specific value OR circuit”. In the embodiment shown in FIG. And a three-input multi-value logic circuit in which three NMOSs are connected in series. The output specific value m is output when at least one of the numerical values of the three input signals of the input terminals In1 to In3 is equal to the input specific value m, otherwise the output is released. In the embodiment of FIG. 27, if a binary NOT circuit is inserted and connected as in the embodiment of FIG. 13 with respect to the embodiment of FIG. 12, a multi-value specific value NAND circuit is obtained.

reference. Each of the circuits in FIGS. 28 to 31 is not an embodiment but a multi-value logic circuit combined with the embodiment of the present invention. The circuit of FIG. 28 is a multi-value specific value AND circuit having a numerical value n for both input and output specific values. The circuit of FIG. 29 is a multi-value specific value AND circuit having a numerical value 0 for both input and output specific values. The circuit shown in FIG. 31 is a multi-value specific value OR circuit having a numerical value n for both input and output specific values, and the circuit in FIG. 31 is a multi-value specific value OR circuit having a numerical value 0 for both input and output.
In the circuit of FIG. 28, if three NMOSs and the rightmost PMOS are removed and the drain terminals of the remaining three PMOSs are used as output terminals, both input and output specific values become a multi-value specific value NAND circuit with a numerical value n. In the circuit of FIG. 29, when three PMOSs and the rightmost NMOS are removed and the drain terminals of the remaining three NMOSs are used as output terminals, both the input and output specific values become a multi-value specific value NAND circuit having a numerical value of zero. In the circuit of FIG. 30, when three NMOSs and the rightmost PMOS are removed and the open drain terminal of the remaining three PMOSs is used as an output terminal, both the input specific value and the output specific value become a multi-value specific value NOR circuit with a numerical value n. Become. When the three PMOSs and the rightmost NMOS in the figure are removed in the concave path of FIG. 31, and the open drain terminal of the remaining three NMOS series circuits is used as the output terminal, the input and output specific values are both multi-value specific value NOR circuits with numerical values 0 become.

  An embodiment of the embodiment 31 named by the present inventor as "multi-value AND circuit" will be described. For example, “n = 10 and m is 1 to 8 in“ the embodiment of FIG. 26 ”or“ the embodiment of FIG. 10 in which the number of inputs is three ”is eight”, “n = 10 in FIG. 29 "and" one circuit of FIG. 29 where n = 10 "are prepared, 10 input terminals In1, 10 input terminals In2, 10 input terminals In3, and 10 output terminals Out. Are connected to each other to form new input terminals In1 to In3 and an output terminal Out, a 10-value 3-input multi-value AND circuit can be formed. In this case, if all the “numerical values corresponding to the potentials of the input terminals In1 to In3” are the same, the “potential (or voltage) corresponding to the numerical values” is output from the output terminal Out. That is, regarding the logical operation, the embodiment 31 outputs the same numerical value when all three input numerical values are the same, and releases the output when even one of the numerical values is different.

  Thus, in the case of the first and second inventions, as long as “different potentials”, that is, “different values” are not output simultaneously, the output terminals and the input terminals of a plurality of multi-value logic circuits are connected to each other. Logical processing capability can be developed and strengthened. In addition, for example, “a specific value for both input and output is a numerical value (m + 1) multi-value specific value NUNDER circuit”, “a specific value for both input and output is a multi-value specific value determination circuit with a numerical value m”, and If the input terminals and output terminals of the "multi-value specific value NOVER circuit with both input and output specific values are numerical values (m-1)" are connected, "input signal numerical value ≥ numerical value (m + 1) "Numerical value (m + 1) is output", "Numerical value m is output when numerical value of input signal = numerical value m", and "Numerical value (m-1) is output when numerical value of input signal ≤ Numerical value (m-1)" The multi-value logic circuit can be configured. Such characteristics are suitable for neurocomputers.

Finally, the following will be supplemented.
a) In the embodiments of FIGS. 10 to 13 and FIGS. 22 to 27, if the input threshold potential is changed for each input terminal, the multi-value logic processing function is further developed.
b) In the case of the present invention, it is not necessary to change the circuit configuration regardless of the number of multi-values (N of N values), and the same circuit configuration may be used regardless of 5 values, 10 values, or 100 values. , Freedom, flexibility, responsiveness. You just need to change the connection of the power line to connect.
c) In the present invention, since the multi-value logic output method of releasing the output can also be selected, the exit means (eg, output terminal etc.) can be selected by a resistor or the like other than “specific potential supply means (eg: power supply line) Vm. The output voltage can be freely changed by pulling up or down to “potential supply means other than“ potential supply means V0 to V (n−1) ”.
d) Although called inlet means and outlet means for the sake of convenience of explanation, they do not exist as terminals, and are often simple wires or electrodes. This is the same as what is called a base terminal, a base electrode, and a base lead wire of a transistor, for example.
e) The mathematical explanation of the number of types of multi-valued logic processing described above (paragraph number 0009) in the mathematical explanation regarding the super-explosive bubble size has been described conservatively in the case of two digits, but the number of digits and input As the number increases, it becomes "super, super, ... super, explosive size." For example, if there are 10 values, 1 digit and 3 inputs, there are 10-thousand powers of multi-value logic processing and multi-valued logic functions. There are multi-valued logic processing and multi-valued logic functions of “10 millions of powers” with 3 inputs, which are exactly “super-astronomical numbers”. Practically, it is a saying even if it is “infinite”, there is anything, and there is no logical processing that cannot be done (???).
On the other hand, in the case of "future binary quantum computer", which is said to be very difficult to maintain quantum coherency, even if it says "calculation speed is fast", it is "tens of 10" times . “Diversity of processing super-astronomical numbers” and “computation speed of tens of powers of 10” are not directly compared, but a decimal computer might be more advantageous.
f) Three-dimensional IC technology, low voltage technology, etc. strongly assist the practical application of “multi-ary logic circuits, multi-ary arithmetic circuits, multi-ary memory circuits, multi-adic computers, etc.”. If three-dimensional IC technology, low voltage drive and withstand voltage maintenance technology, energy saving technology, cooling technology, etc. will continue to advance in the future, 64 base, 100 base, 128 base logic circuits, arithmetic circuits, memory Circuits, computers, etc. will also be possible, and there may be 64, 100, 128, super, super, super, ultra, and super computers.

g) By the way, the decimal computer “DC” (Decimal Computer) eliminates, prevents, or alleviates the “syndrome called“ computer over-adaptation ”caused by the current binary computer” Or it is expected to be cured. In “Computer Over-Adaptation”, “0” becomes the same as the binary thinking of a computer that has only “1”, and communication with “others who leave ambiguous room” becomes impossible. Gets worse.
Reference: p. Of the morning edition dated March 11, 2002 of the Nihon Keizai Shimbun (Tokyo edition). 34 “Musoba techno stress”.
This means that “multi-decimal, especially decimal, is better for building human-friendly, human-friendly computers, neuro-computers or artificial intelligence” and “multi-decimal, especially decimal, for fuzzy control. Suggests that “is better.”
However, these things may apply to Asians such as Japan with a “culture that expresses ambiguous expression”, and may not apply to Western countries that have “a culture that expresses YES and NO clearly”. If so, “Isn't the multi-adic computer etc. a good field for Asians like Japan? ? ].
h) If the number of input terminals of the embodiment 31 (refer to paragraph number 0070) named by the present inventor as “multi-value AND circuit” is set to one and the input terminal and the output terminal are connected, 10-value memory, 10-value A memory cell and a 10-value storage means can be configured. Similarly, multi-value storage means having different multi-value numbers can be configured by changing the multi-value number (N of N values).
i) For example, a plurality of ten-value or more multi-value storage means are used in decimal decimal numbers, and the 11-value and 12-value portions other than 10 values are used for plus / minus sign or parity check. It is also possible. For this reason, a multi-value number and a multi-adic number (N in N-ary system) do not always match. The present inventor believes that it is more correct to call it "multi-adic computer etc.". Actually, a binary circuit using a quaternary memory has been put into practical use.
j) Even when the power consumption and the number of parts are larger than those of the binary system in multi-ary logic circuits, multi-adic computers, etc., these performances can be compensated for and even higher performance and advantages. If there is, there is value in practical use. One of the advantages of the above-mentioned “human-friendly” is that the amount of information that can be sent and the amount of information that can be handled with the same number of data lines. Other advantages are that there is no error and that the number of carry and carry is small. There are others.
k) Supplementary description will be made regarding effect 3 (paragraph number 0023) of the first invention.
“A circuit in which the transistors Q1 and Q4 are removed from the conventional circuit of FIG. 2”, that is, “a circuit of bidirectional switching means connected to an intermediate potential between the lowest potential and the highest potential” is shown in FIGS. Although it corresponds to each embodiment, as described above (paragraph number 0008), its usage is limited and it cannot be used alone. On the other hand, each embodiment shown in each of FIGS. 1 to 8 does not have such usage restrictions and can be used freely. That is, these embodiments have a “multi-valued logic processing function that cannot be realized by a conventional circuit”.
Further, the output function of the complementary output, such as “multi-value specific value NOT circuit”, “multi-value specific value NAND circuit” and “multi-value specific value NOR circuit” in the second invention, is also “multi-value that cannot be realized by the conventional circuit”. "Logic processing function" or "Unknown multi-value logic processing function". Furthermore, the same multi-value logic processing function as the “multi-value specific value OVER circuit”, “multi-value specific value UNDER circuit”, “multi-value specific value NOVER circuit”, “multi-value specific value NUNDER circuit”, etc. of the second invention is provided. There is no conventional circuit. This is especially true for circuits that output a specific potential bidirectionally.
l) In the conventional circuit of FIG. 2, the transistors Q2 and Q3 can be removed, and one of the embodiments shown in FIGS. 1 to 8 can be combined instead. On the other hand, a circuit in which n = 3 instead of n = 10 in Example 31 (paragraph 0070) is also possible.
As described above, the present invention has a high degree of freedom and response capability, and can be freely developed, strengthened or changed.

It is a circuit diagram showing one embodiment common to the first and second inventions. It is a circuit diagram which shows one example of the conventional multi-value logic circuit.

Claims (2)

When a predetermined plural number of 3 or 3 is represented by N and a predetermined natural number is represented by S,
“First potential supply means for supplying“ N potentials that are defined to correspond to N numerical values one by one and increase in order of numbers from the first potential to the Nth potential ”to Nth potential supply Means "
"First input means to S input means serving as S input signal inlets";
“The numerical values corresponding to the potentials of the first inlet means to the S inlet means” are predetermined multi-valued logic based on the positive or negative threshold potential with respect to each of the N potentials. Numeric value discriminating means for discriminating which one of the input numeric values used in or which one corresponds to ",
"Multi-value logic processing means for performing the predetermined multi-value logic according to the discrimination output signal of the numerical value discrimination means";
"Exit means to be the output of the logic output signal",
"One or more of the second potential supply means to the (N-1) th potential supply means, one or more specific potential supply means and one outlet connected between each of the outlet means""Bidirectional switching means",
“ON / OFF drive means controlled by the multi-value logic processing means to drive each of the“ one or more bidirectional switching means ”ON / OFF”,
In a multi-value logic circuit having
Each of the “one or more bidirectional switching means” is “the same channel, two reverse-conductive, normally-off gate-insulated FETs connected at their sources” or “normally-off four terminals” Using `` gate insulated FET ''
As the on / off driving means, “the one in which no current flows in the reverse conduction direction or the conduction direction between the back gate and the source and between the back gate and the drain of the four-terminal gate insulated FET during the off driving” is used. A multi-value logic circuit characterized by that. The multi-value logic circuit according to claim 1, wherein
The numerical value discriminating means is based on “the positive side or the negative side threshold potential with reference to each of one or a plurality of input specific potentials among the N potentials”. The relationship between each numerical value corresponding to each potential of the S inlet means and each numerical value of the one or more input specific potentials, the vertical relationship, the relationship between whether or not, or equal but not equal A multi-value specific value logic circuit characterized by determining the relationship.

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